1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988-2021 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
24 modified by John Hassey (hassey@dg-rtp.dg.com)
25 x86-64 support added by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
28 /* The main tables describing the instructions is essentially a copy
29 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30 Programmers Manual. Usually, there is a capital letter, followed
31 by a small letter. The capital letter tell the addressing mode,
32 and the small letter tells about the operand size. Refer to
33 the Intel manual for details. */
36 #include "disassemble.h"
38 #include "opcode/i386.h"
39 #include "libiberty.h"
40 #include "safe-ctype.h"
44 static int print_insn (bfd_vma
, disassemble_info
*);
45 static void dofloat (int);
46 static void OP_ST (int, int);
47 static void OP_STi (int, int);
48 static int putop (const char *, int);
49 static void oappend (const char *);
50 static void append_seg (void);
51 static void OP_indirE (int, int);
52 static void print_operand_value (char *, int, bfd_vma
);
53 static void OP_E_register (int, int);
54 static void OP_E_memory (int, int);
55 static void print_displacement (char *, bfd_vma
);
56 static void OP_E (int, int);
57 static void OP_G (int, int);
58 static bfd_vma
get64 (void);
59 static bfd_signed_vma
get32 (void);
60 static bfd_signed_vma
get32s (void);
61 static int get16 (void);
62 static void set_op (bfd_vma
, int);
63 static void OP_Skip_MODRM (int, int);
64 static void OP_REG (int, int);
65 static void OP_IMREG (int, int);
66 static void OP_I (int, int);
67 static void OP_I64 (int, int);
68 static void OP_sI (int, int);
69 static void OP_J (int, int);
70 static void OP_SEG (int, int);
71 static void OP_DIR (int, int);
72 static void OP_OFF (int, int);
73 static void OP_OFF64 (int, int);
74 static void ptr_reg (int, int);
75 static void OP_ESreg (int, int);
76 static void OP_DSreg (int, int);
77 static void OP_C (int, int);
78 static void OP_D (int, int);
79 static void OP_T (int, int);
80 static void OP_MMX (int, int);
81 static void OP_XMM (int, int);
82 static void OP_EM (int, int);
83 static void OP_EX (int, int);
84 static void OP_EMC (int,int);
85 static void OP_MXC (int,int);
86 static void OP_MS (int, int);
87 static void OP_XS (int, int);
88 static void OP_M (int, int);
89 static void OP_VEX (int, int);
90 static void OP_VexR (int, int);
91 static void OP_VexW (int, int);
92 static void OP_Rounding (int, int);
93 static void OP_REG_VexI4 (int, int);
94 static void OP_VexI4 (int, int);
95 static void PCLMUL_Fixup (int, int);
96 static void VPCMP_Fixup (int, int);
97 static void VPCOM_Fixup (int, int);
98 static void OP_0f07 (int, int);
99 static void OP_Monitor (int, int);
100 static void OP_Mwait (int, int);
101 static void NOP_Fixup1 (int, int);
102 static void NOP_Fixup2 (int, int);
103 static void OP_3DNowSuffix (int, int);
104 static void CMP_Fixup (int, int);
105 static void BadOp (void);
106 static void REP_Fixup (int, int);
107 static void SEP_Fixup (int, int);
108 static void BND_Fixup (int, int);
109 static void NOTRACK_Fixup (int, int);
110 static void HLE_Fixup1 (int, int);
111 static void HLE_Fixup2 (int, int);
112 static void HLE_Fixup3 (int, int);
113 static void CMPXCHG8B_Fixup (int, int);
114 static void XMM_Fixup (int, int);
115 static void FXSAVE_Fixup (int, int);
117 static void MOVSXD_Fixup (int, int);
119 static void OP_Mask (int, int);
122 /* Points to first byte not fetched. */
123 bfd_byte
*max_fetched
;
124 bfd_byte the_buffer
[MAX_MNEM_SIZE
];
127 OPCODES_SIGJMP_BUF bailout
;
137 enum address_mode address_mode
;
139 /* Flags for the prefixes for the current instruction. See below. */
142 /* REX prefix the current instruction. See below. */
144 /* Bits of REX we've already used. */
146 /* Mark parts used in the REX prefix. When we are testing for
147 empty prefix (for 8bit register REX extension), just mask it
148 out. Otherwise test for REX bit is excuse for existence of REX
149 only in case value is nonzero. */
150 #define USED_REX(value) \
155 rex_used |= (value) | REX_OPCODE; \
158 rex_used |= REX_OPCODE; \
161 /* Flags for prefixes which we somehow handled when printing the
162 current instruction. */
163 static int used_prefixes
;
165 /* Flags stored in PREFIXES. */
166 #define PREFIX_REPZ 1
167 #define PREFIX_REPNZ 2
168 #define PREFIX_LOCK 4
170 #define PREFIX_SS 0x10
171 #define PREFIX_DS 0x20
172 #define PREFIX_ES 0x40
173 #define PREFIX_FS 0x80
174 #define PREFIX_GS 0x100
175 #define PREFIX_DATA 0x200
176 #define PREFIX_ADDR 0x400
177 #define PREFIX_FWAIT 0x800
179 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
180 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
182 #define FETCH_DATA(info, addr) \
183 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
184 ? 1 : fetch_data ((info), (addr)))
187 fetch_data (struct disassemble_info
*info
, bfd_byte
*addr
)
190 struct dis_private
*priv
= (struct dis_private
*) info
->private_data
;
191 bfd_vma start
= priv
->insn_start
+ (priv
->max_fetched
- priv
->the_buffer
);
193 if (addr
<= priv
->the_buffer
+ MAX_MNEM_SIZE
)
194 status
= (*info
->read_memory_func
) (start
,
196 addr
- priv
->max_fetched
,
202 /* If we did manage to read at least one byte, then
203 print_insn_i386 will do something sensible. Otherwise, print
204 an error. We do that here because this is where we know
206 if (priv
->max_fetched
== priv
->the_buffer
)
207 (*info
->memory_error_func
) (status
, start
, info
);
208 OPCODES_SIGLONGJMP (priv
->bailout
, 1);
211 priv
->max_fetched
= addr
;
215 /* Possible values for prefix requirement. */
216 #define PREFIX_IGNORED_SHIFT 16
217 #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
218 #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
219 #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
220 #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
221 #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
223 /* Opcode prefixes. */
224 #define PREFIX_OPCODE (PREFIX_REPZ \
228 /* Prefixes ignored. */
229 #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \
230 | PREFIX_IGNORED_REPNZ \
231 | PREFIX_IGNORED_DATA)
233 #define XX { NULL, 0 }
234 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
236 #define Eb { OP_E, b_mode }
237 #define Ebnd { OP_E, bnd_mode }
238 #define EbS { OP_E, b_swap_mode }
239 #define EbndS { OP_E, bnd_swap_mode }
240 #define Ev { OP_E, v_mode }
241 #define Eva { OP_E, va_mode }
242 #define Ev_bnd { OP_E, v_bnd_mode }
243 #define EvS { OP_E, v_swap_mode }
244 #define Ed { OP_E, d_mode }
245 #define Edq { OP_E, dq_mode }
246 #define Edqw { OP_E, dqw_mode }
247 #define Edqb { OP_E, dqb_mode }
248 #define Edb { OP_E, db_mode }
249 #define Edw { OP_E, dw_mode }
250 #define Edqd { OP_E, dqd_mode }
251 #define Eq { OP_E, q_mode }
252 #define indirEv { OP_indirE, indir_v_mode }
253 #define indirEp { OP_indirE, f_mode }
254 #define stackEv { OP_E, stack_v_mode }
255 #define Em { OP_E, m_mode }
256 #define Ew { OP_E, w_mode }
257 #define M { OP_M, 0 } /* lea, lgdt, etc. */
258 #define Ma { OP_M, a_mode }
259 #define Mb { OP_M, b_mode }
260 #define Md { OP_M, d_mode }
261 #define Mo { OP_M, o_mode }
262 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
263 #define Mq { OP_M, q_mode }
264 #define Mv { OP_M, v_mode }
265 #define Mv_bnd { OP_M, v_bndmk_mode }
266 #define Mx { OP_M, x_mode }
267 #define Mxmm { OP_M, xmm_mode }
268 #define Gb { OP_G, b_mode }
269 #define Gbnd { OP_G, bnd_mode }
270 #define Gv { OP_G, v_mode }
271 #define Gd { OP_G, d_mode }
272 #define Gdq { OP_G, dq_mode }
273 #define Gm { OP_G, m_mode }
274 #define Gva { OP_G, va_mode }
275 #define Gw { OP_G, w_mode }
276 #define Ib { OP_I, b_mode }
277 #define sIb { OP_sI, b_mode } /* sign extened byte */
278 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
279 #define Iv { OP_I, v_mode }
280 #define sIv { OP_sI, v_mode }
281 #define Iv64 { OP_I64, v_mode }
282 #define Id { OP_I, d_mode }
283 #define Iw { OP_I, w_mode }
284 #define I1 { OP_I, const_1_mode }
285 #define Jb { OP_J, b_mode }
286 #define Jv { OP_J, v_mode }
287 #define Jdqw { OP_J, dqw_mode }
288 #define Cm { OP_C, m_mode }
289 #define Dm { OP_D, m_mode }
290 #define Td { OP_T, d_mode }
291 #define Skip_MODRM { OP_Skip_MODRM, 0 }
293 #define RMeAX { OP_REG, eAX_reg }
294 #define RMeBX { OP_REG, eBX_reg }
295 #define RMeCX { OP_REG, eCX_reg }
296 #define RMeDX { OP_REG, eDX_reg }
297 #define RMeSP { OP_REG, eSP_reg }
298 #define RMeBP { OP_REG, eBP_reg }
299 #define RMeSI { OP_REG, eSI_reg }
300 #define RMeDI { OP_REG, eDI_reg }
301 #define RMrAX { OP_REG, rAX_reg }
302 #define RMrBX { OP_REG, rBX_reg }
303 #define RMrCX { OP_REG, rCX_reg }
304 #define RMrDX { OP_REG, rDX_reg }
305 #define RMrSP { OP_REG, rSP_reg }
306 #define RMrBP { OP_REG, rBP_reg }
307 #define RMrSI { OP_REG, rSI_reg }
308 #define RMrDI { OP_REG, rDI_reg }
309 #define RMAL { OP_REG, al_reg }
310 #define RMCL { OP_REG, cl_reg }
311 #define RMDL { OP_REG, dl_reg }
312 #define RMBL { OP_REG, bl_reg }
313 #define RMAH { OP_REG, ah_reg }
314 #define RMCH { OP_REG, ch_reg }
315 #define RMDH { OP_REG, dh_reg }
316 #define RMBH { OP_REG, bh_reg }
317 #define RMAX { OP_REG, ax_reg }
318 #define RMDX { OP_REG, dx_reg }
320 #define eAX { OP_IMREG, eAX_reg }
321 #define AL { OP_IMREG, al_reg }
322 #define CL { OP_IMREG, cl_reg }
323 #define zAX { OP_IMREG, z_mode_ax_reg }
324 #define indirDX { OP_IMREG, indir_dx_reg }
326 #define Sw { OP_SEG, w_mode }
327 #define Sv { OP_SEG, v_mode }
328 #define Ap { OP_DIR, 0 }
329 #define Ob { OP_OFF64, b_mode }
330 #define Ov { OP_OFF64, v_mode }
331 #define Xb { OP_DSreg, eSI_reg }
332 #define Xv { OP_DSreg, eSI_reg }
333 #define Xz { OP_DSreg, eSI_reg }
334 #define Yb { OP_ESreg, eDI_reg }
335 #define Yv { OP_ESreg, eDI_reg }
336 #define DSBX { OP_DSreg, eBX_reg }
338 #define es { OP_REG, es_reg }
339 #define ss { OP_REG, ss_reg }
340 #define cs { OP_REG, cs_reg }
341 #define ds { OP_REG, ds_reg }
342 #define fs { OP_REG, fs_reg }
343 #define gs { OP_REG, gs_reg }
345 #define MX { OP_MMX, 0 }
346 #define XM { OP_XMM, 0 }
347 #define XMScalar { OP_XMM, scalar_mode }
348 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
349 #define XMM { OP_XMM, xmm_mode }
350 #define TMM { OP_XMM, tmm_mode }
351 #define XMxmmq { OP_XMM, xmmq_mode }
352 #define EM { OP_EM, v_mode }
353 #define EMS { OP_EM, v_swap_mode }
354 #define EMd { OP_EM, d_mode }
355 #define EMx { OP_EM, x_mode }
356 #define EXbwUnit { OP_EX, bw_unit_mode }
357 #define EXw { OP_EX, w_mode }
358 #define EXd { OP_EX, d_mode }
359 #define EXdS { OP_EX, d_swap_mode }
360 #define EXq { OP_EX, q_mode }
361 #define EXqS { OP_EX, q_swap_mode }
362 #define EXx { OP_EX, x_mode }
363 #define EXxS { OP_EX, x_swap_mode }
364 #define EXxmm { OP_EX, xmm_mode }
365 #define EXymm { OP_EX, ymm_mode }
366 #define EXtmm { OP_EX, tmm_mode }
367 #define EXxmmq { OP_EX, xmmq_mode }
368 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
369 #define EXxmm_mb { OP_EX, xmm_mb_mode }
370 #define EXxmm_mw { OP_EX, xmm_mw_mode }
371 #define EXxmm_md { OP_EX, xmm_md_mode }
372 #define EXxmm_mq { OP_EX, xmm_mq_mode }
373 #define EXxmmdw { OP_EX, xmmdw_mode }
374 #define EXxmmqd { OP_EX, xmmqd_mode }
375 #define EXymmq { OP_EX, ymmq_mode }
376 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
377 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
378 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
379 #define MS { OP_MS, v_mode }
380 #define XS { OP_XS, v_mode }
381 #define EMCq { OP_EMC, q_mode }
382 #define MXC { OP_MXC, 0 }
383 #define OPSUF { OP_3DNowSuffix, 0 }
384 #define SEP { SEP_Fixup, 0 }
385 #define CMP { CMP_Fixup, 0 }
386 #define XMM0 { XMM_Fixup, 0 }
387 #define FXSAVE { FXSAVE_Fixup, 0 }
389 #define Vex { OP_VEX, vex_mode }
390 #define VexW { OP_VexW, vex_mode }
391 #define VexScalar { OP_VEX, vex_scalar_mode }
392 #define VexScalarR { OP_VexR, vex_scalar_mode }
393 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
394 #define VexGdq { OP_VEX, dq_mode }
395 #define VexTmm { OP_VEX, tmm_mode }
396 #define XMVexI4 { OP_REG_VexI4, x_mode }
397 #define XMVexScalarI4 { OP_REG_VexI4, scalar_mode }
398 #define VexI4 { OP_VexI4, 0 }
399 #define PCLMUL { PCLMUL_Fixup, 0 }
400 #define VPCMP { VPCMP_Fixup, 0 }
401 #define VPCOM { VPCOM_Fixup, 0 }
403 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
404 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
405 #define EXxEVexS { OP_Rounding, evex_sae_mode }
407 #define XMask { OP_Mask, mask_mode }
408 #define MaskG { OP_G, mask_mode }
409 #define MaskE { OP_E, mask_mode }
410 #define MaskBDE { OP_E, mask_bd_mode }
411 #define MaskVex { OP_VEX, mask_mode }
413 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
414 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
416 #define MVexSIBMEM { OP_M, vex_sibmem_mode }
418 /* Used handle "rep" prefix for string instructions. */
419 #define Xbr { REP_Fixup, eSI_reg }
420 #define Xvr { REP_Fixup, eSI_reg }
421 #define Ybr { REP_Fixup, eDI_reg }
422 #define Yvr { REP_Fixup, eDI_reg }
423 #define Yzr { REP_Fixup, eDI_reg }
424 #define indirDXr { REP_Fixup, indir_dx_reg }
425 #define ALr { REP_Fixup, al_reg }
426 #define eAXr { REP_Fixup, eAX_reg }
428 /* Used handle HLE prefix for lockable instructions. */
429 #define Ebh1 { HLE_Fixup1, b_mode }
430 #define Evh1 { HLE_Fixup1, v_mode }
431 #define Ebh2 { HLE_Fixup2, b_mode }
432 #define Evh2 { HLE_Fixup2, v_mode }
433 #define Ebh3 { HLE_Fixup3, b_mode }
434 #define Evh3 { HLE_Fixup3, v_mode }
436 #define BND { BND_Fixup, 0 }
437 #define NOTRACK { NOTRACK_Fixup, 0 }
439 #define cond_jump_flag { NULL, cond_jump_mode }
440 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
442 /* bits in sizeflag */
443 #define SUFFIX_ALWAYS 4
451 /* byte operand with operand swapped */
453 /* byte operand, sign extend like 'T' suffix */
455 /* operand size depends on prefixes */
457 /* operand size depends on prefixes with operand swapped */
459 /* operand size depends on address prefix */
463 /* double word operand */
465 /* double word operand with operand swapped */
467 /* quad word operand */
469 /* quad word operand with operand swapped */
471 /* ten-byte operand */
473 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
474 broadcast enabled. */
476 /* Similar to x_mode, but with different EVEX mem shifts. */
478 /* Similar to x_mode, but with yet different EVEX mem shifts. */
480 /* Similar to x_mode, but with disabled broadcast. */
482 /* Similar to x_mode, but with operands swapped and disabled broadcast
485 /* 16-byte XMM operand */
487 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
488 memory operand (depending on vector length). Broadcast isn't
491 /* Same as xmmq_mode, but broadcast is allowed. */
492 evex_half_bcst_xmmq_mode
,
493 /* XMM register or byte memory operand */
495 /* XMM register or word memory operand */
497 /* XMM register or double word memory operand */
499 /* XMM register or quad word memory operand */
501 /* 16-byte XMM, word, double word or quad word operand. */
503 /* 16-byte XMM, double word, quad word operand or xmm word operand. */
505 /* 32-byte YMM operand */
507 /* quad word, ymmword or zmmword memory operand. */
509 /* 32-byte YMM or 16-byte word operand */
513 /* d_mode in 32bit, q_mode in 64bit mode. */
515 /* pair of v_mode operands */
521 /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode. */
523 /* operand size depends on REX prefixes. */
525 /* registers like dq_mode, memory like w_mode, displacements like
526 v_mode without considering Intel64 ISA. */
530 /* bounds operand with operand swapped */
532 /* 4- or 6-byte pointer operand */
535 /* v_mode for indirect branch opcodes. */
537 /* v_mode for stack-related opcodes. */
539 /* non-quad operand size depends on prefixes */
541 /* 16-byte operand */
543 /* registers like dq_mode, memory like b_mode. */
545 /* registers like d_mode, memory like b_mode. */
547 /* registers like d_mode, memory like w_mode. */
549 /* registers like dq_mode, memory like d_mode. */
551 /* normal vex mode */
554 /* Operand size depends on the VEX.W bit, with VSIB dword indices. */
555 vex_vsib_d_w_dq_mode
,
556 /* Operand size depends on the VEX.W bit, with VSIB qword indices. */
557 vex_vsib_q_w_dq_mode
,
558 /* mandatory non-vector SIB. */
561 /* scalar, ignore vector length. */
563 /* like vex_mode, ignore vector length. */
565 /* Operand size depends on the VEX.W bit, ignore vector length. */
566 vex_scalar_w_dq_mode
,
568 /* Static rounding. */
570 /* Static rounding, 64-bit mode only. */
571 evex_rounding_64_mode
,
572 /* Supress all exceptions. */
575 /* Mask register operand. */
577 /* Mask register operand. */
645 #define FLOAT NULL, { { NULL, FLOATCODE } }, 0
647 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0
648 #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P
649 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
650 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
651 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
652 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
653 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
654 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
655 #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
656 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
657 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
658 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
659 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
660 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
661 #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I))
662 #define EVEX_LEN_TABLE(I) DIS386 (USE_EVEX_LEN_TABLE, (I))
689 REG_0F3A0F_PREFIX_1_MOD_3
,
702 REG_VEX_0F3849_X86_64_P_0_W_0_M_1
,
707 REG_XOP_09_12_M_1_L_0
,
713 REG_EVEX_0F38C6_M_0_L_2
,
714 REG_EVEX_0F38C7_M_0_L_2
791 MOD_VEX_0F12_PREFIX_0
,
792 MOD_VEX_0F12_PREFIX_2
,
794 MOD_VEX_0F16_PREFIX_0
,
795 MOD_VEX_0F16_PREFIX_2
,
819 MOD_VEX_0FF0_PREFIX_3
,
826 MOD_VEX_0F3849_X86_64_P_0_W_0
,
827 MOD_VEX_0F3849_X86_64_P_2_W_0
,
828 MOD_VEX_0F3849_X86_64_P_3_W_0
,
829 MOD_VEX_0F384B_X86_64_P_1_W_0
,
830 MOD_VEX_0F384B_X86_64_P_2_W_0
,
831 MOD_VEX_0F384B_X86_64_P_3_W_0
,
833 MOD_VEX_0F385C_X86_64_P_1_W_0
,
834 MOD_VEX_0F385E_X86_64_P_0_W_0
,
835 MOD_VEX_0F385E_X86_64_P_1_W_0
,
836 MOD_VEX_0F385E_X86_64_P_2_W_0
,
837 MOD_VEX_0F385E_X86_64_P_3_W_0
,
847 MOD_EVEX_0F12_PREFIX_0
,
848 MOD_EVEX_0F12_PREFIX_2
,
850 MOD_EVEX_0F16_PREFIX_0
,
851 MOD_EVEX_0F16_PREFIX_2
,
857 MOD_EVEX_0F382A_P_1_W_1
,
859 MOD_EVEX_0F383A_P_1_W_0
,
879 RM_0F1E_P_1_MOD_3_REG_7
,
880 RM_0FAE_REG_6_MOD_3_P_0
,
882 RM_0F3A0F_P_1_MOD_3_REG_0
,
884 RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0
890 PREFIX_0F01_REG_1_RM_4
,
891 PREFIX_0F01_REG_1_RM_5
,
892 PREFIX_0F01_REG_1_RM_6
,
893 PREFIX_0F01_REG_1_RM_7
,
894 PREFIX_0F01_REG_3_RM_1
,
895 PREFIX_0F01_REG_5_MOD_0
,
896 PREFIX_0F01_REG_5_MOD_3_RM_0
,
897 PREFIX_0F01_REG_5_MOD_3_RM_1
,
898 PREFIX_0F01_REG_5_MOD_3_RM_2
,
899 PREFIX_0F01_REG_5_MOD_3_RM_4
,
900 PREFIX_0F01_REG_5_MOD_3_RM_5
,
901 PREFIX_0F01_REG_5_MOD_3_RM_6
,
902 PREFIX_0F01_REG_5_MOD_3_RM_7
,
903 PREFIX_0F01_REG_7_MOD_3_RM_2
,
904 PREFIX_0F01_REG_7_MOD_3_RM_6
,
905 PREFIX_0F01_REG_7_MOD_3_RM_7
,
943 PREFIX_0FAE_REG_0_MOD_3
,
944 PREFIX_0FAE_REG_1_MOD_3
,
945 PREFIX_0FAE_REG_2_MOD_3
,
946 PREFIX_0FAE_REG_3_MOD_3
,
947 PREFIX_0FAE_REG_4_MOD_0
,
948 PREFIX_0FAE_REG_4_MOD_3
,
949 PREFIX_0FAE_REG_5_MOD_3
,
950 PREFIX_0FAE_REG_6_MOD_0
,
951 PREFIX_0FAE_REG_6_MOD_3
,
952 PREFIX_0FAE_REG_7_MOD_0
,
957 PREFIX_0FC7_REG_6_MOD_0
,
958 PREFIX_0FC7_REG_6_MOD_3
,
959 PREFIX_0FC7_REG_7_MOD_3
,
987 PREFIX_VEX_0F41_L_1_M_1_W_0
,
988 PREFIX_VEX_0F41_L_1_M_1_W_1
,
989 PREFIX_VEX_0F42_L_1_M_1_W_0
,
990 PREFIX_VEX_0F42_L_1_M_1_W_1
,
991 PREFIX_VEX_0F44_L_0_M_1_W_0
,
992 PREFIX_VEX_0F44_L_0_M_1_W_1
,
993 PREFIX_VEX_0F45_L_1_M_1_W_0
,
994 PREFIX_VEX_0F45_L_1_M_1_W_1
,
995 PREFIX_VEX_0F46_L_1_M_1_W_0
,
996 PREFIX_VEX_0F46_L_1_M_1_W_1
,
997 PREFIX_VEX_0F47_L_1_M_1_W_0
,
998 PREFIX_VEX_0F47_L_1_M_1_W_1
,
999 PREFIX_VEX_0F4A_L_1_M_1_W_0
,
1000 PREFIX_VEX_0F4A_L_1_M_1_W_1
,
1001 PREFIX_VEX_0F4B_L_1_M_1_W_0
,
1002 PREFIX_VEX_0F4B_L_1_M_1_W_1
,
1020 PREFIX_VEX_0F90_L_0_W_0
,
1021 PREFIX_VEX_0F90_L_0_W_1
,
1022 PREFIX_VEX_0F91_L_0_M_0_W_0
,
1023 PREFIX_VEX_0F91_L_0_M_0_W_1
,
1024 PREFIX_VEX_0F92_L_0_M_1_W_0
,
1025 PREFIX_VEX_0F92_L_0_M_1_W_1
,
1026 PREFIX_VEX_0F93_L_0_M_1_W_0
,
1027 PREFIX_VEX_0F93_L_0_M_1_W_1
,
1028 PREFIX_VEX_0F98_L_0_M_1_W_0
,
1029 PREFIX_VEX_0F98_L_0_M_1_W_1
,
1030 PREFIX_VEX_0F99_L_0_M_1_W_0
,
1031 PREFIX_VEX_0F99_L_0_M_1_W_1
,
1036 PREFIX_VEX_0F3849_X86_64
,
1037 PREFIX_VEX_0F384B_X86_64
,
1038 PREFIX_VEX_0F385C_X86_64
,
1039 PREFIX_VEX_0F385E_X86_64
,
1040 PREFIX_VEX_0F38F5_L_0
,
1041 PREFIX_VEX_0F38F6_L_0
,
1042 PREFIX_VEX_0F38F7_L_0
,
1043 PREFIX_VEX_0F3AF0_L_0
,
1138 X86_64_0F01_REG_1_RM_5_PREFIX_2
,
1139 X86_64_0F01_REG_1_RM_6_PREFIX_2
,
1140 X86_64_0F01_REG_1_RM_7_PREFIX_2
,
1143 X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1
,
1144 X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1
,
1145 X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1
,
1146 X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1
,
1147 X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1
,
1148 X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3
,
1149 X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1
,
1152 X86_64_0FC7_REG_6_MOD_3_PREFIX_1
,
1162 THREE_BYTE_0F38
= 0,
1189 VEX_LEN_0F12_P_0_M_0
= 0,
1190 VEX_LEN_0F12_P_0_M_1
,
1191 #define VEX_LEN_0F12_P_2_M_0 VEX_LEN_0F12_P_0_M_0
1193 VEX_LEN_0F16_P_0_M_0
,
1194 VEX_LEN_0F16_P_0_M_1
,
1195 #define VEX_LEN_0F16_P_2_M_0 VEX_LEN_0F16_P_0_M_0
1215 VEX_LEN_0FAE_R_2_M_0
,
1216 VEX_LEN_0FAE_R_3_M_0
,
1226 VEX_LEN_0F3849_X86_64_P_0_W_0_M_0
,
1227 VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0
,
1228 VEX_LEN_0F3849_X86_64_P_2_W_0_M_0
,
1229 VEX_LEN_0F3849_X86_64_P_3_W_0_M_0
,
1230 VEX_LEN_0F384B_X86_64_P_1_W_0_M_0
,
1231 VEX_LEN_0F384B_X86_64_P_2_W_0_M_0
,
1232 VEX_LEN_0F384B_X86_64_P_3_W_0_M_0
,
1234 VEX_LEN_0F385C_X86_64_P_1_W_0_M_0
,
1235 VEX_LEN_0F385E_X86_64_P_0_W_0_M_0
,
1236 VEX_LEN_0F385E_X86_64_P_1_W_0_M_0
,
1237 VEX_LEN_0F385E_X86_64_P_2_W_0_M_0
,
1238 VEX_LEN_0F385E_X86_64_P_3_W_0_M_0
,
1271 VEX_LEN_0FXOP_08_85
,
1272 VEX_LEN_0FXOP_08_86
,
1273 VEX_LEN_0FXOP_08_87
,
1274 VEX_LEN_0FXOP_08_8E
,
1275 VEX_LEN_0FXOP_08_8F
,
1276 VEX_LEN_0FXOP_08_95
,
1277 VEX_LEN_0FXOP_08_96
,
1278 VEX_LEN_0FXOP_08_97
,
1279 VEX_LEN_0FXOP_08_9E
,
1280 VEX_LEN_0FXOP_08_9F
,
1281 VEX_LEN_0FXOP_08_A3
,
1282 VEX_LEN_0FXOP_08_A6
,
1283 VEX_LEN_0FXOP_08_B6
,
1284 VEX_LEN_0FXOP_08_C0
,
1285 VEX_LEN_0FXOP_08_C1
,
1286 VEX_LEN_0FXOP_08_C2
,
1287 VEX_LEN_0FXOP_08_C3
,
1288 VEX_LEN_0FXOP_08_CC
,
1289 VEX_LEN_0FXOP_08_CD
,
1290 VEX_LEN_0FXOP_08_CE
,
1291 VEX_LEN_0FXOP_08_CF
,
1292 VEX_LEN_0FXOP_08_EC
,
1293 VEX_LEN_0FXOP_08_ED
,
1294 VEX_LEN_0FXOP_08_EE
,
1295 VEX_LEN_0FXOP_08_EF
,
1296 VEX_LEN_0FXOP_09_01
,
1297 VEX_LEN_0FXOP_09_02
,
1298 VEX_LEN_0FXOP_09_12_M_1
,
1299 VEX_LEN_0FXOP_09_82_W_0
,
1300 VEX_LEN_0FXOP_09_83_W_0
,
1301 VEX_LEN_0FXOP_09_90
,
1302 VEX_LEN_0FXOP_09_91
,
1303 VEX_LEN_0FXOP_09_92
,
1304 VEX_LEN_0FXOP_09_93
,
1305 VEX_LEN_0FXOP_09_94
,
1306 VEX_LEN_0FXOP_09_95
,
1307 VEX_LEN_0FXOP_09_96
,
1308 VEX_LEN_0FXOP_09_97
,
1309 VEX_LEN_0FXOP_09_98
,
1310 VEX_LEN_0FXOP_09_99
,
1311 VEX_LEN_0FXOP_09_9A
,
1312 VEX_LEN_0FXOP_09_9B
,
1313 VEX_LEN_0FXOP_09_C1
,
1314 VEX_LEN_0FXOP_09_C2
,
1315 VEX_LEN_0FXOP_09_C3
,
1316 VEX_LEN_0FXOP_09_C6
,
1317 VEX_LEN_0FXOP_09_C7
,
1318 VEX_LEN_0FXOP_09_CB
,
1319 VEX_LEN_0FXOP_09_D1
,
1320 VEX_LEN_0FXOP_09_D2
,
1321 VEX_LEN_0FXOP_09_D3
,
1322 VEX_LEN_0FXOP_09_D6
,
1323 VEX_LEN_0FXOP_09_D7
,
1324 VEX_LEN_0FXOP_09_DB
,
1325 VEX_LEN_0FXOP_09_E1
,
1326 VEX_LEN_0FXOP_09_E2
,
1327 VEX_LEN_0FXOP_09_E3
,
1328 VEX_LEN_0FXOP_0A_12
,
1333 EVEX_LEN_0F3816
= 0,
1335 EVEX_LEN_0F381A_M_0
,
1336 EVEX_LEN_0F381B_M_0
,
1338 EVEX_LEN_0F385A_M_0
,
1339 EVEX_LEN_0F385B_M_0
,
1340 EVEX_LEN_0F38C6_M_0
,
1341 EVEX_LEN_0F38C7_M_0
,
1358 VEX_W_0F41_L_1_M_1
= 0,
1380 VEX_W_0F381A_M_0_L_1
,
1387 VEX_W_0F3849_X86_64_P_0
,
1388 VEX_W_0F3849_X86_64_P_2
,
1389 VEX_W_0F3849_X86_64_P_3
,
1390 VEX_W_0F384B_X86_64_P_1
,
1391 VEX_W_0F384B_X86_64_P_2
,
1392 VEX_W_0F384B_X86_64_P_3
,
1399 VEX_W_0F385A_M_0_L_0
,
1400 VEX_W_0F385C_X86_64_P_1
,
1401 VEX_W_0F385E_X86_64_P_0
,
1402 VEX_W_0F385E_X86_64_P_1
,
1403 VEX_W_0F385E_X86_64_P_2
,
1404 VEX_W_0F385E_X86_64_P_3
,
1426 VEX_W_0FXOP_08_85_L_0
,
1427 VEX_W_0FXOP_08_86_L_0
,
1428 VEX_W_0FXOP_08_87_L_0
,
1429 VEX_W_0FXOP_08_8E_L_0
,
1430 VEX_W_0FXOP_08_8F_L_0
,
1431 VEX_W_0FXOP_08_95_L_0
,
1432 VEX_W_0FXOP_08_96_L_0
,
1433 VEX_W_0FXOP_08_97_L_0
,
1434 VEX_W_0FXOP_08_9E_L_0
,
1435 VEX_W_0FXOP_08_9F_L_0
,
1436 VEX_W_0FXOP_08_A6_L_0
,
1437 VEX_W_0FXOP_08_B6_L_0
,
1438 VEX_W_0FXOP_08_C0_L_0
,
1439 VEX_W_0FXOP_08_C1_L_0
,
1440 VEX_W_0FXOP_08_C2_L_0
,
1441 VEX_W_0FXOP_08_C3_L_0
,
1442 VEX_W_0FXOP_08_CC_L_0
,
1443 VEX_W_0FXOP_08_CD_L_0
,
1444 VEX_W_0FXOP_08_CE_L_0
,
1445 VEX_W_0FXOP_08_CF_L_0
,
1446 VEX_W_0FXOP_08_EC_L_0
,
1447 VEX_W_0FXOP_08_ED_L_0
,
1448 VEX_W_0FXOP_08_EE_L_0
,
1449 VEX_W_0FXOP_08_EF_L_0
,
1455 VEX_W_0FXOP_09_C1_L_0
,
1456 VEX_W_0FXOP_09_C2_L_0
,
1457 VEX_W_0FXOP_09_C3_L_0
,
1458 VEX_W_0FXOP_09_C6_L_0
,
1459 VEX_W_0FXOP_09_C7_L_0
,
1460 VEX_W_0FXOP_09_CB_L_0
,
1461 VEX_W_0FXOP_09_D1_L_0
,
1462 VEX_W_0FXOP_09_D2_L_0
,
1463 VEX_W_0FXOP_09_D3_L_0
,
1464 VEX_W_0FXOP_09_D6_L_0
,
1465 VEX_W_0FXOP_09_D7_L_0
,
1466 VEX_W_0FXOP_09_DB_L_0
,
1467 VEX_W_0FXOP_09_E1_L_0
,
1468 VEX_W_0FXOP_09_E2_L_0
,
1469 VEX_W_0FXOP_09_E3_L_0
,
1475 EVEX_W_0F12_P_0_M_1
,
1478 EVEX_W_0F16_P_0_M_1
,
1558 EVEX_W_0F381A_M_0_L_n
,
1559 EVEX_W_0F381B_M_0_L_2
,
1585 EVEX_W_0F385A_M_0_L_n
,
1586 EVEX_W_0F385B_M_0_L_2
,
1616 typedef void (*op_rtn
) (int bytemode
, int sizeflag
);
1625 unsigned int prefix_requirement
;
1628 /* Upper case letters in the instruction names here are macros.
1629 'A' => print 'b' if no register operands or suffix_always is true
1630 'B' => print 'b' if suffix_always is true
1631 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
1633 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
1634 suffix_always is true
1635 'E' => print 'e' if 32-bit form of jcxz
1636 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
1637 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
1638 'H' => print ",pt" or ",pn" branch hint
1641 'K' => print 'd' or 'q' if rex prefix is present.
1643 'M' => print 'r' if intel_mnemonic is false.
1644 'N' => print 'n' if instruction has no wait "prefix"
1645 'O' => print 'd' or 'o' (or 'q' in Intel mode)
1646 'P' => behave as 'T' except with register operand outside of suffix_always
1648 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
1650 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
1651 'S' => print 'w', 'l' or 'q' if suffix_always is true
1652 'T' => print 'w', 'l'/'d', or 'q' if instruction has an operand size
1653 prefix or if suffix_always is true.
1656 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
1657 'X' => print 's', 'd' depending on data16 prefix (for XMM)
1659 'Z' => print 'q' in 64bit mode and 'l' otherwise, if suffix_always is true.
1660 '!' => change condition from true to false or from false to true.
1661 '%' => add 1 upper case letter to the macro.
1662 '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size
1663 prefix or suffix_always is true (lcall/ljmp).
1664 '@' => in 64bit mode for Intel64 ISA or if instruction
1665 has no operand sizing prefix, print 'q' if suffix_always is true or
1666 nothing otherwise; behave as 'P' in all other cases
1668 2 upper case letter macros:
1669 "XY" => print 'x' or 'y' if suffix_always is true or no register
1670 operands and no broadcast.
1671 "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
1672 register operands and no broadcast.
1673 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
1674 "XV" => print "{vex3}" pseudo prefix
1675 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand, cond
1676 being false, or no operand at all in 64bit mode, or if suffix_always
1678 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
1679 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
1680 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
1681 "DQ" => print 'd' or 'q' depending on the VEX.W bit
1682 "BW" => print 'b' or 'w' depending on the VEX.W bit
1683 "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
1684 an operand size prefix, or suffix_always is true. print
1685 'q' if rex prefix is present.
1687 Many of the above letters print nothing in Intel mode. See "putop"
1690 Braces '{' and '}', and vertical bars '|', indicate alternative
1691 mnemonic strings for AT&T and Intel. */
1693 static const struct dis386 dis386
[] = {
1695 { "addB", { Ebh1
, Gb
}, 0 },
1696 { "addS", { Evh1
, Gv
}, 0 },
1697 { "addB", { Gb
, EbS
}, 0 },
1698 { "addS", { Gv
, EvS
}, 0 },
1699 { "addB", { AL
, Ib
}, 0 },
1700 { "addS", { eAX
, Iv
}, 0 },
1701 { X86_64_TABLE (X86_64_06
) },
1702 { X86_64_TABLE (X86_64_07
) },
1704 { "orB", { Ebh1
, Gb
}, 0 },
1705 { "orS", { Evh1
, Gv
}, 0 },
1706 { "orB", { Gb
, EbS
}, 0 },
1707 { "orS", { Gv
, EvS
}, 0 },
1708 { "orB", { AL
, Ib
}, 0 },
1709 { "orS", { eAX
, Iv
}, 0 },
1710 { X86_64_TABLE (X86_64_0E
) },
1711 { Bad_Opcode
}, /* 0x0f extended opcode escape */
1713 { "adcB", { Ebh1
, Gb
}, 0 },
1714 { "adcS", { Evh1
, Gv
}, 0 },
1715 { "adcB", { Gb
, EbS
}, 0 },
1716 { "adcS", { Gv
, EvS
}, 0 },
1717 { "adcB", { AL
, Ib
}, 0 },
1718 { "adcS", { eAX
, Iv
}, 0 },
1719 { X86_64_TABLE (X86_64_16
) },
1720 { X86_64_TABLE (X86_64_17
) },
1722 { "sbbB", { Ebh1
, Gb
}, 0 },
1723 { "sbbS", { Evh1
, Gv
}, 0 },
1724 { "sbbB", { Gb
, EbS
}, 0 },
1725 { "sbbS", { Gv
, EvS
}, 0 },
1726 { "sbbB", { AL
, Ib
}, 0 },
1727 { "sbbS", { eAX
, Iv
}, 0 },
1728 { X86_64_TABLE (X86_64_1E
) },
1729 { X86_64_TABLE (X86_64_1F
) },
1731 { "andB", { Ebh1
, Gb
}, 0 },
1732 { "andS", { Evh1
, Gv
}, 0 },
1733 { "andB", { Gb
, EbS
}, 0 },
1734 { "andS", { Gv
, EvS
}, 0 },
1735 { "andB", { AL
, Ib
}, 0 },
1736 { "andS", { eAX
, Iv
}, 0 },
1737 { Bad_Opcode
}, /* SEG ES prefix */
1738 { X86_64_TABLE (X86_64_27
) },
1740 { "subB", { Ebh1
, Gb
}, 0 },
1741 { "subS", { Evh1
, Gv
}, 0 },
1742 { "subB", { Gb
, EbS
}, 0 },
1743 { "subS", { Gv
, EvS
}, 0 },
1744 { "subB", { AL
, Ib
}, 0 },
1745 { "subS", { eAX
, Iv
}, 0 },
1746 { Bad_Opcode
}, /* SEG CS prefix */
1747 { X86_64_TABLE (X86_64_2F
) },
1749 { "xorB", { Ebh1
, Gb
}, 0 },
1750 { "xorS", { Evh1
, Gv
}, 0 },
1751 { "xorB", { Gb
, EbS
}, 0 },
1752 { "xorS", { Gv
, EvS
}, 0 },
1753 { "xorB", { AL
, Ib
}, 0 },
1754 { "xorS", { eAX
, Iv
}, 0 },
1755 { Bad_Opcode
}, /* SEG SS prefix */
1756 { X86_64_TABLE (X86_64_37
) },
1758 { "cmpB", { Eb
, Gb
}, 0 },
1759 { "cmpS", { Ev
, Gv
}, 0 },
1760 { "cmpB", { Gb
, EbS
}, 0 },
1761 { "cmpS", { Gv
, EvS
}, 0 },
1762 { "cmpB", { AL
, Ib
}, 0 },
1763 { "cmpS", { eAX
, Iv
}, 0 },
1764 { Bad_Opcode
}, /* SEG DS prefix */
1765 { X86_64_TABLE (X86_64_3F
) },
1767 { "inc{S|}", { RMeAX
}, 0 },
1768 { "inc{S|}", { RMeCX
}, 0 },
1769 { "inc{S|}", { RMeDX
}, 0 },
1770 { "inc{S|}", { RMeBX
}, 0 },
1771 { "inc{S|}", { RMeSP
}, 0 },
1772 { "inc{S|}", { RMeBP
}, 0 },
1773 { "inc{S|}", { RMeSI
}, 0 },
1774 { "inc{S|}", { RMeDI
}, 0 },
1776 { "dec{S|}", { RMeAX
}, 0 },
1777 { "dec{S|}", { RMeCX
}, 0 },
1778 { "dec{S|}", { RMeDX
}, 0 },
1779 { "dec{S|}", { RMeBX
}, 0 },
1780 { "dec{S|}", { RMeSP
}, 0 },
1781 { "dec{S|}", { RMeBP
}, 0 },
1782 { "dec{S|}", { RMeSI
}, 0 },
1783 { "dec{S|}", { RMeDI
}, 0 },
1785 { "push{!P|}", { RMrAX
}, 0 },
1786 { "push{!P|}", { RMrCX
}, 0 },
1787 { "push{!P|}", { RMrDX
}, 0 },
1788 { "push{!P|}", { RMrBX
}, 0 },
1789 { "push{!P|}", { RMrSP
}, 0 },
1790 { "push{!P|}", { RMrBP
}, 0 },
1791 { "push{!P|}", { RMrSI
}, 0 },
1792 { "push{!P|}", { RMrDI
}, 0 },
1794 { "pop{!P|}", { RMrAX
}, 0 },
1795 { "pop{!P|}", { RMrCX
}, 0 },
1796 { "pop{!P|}", { RMrDX
}, 0 },
1797 { "pop{!P|}", { RMrBX
}, 0 },
1798 { "pop{!P|}", { RMrSP
}, 0 },
1799 { "pop{!P|}", { RMrBP
}, 0 },
1800 { "pop{!P|}", { RMrSI
}, 0 },
1801 { "pop{!P|}", { RMrDI
}, 0 },
1803 { X86_64_TABLE (X86_64_60
) },
1804 { X86_64_TABLE (X86_64_61
) },
1805 { X86_64_TABLE (X86_64_62
) },
1806 { X86_64_TABLE (X86_64_63
) },
1807 { Bad_Opcode
}, /* seg fs */
1808 { Bad_Opcode
}, /* seg gs */
1809 { Bad_Opcode
}, /* op size prefix */
1810 { Bad_Opcode
}, /* adr size prefix */
1812 { "pushP", { sIv
}, 0 },
1813 { "imulS", { Gv
, Ev
, Iv
}, 0 },
1814 { "pushP", { sIbT
}, 0 },
1815 { "imulS", { Gv
, Ev
, sIb
}, 0 },
1816 { "ins{b|}", { Ybr
, indirDX
}, 0 },
1817 { X86_64_TABLE (X86_64_6D
) },
1818 { "outs{b|}", { indirDXr
, Xb
}, 0 },
1819 { X86_64_TABLE (X86_64_6F
) },
1821 { "joH", { Jb
, BND
, cond_jump_flag
}, 0 },
1822 { "jnoH", { Jb
, BND
, cond_jump_flag
}, 0 },
1823 { "jbH", { Jb
, BND
, cond_jump_flag
}, 0 },
1824 { "jaeH", { Jb
, BND
, cond_jump_flag
}, 0 },
1825 { "jeH", { Jb
, BND
, cond_jump_flag
}, 0 },
1826 { "jneH", { Jb
, BND
, cond_jump_flag
}, 0 },
1827 { "jbeH", { Jb
, BND
, cond_jump_flag
}, 0 },
1828 { "jaH", { Jb
, BND
, cond_jump_flag
}, 0 },
1830 { "jsH", { Jb
, BND
, cond_jump_flag
}, 0 },
1831 { "jnsH", { Jb
, BND
, cond_jump_flag
}, 0 },
1832 { "jpH", { Jb
, BND
, cond_jump_flag
}, 0 },
1833 { "jnpH", { Jb
, BND
, cond_jump_flag
}, 0 },
1834 { "jlH", { Jb
, BND
, cond_jump_flag
}, 0 },
1835 { "jgeH", { Jb
, BND
, cond_jump_flag
}, 0 },
1836 { "jleH", { Jb
, BND
, cond_jump_flag
}, 0 },
1837 { "jgH", { Jb
, BND
, cond_jump_flag
}, 0 },
1839 { REG_TABLE (REG_80
) },
1840 { REG_TABLE (REG_81
) },
1841 { X86_64_TABLE (X86_64_82
) },
1842 { REG_TABLE (REG_83
) },
1843 { "testB", { Eb
, Gb
}, 0 },
1844 { "testS", { Ev
, Gv
}, 0 },
1845 { "xchgB", { Ebh2
, Gb
}, 0 },
1846 { "xchgS", { Evh2
, Gv
}, 0 },
1848 { "movB", { Ebh3
, Gb
}, 0 },
1849 { "movS", { Evh3
, Gv
}, 0 },
1850 { "movB", { Gb
, EbS
}, 0 },
1851 { "movS", { Gv
, EvS
}, 0 },
1852 { "movD", { Sv
, Sw
}, 0 },
1853 { MOD_TABLE (MOD_8D
) },
1854 { "movD", { Sw
, Sv
}, 0 },
1855 { REG_TABLE (REG_8F
) },
1857 { PREFIX_TABLE (PREFIX_90
) },
1858 { "xchgS", { RMeCX
, eAX
}, 0 },
1859 { "xchgS", { RMeDX
, eAX
}, 0 },
1860 { "xchgS", { RMeBX
, eAX
}, 0 },
1861 { "xchgS", { RMeSP
, eAX
}, 0 },
1862 { "xchgS", { RMeBP
, eAX
}, 0 },
1863 { "xchgS", { RMeSI
, eAX
}, 0 },
1864 { "xchgS", { RMeDI
, eAX
}, 0 },
1866 { "cW{t|}R", { XX
}, 0 },
1867 { "cR{t|}O", { XX
}, 0 },
1868 { X86_64_TABLE (X86_64_9A
) },
1869 { Bad_Opcode
}, /* fwait */
1870 { "pushfP", { XX
}, 0 },
1871 { "popfP", { XX
}, 0 },
1872 { "sahf", { XX
}, 0 },
1873 { "lahf", { XX
}, 0 },
1875 { "mov%LB", { AL
, Ob
}, 0 },
1876 { "mov%LS", { eAX
, Ov
}, 0 },
1877 { "mov%LB", { Ob
, AL
}, 0 },
1878 { "mov%LS", { Ov
, eAX
}, 0 },
1879 { "movs{b|}", { Ybr
, Xb
}, 0 },
1880 { "movs{R|}", { Yvr
, Xv
}, 0 },
1881 { "cmps{b|}", { Xb
, Yb
}, 0 },
1882 { "cmps{R|}", { Xv
, Yv
}, 0 },
1884 { "testB", { AL
, Ib
}, 0 },
1885 { "testS", { eAX
, Iv
}, 0 },
1886 { "stosB", { Ybr
, AL
}, 0 },
1887 { "stosS", { Yvr
, eAX
}, 0 },
1888 { "lodsB", { ALr
, Xb
}, 0 },
1889 { "lodsS", { eAXr
, Xv
}, 0 },
1890 { "scasB", { AL
, Yb
}, 0 },
1891 { "scasS", { eAX
, Yv
}, 0 },
1893 { "movB", { RMAL
, Ib
}, 0 },
1894 { "movB", { RMCL
, Ib
}, 0 },
1895 { "movB", { RMDL
, Ib
}, 0 },
1896 { "movB", { RMBL
, Ib
}, 0 },
1897 { "movB", { RMAH
, Ib
}, 0 },
1898 { "movB", { RMCH
, Ib
}, 0 },
1899 { "movB", { RMDH
, Ib
}, 0 },
1900 { "movB", { RMBH
, Ib
}, 0 },
1902 { "mov%LV", { RMeAX
, Iv64
}, 0 },
1903 { "mov%LV", { RMeCX
, Iv64
}, 0 },
1904 { "mov%LV", { RMeDX
, Iv64
}, 0 },
1905 { "mov%LV", { RMeBX
, Iv64
}, 0 },
1906 { "mov%LV", { RMeSP
, Iv64
}, 0 },
1907 { "mov%LV", { RMeBP
, Iv64
}, 0 },
1908 { "mov%LV", { RMeSI
, Iv64
}, 0 },
1909 { "mov%LV", { RMeDI
, Iv64
}, 0 },
1911 { REG_TABLE (REG_C0
) },
1912 { REG_TABLE (REG_C1
) },
1913 { X86_64_TABLE (X86_64_C2
) },
1914 { X86_64_TABLE (X86_64_C3
) },
1915 { X86_64_TABLE (X86_64_C4
) },
1916 { X86_64_TABLE (X86_64_C5
) },
1917 { REG_TABLE (REG_C6
) },
1918 { REG_TABLE (REG_C7
) },
1920 { "enterP", { Iw
, Ib
}, 0 },
1921 { "leaveP", { XX
}, 0 },
1922 { "{l|}ret{|f}%LP", { Iw
}, 0 },
1923 { "{l|}ret{|f}%LP", { XX
}, 0 },
1924 { "int3", { XX
}, 0 },
1925 { "int", { Ib
}, 0 },
1926 { X86_64_TABLE (X86_64_CE
) },
1927 { "iret%LP", { XX
}, 0 },
1929 { REG_TABLE (REG_D0
) },
1930 { REG_TABLE (REG_D1
) },
1931 { REG_TABLE (REG_D2
) },
1932 { REG_TABLE (REG_D3
) },
1933 { X86_64_TABLE (X86_64_D4
) },
1934 { X86_64_TABLE (X86_64_D5
) },
1936 { "xlat", { DSBX
}, 0 },
1947 { "loopneFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
1948 { "loopeFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
1949 { "loopFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
1950 { "jEcxzH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
1951 { "inB", { AL
, Ib
}, 0 },
1952 { "inG", { zAX
, Ib
}, 0 },
1953 { "outB", { Ib
, AL
}, 0 },
1954 { "outG", { Ib
, zAX
}, 0 },
1956 { X86_64_TABLE (X86_64_E8
) },
1957 { X86_64_TABLE (X86_64_E9
) },
1958 { X86_64_TABLE (X86_64_EA
) },
1959 { "jmp", { Jb
, BND
}, 0 },
1960 { "inB", { AL
, indirDX
}, 0 },
1961 { "inG", { zAX
, indirDX
}, 0 },
1962 { "outB", { indirDX
, AL
}, 0 },
1963 { "outG", { indirDX
, zAX
}, 0 },
1965 { Bad_Opcode
}, /* lock prefix */
1966 { "icebp", { XX
}, 0 },
1967 { Bad_Opcode
}, /* repne */
1968 { Bad_Opcode
}, /* repz */
1969 { "hlt", { XX
}, 0 },
1970 { "cmc", { XX
}, 0 },
1971 { REG_TABLE (REG_F6
) },
1972 { REG_TABLE (REG_F7
) },
1974 { "clc", { XX
}, 0 },
1975 { "stc", { XX
}, 0 },
1976 { "cli", { XX
}, 0 },
1977 { "sti", { XX
}, 0 },
1978 { "cld", { XX
}, 0 },
1979 { "std", { XX
}, 0 },
1980 { REG_TABLE (REG_FE
) },
1981 { REG_TABLE (REG_FF
) },
1984 static const struct dis386 dis386_twobyte
[] = {
1986 { REG_TABLE (REG_0F00
) },
1987 { REG_TABLE (REG_0F01
) },
1988 { "larS", { Gv
, Ew
}, 0 },
1989 { "lslS", { Gv
, Ew
}, 0 },
1991 { "syscall", { XX
}, 0 },
1992 { "clts", { XX
}, 0 },
1993 { "sysret%LQ", { XX
}, 0 },
1995 { "invd", { XX
}, 0 },
1996 { PREFIX_TABLE (PREFIX_0F09
) },
1998 { "ud2", { XX
}, 0 },
2000 { REG_TABLE (REG_0F0D
) },
2001 { "femms", { XX
}, 0 },
2002 { "", { MX
, EM
, OPSUF
}, 0 }, /* See OP_3DNowSuffix. */
2004 { PREFIX_TABLE (PREFIX_0F10
) },
2005 { PREFIX_TABLE (PREFIX_0F11
) },
2006 { PREFIX_TABLE (PREFIX_0F12
) },
2007 { MOD_TABLE (MOD_0F13
) },
2008 { "unpcklpX", { XM
, EXx
}, PREFIX_OPCODE
},
2009 { "unpckhpX", { XM
, EXx
}, PREFIX_OPCODE
},
2010 { PREFIX_TABLE (PREFIX_0F16
) },
2011 { MOD_TABLE (MOD_0F17
) },
2013 { REG_TABLE (REG_0F18
) },
2014 { "nopQ", { Ev
}, 0 },
2015 { PREFIX_TABLE (PREFIX_0F1A
) },
2016 { PREFIX_TABLE (PREFIX_0F1B
) },
2017 { PREFIX_TABLE (PREFIX_0F1C
) },
2018 { "nopQ", { Ev
}, 0 },
2019 { PREFIX_TABLE (PREFIX_0F1E
) },
2020 { "nopQ", { Ev
}, 0 },
2022 { "movZ", { Em
, Cm
}, 0 },
2023 { "movZ", { Em
, Dm
}, 0 },
2024 { "movZ", { Cm
, Em
}, 0 },
2025 { "movZ", { Dm
, Em
}, 0 },
2026 { X86_64_TABLE (X86_64_0F24
) },
2028 { X86_64_TABLE (X86_64_0F26
) },
2031 { "movapX", { XM
, EXx
}, PREFIX_OPCODE
},
2032 { "movapX", { EXxS
, XM
}, PREFIX_OPCODE
},
2033 { PREFIX_TABLE (PREFIX_0F2A
) },
2034 { PREFIX_TABLE (PREFIX_0F2B
) },
2035 { PREFIX_TABLE (PREFIX_0F2C
) },
2036 { PREFIX_TABLE (PREFIX_0F2D
) },
2037 { PREFIX_TABLE (PREFIX_0F2E
) },
2038 { PREFIX_TABLE (PREFIX_0F2F
) },
2040 { "wrmsr", { XX
}, 0 },
2041 { "rdtsc", { XX
}, 0 },
2042 { "rdmsr", { XX
}, 0 },
2043 { "rdpmc", { XX
}, 0 },
2044 { "sysenter", { SEP
}, 0 },
2045 { "sysexit%LQ", { SEP
}, 0 },
2047 { "getsec", { XX
}, 0 },
2049 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38
, PREFIX_OPCODE
) },
2051 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A
, PREFIX_OPCODE
) },
2058 { "cmovoS", { Gv
, Ev
}, 0 },
2059 { "cmovnoS", { Gv
, Ev
}, 0 },
2060 { "cmovbS", { Gv
, Ev
}, 0 },
2061 { "cmovaeS", { Gv
, Ev
}, 0 },
2062 { "cmoveS", { Gv
, Ev
}, 0 },
2063 { "cmovneS", { Gv
, Ev
}, 0 },
2064 { "cmovbeS", { Gv
, Ev
}, 0 },
2065 { "cmovaS", { Gv
, Ev
}, 0 },
2067 { "cmovsS", { Gv
, Ev
}, 0 },
2068 { "cmovnsS", { Gv
, Ev
}, 0 },
2069 { "cmovpS", { Gv
, Ev
}, 0 },
2070 { "cmovnpS", { Gv
, Ev
}, 0 },
2071 { "cmovlS", { Gv
, Ev
}, 0 },
2072 { "cmovgeS", { Gv
, Ev
}, 0 },
2073 { "cmovleS", { Gv
, Ev
}, 0 },
2074 { "cmovgS", { Gv
, Ev
}, 0 },
2076 { MOD_TABLE (MOD_0F50
) },
2077 { PREFIX_TABLE (PREFIX_0F51
) },
2078 { PREFIX_TABLE (PREFIX_0F52
) },
2079 { PREFIX_TABLE (PREFIX_0F53
) },
2080 { "andpX", { XM
, EXx
}, PREFIX_OPCODE
},
2081 { "andnpX", { XM
, EXx
}, PREFIX_OPCODE
},
2082 { "orpX", { XM
, EXx
}, PREFIX_OPCODE
},
2083 { "xorpX", { XM
, EXx
}, PREFIX_OPCODE
},
2085 { PREFIX_TABLE (PREFIX_0F58
) },
2086 { PREFIX_TABLE (PREFIX_0F59
) },
2087 { PREFIX_TABLE (PREFIX_0F5A
) },
2088 { PREFIX_TABLE (PREFIX_0F5B
) },
2089 { PREFIX_TABLE (PREFIX_0F5C
) },
2090 { PREFIX_TABLE (PREFIX_0F5D
) },
2091 { PREFIX_TABLE (PREFIX_0F5E
) },
2092 { PREFIX_TABLE (PREFIX_0F5F
) },
2094 { PREFIX_TABLE (PREFIX_0F60
) },
2095 { PREFIX_TABLE (PREFIX_0F61
) },
2096 { PREFIX_TABLE (PREFIX_0F62
) },
2097 { "packsswb", { MX
, EM
}, PREFIX_OPCODE
},
2098 { "pcmpgtb", { MX
, EM
}, PREFIX_OPCODE
},
2099 { "pcmpgtw", { MX
, EM
}, PREFIX_OPCODE
},
2100 { "pcmpgtd", { MX
, EM
}, PREFIX_OPCODE
},
2101 { "packuswb", { MX
, EM
}, PREFIX_OPCODE
},
2103 { "punpckhbw", { MX
, EM
}, PREFIX_OPCODE
},
2104 { "punpckhwd", { MX
, EM
}, PREFIX_OPCODE
},
2105 { "punpckhdq", { MX
, EM
}, PREFIX_OPCODE
},
2106 { "packssdw", { MX
, EM
}, PREFIX_OPCODE
},
2107 { "punpcklqdq", { XM
, EXx
}, PREFIX_DATA
},
2108 { "punpckhqdq", { XM
, EXx
}, PREFIX_DATA
},
2109 { "movK", { MX
, Edq
}, PREFIX_OPCODE
},
2110 { PREFIX_TABLE (PREFIX_0F6F
) },
2112 { PREFIX_TABLE (PREFIX_0F70
) },
2113 { MOD_TABLE (MOD_0F71
) },
2114 { MOD_TABLE (MOD_0F72
) },
2115 { MOD_TABLE (MOD_0F73
) },
2116 { "pcmpeqb", { MX
, EM
}, PREFIX_OPCODE
},
2117 { "pcmpeqw", { MX
, EM
}, PREFIX_OPCODE
},
2118 { "pcmpeqd", { MX
, EM
}, PREFIX_OPCODE
},
2119 { "emms", { XX
}, PREFIX_OPCODE
},
2121 { PREFIX_TABLE (PREFIX_0F78
) },
2122 { PREFIX_TABLE (PREFIX_0F79
) },
2125 { PREFIX_TABLE (PREFIX_0F7C
) },
2126 { PREFIX_TABLE (PREFIX_0F7D
) },
2127 { PREFIX_TABLE (PREFIX_0F7E
) },
2128 { PREFIX_TABLE (PREFIX_0F7F
) },
2130 { "joH", { Jv
, BND
, cond_jump_flag
}, 0 },
2131 { "jnoH", { Jv
, BND
, cond_jump_flag
}, 0 },
2132 { "jbH", { Jv
, BND
, cond_jump_flag
}, 0 },
2133 { "jaeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2134 { "jeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2135 { "jneH", { Jv
, BND
, cond_jump_flag
}, 0 },
2136 { "jbeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2137 { "jaH", { Jv
, BND
, cond_jump_flag
}, 0 },
2139 { "jsH", { Jv
, BND
, cond_jump_flag
}, 0 },
2140 { "jnsH", { Jv
, BND
, cond_jump_flag
}, 0 },
2141 { "jpH", { Jv
, BND
, cond_jump_flag
}, 0 },
2142 { "jnpH", { Jv
, BND
, cond_jump_flag
}, 0 },
2143 { "jlH", { Jv
, BND
, cond_jump_flag
}, 0 },
2144 { "jgeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2145 { "jleH", { Jv
, BND
, cond_jump_flag
}, 0 },
2146 { "jgH", { Jv
, BND
, cond_jump_flag
}, 0 },
2148 { "seto", { Eb
}, 0 },
2149 { "setno", { Eb
}, 0 },
2150 { "setb", { Eb
}, 0 },
2151 { "setae", { Eb
}, 0 },
2152 { "sete", { Eb
}, 0 },
2153 { "setne", { Eb
}, 0 },
2154 { "setbe", { Eb
}, 0 },
2155 { "seta", { Eb
}, 0 },
2157 { "sets", { Eb
}, 0 },
2158 { "setns", { Eb
}, 0 },
2159 { "setp", { Eb
}, 0 },
2160 { "setnp", { Eb
}, 0 },
2161 { "setl", { Eb
}, 0 },
2162 { "setge", { Eb
}, 0 },
2163 { "setle", { Eb
}, 0 },
2164 { "setg", { Eb
}, 0 },
2166 { "pushP", { fs
}, 0 },
2167 { "popP", { fs
}, 0 },
2168 { "cpuid", { XX
}, 0 },
2169 { "btS", { Ev
, Gv
}, 0 },
2170 { "shldS", { Ev
, Gv
, Ib
}, 0 },
2171 { "shldS", { Ev
, Gv
, CL
}, 0 },
2172 { REG_TABLE (REG_0FA6
) },
2173 { REG_TABLE (REG_0FA7
) },
2175 { "pushP", { gs
}, 0 },
2176 { "popP", { gs
}, 0 },
2177 { "rsm", { XX
}, 0 },
2178 { "btsS", { Evh1
, Gv
}, 0 },
2179 { "shrdS", { Ev
, Gv
, Ib
}, 0 },
2180 { "shrdS", { Ev
, Gv
, CL
}, 0 },
2181 { REG_TABLE (REG_0FAE
) },
2182 { "imulS", { Gv
, Ev
}, 0 },
2184 { "cmpxchgB", { Ebh1
, Gb
}, 0 },
2185 { "cmpxchgS", { Evh1
, Gv
}, 0 },
2186 { MOD_TABLE (MOD_0FB2
) },
2187 { "btrS", { Evh1
, Gv
}, 0 },
2188 { MOD_TABLE (MOD_0FB4
) },
2189 { MOD_TABLE (MOD_0FB5
) },
2190 { "movz{bR|x}", { Gv
, Eb
}, 0 },
2191 { "movz{wR|x}", { Gv
, Ew
}, 0 }, /* yes, there really is movzww ! */
2193 { PREFIX_TABLE (PREFIX_0FB8
) },
2194 { "ud1S", { Gv
, Ev
}, 0 },
2195 { REG_TABLE (REG_0FBA
) },
2196 { "btcS", { Evh1
, Gv
}, 0 },
2197 { PREFIX_TABLE (PREFIX_0FBC
) },
2198 { PREFIX_TABLE (PREFIX_0FBD
) },
2199 { "movs{bR|x}", { Gv
, Eb
}, 0 },
2200 { "movs{wR|x}", { Gv
, Ew
}, 0 }, /* yes, there really is movsww ! */
2202 { "xaddB", { Ebh1
, Gb
}, 0 },
2203 { "xaddS", { Evh1
, Gv
}, 0 },
2204 { PREFIX_TABLE (PREFIX_0FC2
) },
2205 { MOD_TABLE (MOD_0FC3
) },
2206 { "pinsrw", { MX
, Edqw
, Ib
}, PREFIX_OPCODE
},
2207 { "pextrw", { Gdq
, MS
, Ib
}, PREFIX_OPCODE
},
2208 { "shufpX", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
2209 { REG_TABLE (REG_0FC7
) },
2211 { "bswap", { RMeAX
}, 0 },
2212 { "bswap", { RMeCX
}, 0 },
2213 { "bswap", { RMeDX
}, 0 },
2214 { "bswap", { RMeBX
}, 0 },
2215 { "bswap", { RMeSP
}, 0 },
2216 { "bswap", { RMeBP
}, 0 },
2217 { "bswap", { RMeSI
}, 0 },
2218 { "bswap", { RMeDI
}, 0 },
2220 { PREFIX_TABLE (PREFIX_0FD0
) },
2221 { "psrlw", { MX
, EM
}, PREFIX_OPCODE
},
2222 { "psrld", { MX
, EM
}, PREFIX_OPCODE
},
2223 { "psrlq", { MX
, EM
}, PREFIX_OPCODE
},
2224 { "paddq", { MX
, EM
}, PREFIX_OPCODE
},
2225 { "pmullw", { MX
, EM
}, PREFIX_OPCODE
},
2226 { PREFIX_TABLE (PREFIX_0FD6
) },
2227 { MOD_TABLE (MOD_0FD7
) },
2229 { "psubusb", { MX
, EM
}, PREFIX_OPCODE
},
2230 { "psubusw", { MX
, EM
}, PREFIX_OPCODE
},
2231 { "pminub", { MX
, EM
}, PREFIX_OPCODE
},
2232 { "pand", { MX
, EM
}, PREFIX_OPCODE
},
2233 { "paddusb", { MX
, EM
}, PREFIX_OPCODE
},
2234 { "paddusw", { MX
, EM
}, PREFIX_OPCODE
},
2235 { "pmaxub", { MX
, EM
}, PREFIX_OPCODE
},
2236 { "pandn", { MX
, EM
}, PREFIX_OPCODE
},
2238 { "pavgb", { MX
, EM
}, PREFIX_OPCODE
},
2239 { "psraw", { MX
, EM
}, PREFIX_OPCODE
},
2240 { "psrad", { MX
, EM
}, PREFIX_OPCODE
},
2241 { "pavgw", { MX
, EM
}, PREFIX_OPCODE
},
2242 { "pmulhuw", { MX
, EM
}, PREFIX_OPCODE
},
2243 { "pmulhw", { MX
, EM
}, PREFIX_OPCODE
},
2244 { PREFIX_TABLE (PREFIX_0FE6
) },
2245 { PREFIX_TABLE (PREFIX_0FE7
) },
2247 { "psubsb", { MX
, EM
}, PREFIX_OPCODE
},
2248 { "psubsw", { MX
, EM
}, PREFIX_OPCODE
},
2249 { "pminsw", { MX
, EM
}, PREFIX_OPCODE
},
2250 { "por", { MX
, EM
}, PREFIX_OPCODE
},
2251 { "paddsb", { MX
, EM
}, PREFIX_OPCODE
},
2252 { "paddsw", { MX
, EM
}, PREFIX_OPCODE
},
2253 { "pmaxsw", { MX
, EM
}, PREFIX_OPCODE
},
2254 { "pxor", { MX
, EM
}, PREFIX_OPCODE
},
2256 { PREFIX_TABLE (PREFIX_0FF0
) },
2257 { "psllw", { MX
, EM
}, PREFIX_OPCODE
},
2258 { "pslld", { MX
, EM
}, PREFIX_OPCODE
},
2259 { "psllq", { MX
, EM
}, PREFIX_OPCODE
},
2260 { "pmuludq", { MX
, EM
}, PREFIX_OPCODE
},
2261 { "pmaddwd", { MX
, EM
}, PREFIX_OPCODE
},
2262 { "psadbw", { MX
, EM
}, PREFIX_OPCODE
},
2263 { PREFIX_TABLE (PREFIX_0FF7
) },
2265 { "psubb", { MX
, EM
}, PREFIX_OPCODE
},
2266 { "psubw", { MX
, EM
}, PREFIX_OPCODE
},
2267 { "psubd", { MX
, EM
}, PREFIX_OPCODE
},
2268 { "psubq", { MX
, EM
}, PREFIX_OPCODE
},
2269 { "paddb", { MX
, EM
}, PREFIX_OPCODE
},
2270 { "paddw", { MX
, EM
}, PREFIX_OPCODE
},
2271 { "paddd", { MX
, EM
}, PREFIX_OPCODE
},
2272 { "ud0S", { Gv
, Ev
}, 0 },
2275 static const unsigned char onebyte_has_modrm
[256] = {
2276 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2277 /* ------------------------------- */
2278 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2279 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2280 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2281 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2282 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2283 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2284 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2285 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2286 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2287 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2288 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2289 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2290 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2291 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2292 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2293 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
2294 /* ------------------------------- */
2295 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2298 static const unsigned char twobyte_has_modrm
[256] = {
2299 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2300 /* ------------------------------- */
2301 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2302 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2303 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2304 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2305 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2306 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2307 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2308 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2309 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2310 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2311 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2312 /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2313 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2314 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2315 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2316 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 /* ff */
2317 /* ------------------------------- */
2318 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2321 static char obuf
[100];
2323 static char *mnemonicendp
;
2324 static char scratchbuf
[100];
2325 static unsigned char *start_codep
;
2326 static unsigned char *insn_codep
;
2327 static unsigned char *codep
;
2328 static unsigned char *end_codep
;
2329 static int last_lock_prefix
;
2330 static int last_repz_prefix
;
2331 static int last_repnz_prefix
;
2332 static int last_data_prefix
;
2333 static int last_addr_prefix
;
2334 static int last_rex_prefix
;
2335 static int last_seg_prefix
;
2336 static int fwait_prefix
;
2337 /* The active segment register prefix. */
2338 static int active_seg_prefix
;
2339 #define MAX_CODE_LENGTH 15
2340 /* We can up to 14 prefixes since the maximum instruction length is
2342 static int all_prefixes
[MAX_CODE_LENGTH
- 1];
2343 static disassemble_info
*the_info
;
2351 static unsigned char need_modrm
;
2361 int register_specifier
;
2368 int mask_register_specifier
;
2374 static unsigned char need_vex
;
2382 /* If we are accessing mod/rm/reg without need_modrm set, then the
2383 values are stale. Hitting this abort likely indicates that you
2384 need to update onebyte_has_modrm or twobyte_has_modrm. */
2385 #define MODRM_CHECK if (!need_modrm) abort ()
2387 static const char **names64
;
2388 static const char **names32
;
2389 static const char **names16
;
2390 static const char **names8
;
2391 static const char **names8rex
;
2392 static const char **names_seg
;
2393 static const char *index64
;
2394 static const char *index32
;
2395 static const char **index16
;
2396 static const char **names_bnd
;
2398 static const char *intel_names64
[] = {
2399 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2400 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2402 static const char *intel_names32
[] = {
2403 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2404 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2406 static const char *intel_names16
[] = {
2407 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2408 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2410 static const char *intel_names8
[] = {
2411 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2413 static const char *intel_names8rex
[] = {
2414 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2415 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2417 static const char *intel_names_seg
[] = {
2418 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2420 static const char *intel_index64
= "riz";
2421 static const char *intel_index32
= "eiz";
2422 static const char *intel_index16
[] = {
2423 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2426 static const char *att_names64
[] = {
2427 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2428 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2430 static const char *att_names32
[] = {
2431 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2432 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2434 static const char *att_names16
[] = {
2435 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2436 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2438 static const char *att_names8
[] = {
2439 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2441 static const char *att_names8rex
[] = {
2442 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2443 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2445 static const char *att_names_seg
[] = {
2446 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2448 static const char *att_index64
= "%riz";
2449 static const char *att_index32
= "%eiz";
2450 static const char *att_index16
[] = {
2451 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2454 static const char **names_mm
;
2455 static const char *intel_names_mm
[] = {
2456 "mm0", "mm1", "mm2", "mm3",
2457 "mm4", "mm5", "mm6", "mm7"
2459 static const char *att_names_mm
[] = {
2460 "%mm0", "%mm1", "%mm2", "%mm3",
2461 "%mm4", "%mm5", "%mm6", "%mm7"
2464 static const char *intel_names_bnd
[] = {
2465 "bnd0", "bnd1", "bnd2", "bnd3"
2468 static const char *att_names_bnd
[] = {
2469 "%bnd0", "%bnd1", "%bnd2", "%bnd3"
2472 static const char **names_xmm
;
2473 static const char *intel_names_xmm
[] = {
2474 "xmm0", "xmm1", "xmm2", "xmm3",
2475 "xmm4", "xmm5", "xmm6", "xmm7",
2476 "xmm8", "xmm9", "xmm10", "xmm11",
2477 "xmm12", "xmm13", "xmm14", "xmm15",
2478 "xmm16", "xmm17", "xmm18", "xmm19",
2479 "xmm20", "xmm21", "xmm22", "xmm23",
2480 "xmm24", "xmm25", "xmm26", "xmm27",
2481 "xmm28", "xmm29", "xmm30", "xmm31"
2483 static const char *att_names_xmm
[] = {
2484 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
2485 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
2486 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
2487 "%xmm12", "%xmm13", "%xmm14", "%xmm15",
2488 "%xmm16", "%xmm17", "%xmm18", "%xmm19",
2489 "%xmm20", "%xmm21", "%xmm22", "%xmm23",
2490 "%xmm24", "%xmm25", "%xmm26", "%xmm27",
2491 "%xmm28", "%xmm29", "%xmm30", "%xmm31"
2494 static const char **names_ymm
;
2495 static const char *intel_names_ymm
[] = {
2496 "ymm0", "ymm1", "ymm2", "ymm3",
2497 "ymm4", "ymm5", "ymm6", "ymm7",
2498 "ymm8", "ymm9", "ymm10", "ymm11",
2499 "ymm12", "ymm13", "ymm14", "ymm15",
2500 "ymm16", "ymm17", "ymm18", "ymm19",
2501 "ymm20", "ymm21", "ymm22", "ymm23",
2502 "ymm24", "ymm25", "ymm26", "ymm27",
2503 "ymm28", "ymm29", "ymm30", "ymm31"
2505 static const char *att_names_ymm
[] = {
2506 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
2507 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
2508 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
2509 "%ymm12", "%ymm13", "%ymm14", "%ymm15",
2510 "%ymm16", "%ymm17", "%ymm18", "%ymm19",
2511 "%ymm20", "%ymm21", "%ymm22", "%ymm23",
2512 "%ymm24", "%ymm25", "%ymm26", "%ymm27",
2513 "%ymm28", "%ymm29", "%ymm30", "%ymm31"
2516 static const char **names_zmm
;
2517 static const char *intel_names_zmm
[] = {
2518 "zmm0", "zmm1", "zmm2", "zmm3",
2519 "zmm4", "zmm5", "zmm6", "zmm7",
2520 "zmm8", "zmm9", "zmm10", "zmm11",
2521 "zmm12", "zmm13", "zmm14", "zmm15",
2522 "zmm16", "zmm17", "zmm18", "zmm19",
2523 "zmm20", "zmm21", "zmm22", "zmm23",
2524 "zmm24", "zmm25", "zmm26", "zmm27",
2525 "zmm28", "zmm29", "zmm30", "zmm31"
2527 static const char *att_names_zmm
[] = {
2528 "%zmm0", "%zmm1", "%zmm2", "%zmm3",
2529 "%zmm4", "%zmm5", "%zmm6", "%zmm7",
2530 "%zmm8", "%zmm9", "%zmm10", "%zmm11",
2531 "%zmm12", "%zmm13", "%zmm14", "%zmm15",
2532 "%zmm16", "%zmm17", "%zmm18", "%zmm19",
2533 "%zmm20", "%zmm21", "%zmm22", "%zmm23",
2534 "%zmm24", "%zmm25", "%zmm26", "%zmm27",
2535 "%zmm28", "%zmm29", "%zmm30", "%zmm31"
2538 static const char **names_tmm
;
2539 static const char *intel_names_tmm
[] = {
2540 "tmm0", "tmm1", "tmm2", "tmm3",
2541 "tmm4", "tmm5", "tmm6", "tmm7"
2543 static const char *att_names_tmm
[] = {
2544 "%tmm0", "%tmm1", "%tmm2", "%tmm3",
2545 "%tmm4", "%tmm5", "%tmm6", "%tmm7"
2548 static const char **names_mask
;
2549 static const char *intel_names_mask
[] = {
2550 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
2552 static const char *att_names_mask
[] = {
2553 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
2556 static const char *names_rounding
[] =
2564 static const struct dis386 reg_table
[][8] = {
2567 { "addA", { Ebh1
, Ib
}, 0 },
2568 { "orA", { Ebh1
, Ib
}, 0 },
2569 { "adcA", { Ebh1
, Ib
}, 0 },
2570 { "sbbA", { Ebh1
, Ib
}, 0 },
2571 { "andA", { Ebh1
, Ib
}, 0 },
2572 { "subA", { Ebh1
, Ib
}, 0 },
2573 { "xorA", { Ebh1
, Ib
}, 0 },
2574 { "cmpA", { Eb
, Ib
}, 0 },
2578 { "addQ", { Evh1
, Iv
}, 0 },
2579 { "orQ", { Evh1
, Iv
}, 0 },
2580 { "adcQ", { Evh1
, Iv
}, 0 },
2581 { "sbbQ", { Evh1
, Iv
}, 0 },
2582 { "andQ", { Evh1
, Iv
}, 0 },
2583 { "subQ", { Evh1
, Iv
}, 0 },
2584 { "xorQ", { Evh1
, Iv
}, 0 },
2585 { "cmpQ", { Ev
, Iv
}, 0 },
2589 { "addQ", { Evh1
, sIb
}, 0 },
2590 { "orQ", { Evh1
, sIb
}, 0 },
2591 { "adcQ", { Evh1
, sIb
}, 0 },
2592 { "sbbQ", { Evh1
, sIb
}, 0 },
2593 { "andQ", { Evh1
, sIb
}, 0 },
2594 { "subQ", { Evh1
, sIb
}, 0 },
2595 { "xorQ", { Evh1
, sIb
}, 0 },
2596 { "cmpQ", { Ev
, sIb
}, 0 },
2600 { "pop{P|}", { stackEv
}, 0 },
2601 { XOP_8F_TABLE (XOP_09
) },
2605 { XOP_8F_TABLE (XOP_09
) },
2609 { "rolA", { Eb
, Ib
}, 0 },
2610 { "rorA", { Eb
, Ib
}, 0 },
2611 { "rclA", { Eb
, Ib
}, 0 },
2612 { "rcrA", { Eb
, Ib
}, 0 },
2613 { "shlA", { Eb
, Ib
}, 0 },
2614 { "shrA", { Eb
, Ib
}, 0 },
2615 { "shlA", { Eb
, Ib
}, 0 },
2616 { "sarA", { Eb
, Ib
}, 0 },
2620 { "rolQ", { Ev
, Ib
}, 0 },
2621 { "rorQ", { Ev
, Ib
}, 0 },
2622 { "rclQ", { Ev
, Ib
}, 0 },
2623 { "rcrQ", { Ev
, Ib
}, 0 },
2624 { "shlQ", { Ev
, Ib
}, 0 },
2625 { "shrQ", { Ev
, Ib
}, 0 },
2626 { "shlQ", { Ev
, Ib
}, 0 },
2627 { "sarQ", { Ev
, Ib
}, 0 },
2631 { "movA", { Ebh3
, Ib
}, 0 },
2638 { MOD_TABLE (MOD_C6_REG_7
) },
2642 { "movQ", { Evh3
, Iv
}, 0 },
2649 { MOD_TABLE (MOD_C7_REG_7
) },
2653 { "rolA", { Eb
, I1
}, 0 },
2654 { "rorA", { Eb
, I1
}, 0 },
2655 { "rclA", { Eb
, I1
}, 0 },
2656 { "rcrA", { Eb
, I1
}, 0 },
2657 { "shlA", { Eb
, I1
}, 0 },
2658 { "shrA", { Eb
, I1
}, 0 },
2659 { "shlA", { Eb
, I1
}, 0 },
2660 { "sarA", { Eb
, I1
}, 0 },
2664 { "rolQ", { Ev
, I1
}, 0 },
2665 { "rorQ", { Ev
, I1
}, 0 },
2666 { "rclQ", { Ev
, I1
}, 0 },
2667 { "rcrQ", { Ev
, I1
}, 0 },
2668 { "shlQ", { Ev
, I1
}, 0 },
2669 { "shrQ", { Ev
, I1
}, 0 },
2670 { "shlQ", { Ev
, I1
}, 0 },
2671 { "sarQ", { Ev
, I1
}, 0 },
2675 { "rolA", { Eb
, CL
}, 0 },
2676 { "rorA", { Eb
, CL
}, 0 },
2677 { "rclA", { Eb
, CL
}, 0 },
2678 { "rcrA", { Eb
, CL
}, 0 },
2679 { "shlA", { Eb
, CL
}, 0 },
2680 { "shrA", { Eb
, CL
}, 0 },
2681 { "shlA", { Eb
, CL
}, 0 },
2682 { "sarA", { Eb
, CL
}, 0 },
2686 { "rolQ", { Ev
, CL
}, 0 },
2687 { "rorQ", { Ev
, CL
}, 0 },
2688 { "rclQ", { Ev
, CL
}, 0 },
2689 { "rcrQ", { Ev
, CL
}, 0 },
2690 { "shlQ", { Ev
, CL
}, 0 },
2691 { "shrQ", { Ev
, CL
}, 0 },
2692 { "shlQ", { Ev
, CL
}, 0 },
2693 { "sarQ", { Ev
, CL
}, 0 },
2697 { "testA", { Eb
, Ib
}, 0 },
2698 { "testA", { Eb
, Ib
}, 0 },
2699 { "notA", { Ebh1
}, 0 },
2700 { "negA", { Ebh1
}, 0 },
2701 { "mulA", { Eb
}, 0 }, /* Don't print the implicit %al register, */
2702 { "imulA", { Eb
}, 0 }, /* to distinguish these opcodes from other */
2703 { "divA", { Eb
}, 0 }, /* mul/imul opcodes. Do the same for div */
2704 { "idivA", { Eb
}, 0 }, /* and idiv for consistency. */
2708 { "testQ", { Ev
, Iv
}, 0 },
2709 { "testQ", { Ev
, Iv
}, 0 },
2710 { "notQ", { Evh1
}, 0 },
2711 { "negQ", { Evh1
}, 0 },
2712 { "mulQ", { Ev
}, 0 }, /* Don't print the implicit register. */
2713 { "imulQ", { Ev
}, 0 },
2714 { "divQ", { Ev
}, 0 },
2715 { "idivQ", { Ev
}, 0 },
2719 { "incA", { Ebh1
}, 0 },
2720 { "decA", { Ebh1
}, 0 },
2724 { "incQ", { Evh1
}, 0 },
2725 { "decQ", { Evh1
}, 0 },
2726 { "call{@|}", { NOTRACK
, indirEv
, BND
}, 0 },
2727 { MOD_TABLE (MOD_FF_REG_3
) },
2728 { "jmp{@|}", { NOTRACK
, indirEv
, BND
}, 0 },
2729 { MOD_TABLE (MOD_FF_REG_5
) },
2730 { "push{P|}", { stackEv
}, 0 },
2735 { "sldtD", { Sv
}, 0 },
2736 { "strD", { Sv
}, 0 },
2737 { "lldt", { Ew
}, 0 },
2738 { "ltr", { Ew
}, 0 },
2739 { "verr", { Ew
}, 0 },
2740 { "verw", { Ew
}, 0 },
2746 { MOD_TABLE (MOD_0F01_REG_0
) },
2747 { MOD_TABLE (MOD_0F01_REG_1
) },
2748 { MOD_TABLE (MOD_0F01_REG_2
) },
2749 { MOD_TABLE (MOD_0F01_REG_3
) },
2750 { "smswD", { Sv
}, 0 },
2751 { MOD_TABLE (MOD_0F01_REG_5
) },
2752 { "lmsw", { Ew
}, 0 },
2753 { MOD_TABLE (MOD_0F01_REG_7
) },
2757 { "prefetch", { Mb
}, 0 },
2758 { "prefetchw", { Mb
}, 0 },
2759 { "prefetchwt1", { Mb
}, 0 },
2760 { "prefetch", { Mb
}, 0 },
2761 { "prefetch", { Mb
}, 0 },
2762 { "prefetch", { Mb
}, 0 },
2763 { "prefetch", { Mb
}, 0 },
2764 { "prefetch", { Mb
}, 0 },
2768 { MOD_TABLE (MOD_0F18_REG_0
) },
2769 { MOD_TABLE (MOD_0F18_REG_1
) },
2770 { MOD_TABLE (MOD_0F18_REG_2
) },
2771 { MOD_TABLE (MOD_0F18_REG_3
) },
2772 { "nopQ", { Ev
}, 0 },
2773 { "nopQ", { Ev
}, 0 },
2774 { "nopQ", { Ev
}, 0 },
2775 { "nopQ", { Ev
}, 0 },
2777 /* REG_0F1C_P_0_MOD_0 */
2779 { "cldemote", { Mb
}, 0 },
2780 { "nopQ", { Ev
}, 0 },
2781 { "nopQ", { Ev
}, 0 },
2782 { "nopQ", { Ev
}, 0 },
2783 { "nopQ", { Ev
}, 0 },
2784 { "nopQ", { Ev
}, 0 },
2785 { "nopQ", { Ev
}, 0 },
2786 { "nopQ", { Ev
}, 0 },
2788 /* REG_0F1E_P_1_MOD_3 */
2790 { "nopQ", { Ev
}, PREFIX_IGNORED
},
2791 { "rdsspK", { Edq
}, 0 },
2792 { "nopQ", { Ev
}, PREFIX_IGNORED
},
2793 { "nopQ", { Ev
}, PREFIX_IGNORED
},
2794 { "nopQ", { Ev
}, PREFIX_IGNORED
},
2795 { "nopQ", { Ev
}, PREFIX_IGNORED
},
2796 { "nopQ", { Ev
}, PREFIX_IGNORED
},
2797 { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7
) },
2799 /* REG_0F38D8_PREFIX_1 */
2801 { "aesencwide128kl", { M
}, 0 },
2802 { "aesdecwide128kl", { M
}, 0 },
2803 { "aesencwide256kl", { M
}, 0 },
2804 { "aesdecwide256kl", { M
}, 0 },
2806 /* REG_0F3A0F_PREFIX_1_MOD_3 */
2808 { RM_TABLE (RM_0F3A0F_P_1_MOD_3_REG_0
) },
2810 /* REG_0F71_MOD_0 */
2814 { "psrlw", { MS
, Ib
}, PREFIX_OPCODE
},
2816 { "psraw", { MS
, Ib
}, PREFIX_OPCODE
},
2818 { "psllw", { MS
, Ib
}, PREFIX_OPCODE
},
2820 /* REG_0F72_MOD_0 */
2824 { "psrld", { MS
, Ib
}, PREFIX_OPCODE
},
2826 { "psrad", { MS
, Ib
}, PREFIX_OPCODE
},
2828 { "pslld", { MS
, Ib
}, PREFIX_OPCODE
},
2830 /* REG_0F73_MOD_0 */
2834 { "psrlq", { MS
, Ib
}, PREFIX_OPCODE
},
2835 { "psrldq", { XS
, Ib
}, PREFIX_DATA
},
2838 { "psllq", { MS
, Ib
}, PREFIX_OPCODE
},
2839 { "pslldq", { XS
, Ib
}, PREFIX_DATA
},
2843 { "montmul", { { OP_0f07
, 0 } }, 0 },
2844 { "xsha1", { { OP_0f07
, 0 } }, 0 },
2845 { "xsha256", { { OP_0f07
, 0 } }, 0 },
2849 { "xstore-rng", { { OP_0f07
, 0 } }, 0 },
2850 { "xcrypt-ecb", { { OP_0f07
, 0 } }, 0 },
2851 { "xcrypt-cbc", { { OP_0f07
, 0 } }, 0 },
2852 { "xcrypt-ctr", { { OP_0f07
, 0 } }, 0 },
2853 { "xcrypt-cfb", { { OP_0f07
, 0 } }, 0 },
2854 { "xcrypt-ofb", { { OP_0f07
, 0 } }, 0 },
2858 { MOD_TABLE (MOD_0FAE_REG_0
) },
2859 { MOD_TABLE (MOD_0FAE_REG_1
) },
2860 { MOD_TABLE (MOD_0FAE_REG_2
) },
2861 { MOD_TABLE (MOD_0FAE_REG_3
) },
2862 { MOD_TABLE (MOD_0FAE_REG_4
) },
2863 { MOD_TABLE (MOD_0FAE_REG_5
) },
2864 { MOD_TABLE (MOD_0FAE_REG_6
) },
2865 { MOD_TABLE (MOD_0FAE_REG_7
) },
2873 { "btQ", { Ev
, Ib
}, 0 },
2874 { "btsQ", { Evh1
, Ib
}, 0 },
2875 { "btrQ", { Evh1
, Ib
}, 0 },
2876 { "btcQ", { Evh1
, Ib
}, 0 },
2881 { "cmpxchg8b", { { CMPXCHG8B_Fixup
, q_mode
} }, 0 },
2883 { MOD_TABLE (MOD_0FC7_REG_3
) },
2884 { MOD_TABLE (MOD_0FC7_REG_4
) },
2885 { MOD_TABLE (MOD_0FC7_REG_5
) },
2886 { MOD_TABLE (MOD_0FC7_REG_6
) },
2887 { MOD_TABLE (MOD_0FC7_REG_7
) },
2889 /* REG_VEX_0F71_M_0 */
2893 { "vpsrlw", { Vex
, XS
, Ib
}, PREFIX_DATA
},
2895 { "vpsraw", { Vex
, XS
, Ib
}, PREFIX_DATA
},
2897 { "vpsllw", { Vex
, XS
, Ib
}, PREFIX_DATA
},
2899 /* REG_VEX_0F72_M_0 */
2903 { "vpsrld", { Vex
, XS
, Ib
}, PREFIX_DATA
},
2905 { "vpsrad", { Vex
, XS
, Ib
}, PREFIX_DATA
},
2907 { "vpslld", { Vex
, XS
, Ib
}, PREFIX_DATA
},
2909 /* REG_VEX_0F73_M_0 */
2913 { "vpsrlq", { Vex
, XS
, Ib
}, PREFIX_DATA
},
2914 { "vpsrldq", { Vex
, XS
, Ib
}, PREFIX_DATA
},
2917 { "vpsllq", { Vex
, XS
, Ib
}, PREFIX_DATA
},
2918 { "vpslldq", { Vex
, XS
, Ib
}, PREFIX_DATA
},
2924 { MOD_TABLE (MOD_VEX_0FAE_REG_2
) },
2925 { MOD_TABLE (MOD_VEX_0FAE_REG_3
) },
2927 /* REG_VEX_0F3849_X86_64_P_0_W_0_M_1 */
2929 { RM_TABLE (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0
) },
2931 /* REG_VEX_0F38F3_L_0 */
2934 { "blsrS", { VexGdq
, Edq
}, PREFIX_OPCODE
},
2935 { "blsmskS", { VexGdq
, Edq
}, PREFIX_OPCODE
},
2936 { "blsiS", { VexGdq
, Edq
}, PREFIX_OPCODE
},
2938 /* REG_XOP_09_01_L_0 */
2941 { "blcfill", { VexGdq
, Edq
}, 0 },
2942 { "blsfill", { VexGdq
, Edq
}, 0 },
2943 { "blcs", { VexGdq
, Edq
}, 0 },
2944 { "tzmsk", { VexGdq
, Edq
}, 0 },
2945 { "blcic", { VexGdq
, Edq
}, 0 },
2946 { "blsic", { VexGdq
, Edq
}, 0 },
2947 { "t1mskc", { VexGdq
, Edq
}, 0 },
2949 /* REG_XOP_09_02_L_0 */
2952 { "blcmsk", { VexGdq
, Edq
}, 0 },
2957 { "blci", { VexGdq
, Edq
}, 0 },
2959 /* REG_XOP_09_12_M_1_L_0 */
2961 { "llwpcb", { Edq
}, 0 },
2962 { "slwpcb", { Edq
}, 0 },
2964 /* REG_XOP_0A_12_L_0 */
2966 { "lwpins", { VexGdq
, Ed
, Id
}, 0 },
2967 { "lwpval", { VexGdq
, Ed
, Id
}, 0 },
2970 #include "i386-dis-evex-reg.h"
2973 static const struct dis386 prefix_table
[][4] = {
2976 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} }, 0 },
2977 { "pause", { XX
}, 0 },
2978 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} }, 0 },
2979 { NULL
, { { NULL
, 0 } }, PREFIX_IGNORED
}
2982 /* PREFIX_0F01_REG_1_RM_4 */
2986 { "tdcall", { Skip_MODRM
}, 0 },
2990 /* PREFIX_0F01_REG_1_RM_5 */
2994 { X86_64_TABLE (X86_64_0F01_REG_1_RM_5_PREFIX_2
) },
2998 /* PREFIX_0F01_REG_1_RM_6 */
3002 { X86_64_TABLE (X86_64_0F01_REG_1_RM_6_PREFIX_2
) },
3006 /* PREFIX_0F01_REG_1_RM_7 */
3008 { "encls", { Skip_MODRM
}, 0 },
3010 { X86_64_TABLE (X86_64_0F01_REG_1_RM_7_PREFIX_2
) },
3014 /* PREFIX_0F01_REG_3_RM_1 */
3016 { "vmmcall", { Skip_MODRM
}, 0 },
3017 { "vmgexit", { Skip_MODRM
}, 0 },
3019 { "vmgexit", { Skip_MODRM
}, 0 },
3022 /* PREFIX_0F01_REG_5_MOD_0 */
3025 { "rstorssp", { Mq
}, PREFIX_OPCODE
},
3028 /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
3030 { "serialize", { Skip_MODRM
}, PREFIX_OPCODE
},
3031 { "setssbsy", { Skip_MODRM
}, PREFIX_OPCODE
},
3033 { "xsusldtrk", { Skip_MODRM
}, PREFIX_OPCODE
},
3036 /* PREFIX_0F01_REG_5_MOD_3_RM_1 */
3041 { "xresldtrk", { Skip_MODRM
}, PREFIX_OPCODE
},
3044 /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
3047 { "saveprevssp", { Skip_MODRM
}, PREFIX_OPCODE
},
3050 /* PREFIX_0F01_REG_5_MOD_3_RM_4 */
3053 { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1
) },
3056 /* PREFIX_0F01_REG_5_MOD_3_RM_5 */
3059 { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1
) },
3062 /* PREFIX_0F01_REG_5_MOD_3_RM_6 */
3064 { "rdpkru", { Skip_MODRM
}, 0 },
3065 { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1
) },
3068 /* PREFIX_0F01_REG_5_MOD_3_RM_7 */
3070 { "wrpkru", { Skip_MODRM
}, 0 },
3071 { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1
) },
3074 /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
3076 { "monitorx", { { OP_Monitor
, 0 } }, 0 },
3077 { "mcommit", { Skip_MODRM
}, 0 },
3080 /* PREFIX_0F01_REG_7_MOD_3_RM_6 */
3082 { "invlpgb", { Skip_MODRM
}, 0 },
3083 { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1
) },
3085 { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3
) },
3088 /* PREFIX_0F01_REG_7_MOD_3_RM_7 */
3090 { "tlbsync", { Skip_MODRM
}, 0 },
3091 { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1
) },
3093 { "pvalidate", { Skip_MODRM
}, 0 },
3098 { "wbinvd", { XX
}, 0 },
3099 { "wbnoinvd", { XX
}, 0 },
3104 { "movups", { XM
, EXx
}, PREFIX_OPCODE
},
3105 { "movss", { XM
, EXd
}, PREFIX_OPCODE
},
3106 { "movupd", { XM
, EXx
}, PREFIX_OPCODE
},
3107 { "movsd", { XM
, EXq
}, PREFIX_OPCODE
},
3112 { "movups", { EXxS
, XM
}, PREFIX_OPCODE
},
3113 { "movss", { EXdS
, XM
}, PREFIX_OPCODE
},
3114 { "movupd", { EXxS
, XM
}, PREFIX_OPCODE
},
3115 { "movsd", { EXqS
, XM
}, PREFIX_OPCODE
},
3120 { MOD_TABLE (MOD_0F12_PREFIX_0
) },
3121 { "movsldup", { XM
, EXx
}, PREFIX_OPCODE
},
3122 { MOD_TABLE (MOD_0F12_PREFIX_2
) },
3123 { "movddup", { XM
, EXq
}, PREFIX_OPCODE
},
3128 { MOD_TABLE (MOD_0F16_PREFIX_0
) },
3129 { "movshdup", { XM
, EXx
}, PREFIX_OPCODE
},
3130 { MOD_TABLE (MOD_0F16_PREFIX_2
) },
3135 { MOD_TABLE (MOD_0F1A_PREFIX_0
) },
3136 { "bndcl", { Gbnd
, Ev_bnd
}, 0 },
3137 { "bndmov", { Gbnd
, Ebnd
}, 0 },
3138 { "bndcu", { Gbnd
, Ev_bnd
}, 0 },
3143 { MOD_TABLE (MOD_0F1B_PREFIX_0
) },
3144 { MOD_TABLE (MOD_0F1B_PREFIX_1
) },
3145 { "bndmov", { EbndS
, Gbnd
}, 0 },
3146 { "bndcn", { Gbnd
, Ev_bnd
}, 0 },
3151 { MOD_TABLE (MOD_0F1C_PREFIX_0
) },
3152 { "nopQ", { Ev
}, PREFIX_IGNORED
},
3153 { "nopQ", { Ev
}, 0 },
3154 { "nopQ", { Ev
}, PREFIX_IGNORED
},
3159 { "nopQ", { Ev
}, 0 },
3160 { MOD_TABLE (MOD_0F1E_PREFIX_1
) },
3161 { "nopQ", { Ev
}, 0 },
3162 { NULL
, { XX
}, PREFIX_IGNORED
},
3167 { "cvtpi2ps", { XM
, EMCq
}, PREFIX_OPCODE
},
3168 { "cvtsi2ss{%LQ|}", { XM
, Edq
}, PREFIX_OPCODE
},
3169 { "cvtpi2pd", { XM
, EMCq
}, PREFIX_OPCODE
},
3170 { "cvtsi2sd{%LQ|}", { XM
, Edq
}, 0 },
3175 { MOD_TABLE (MOD_0F2B_PREFIX_0
) },
3176 { MOD_TABLE (MOD_0F2B_PREFIX_1
) },
3177 { MOD_TABLE (MOD_0F2B_PREFIX_2
) },
3178 { MOD_TABLE (MOD_0F2B_PREFIX_3
) },
3183 { "cvttps2pi", { MXC
, EXq
}, PREFIX_OPCODE
},
3184 { "cvttss2si", { Gdq
, EXd
}, PREFIX_OPCODE
},
3185 { "cvttpd2pi", { MXC
, EXx
}, PREFIX_OPCODE
},
3186 { "cvttsd2si", { Gdq
, EXq
}, PREFIX_OPCODE
},
3191 { "cvtps2pi", { MXC
, EXq
}, PREFIX_OPCODE
},
3192 { "cvtss2si", { Gdq
, EXd
}, PREFIX_OPCODE
},
3193 { "cvtpd2pi", { MXC
, EXx
}, PREFIX_OPCODE
},
3194 { "cvtsd2si", { Gdq
, EXq
}, PREFIX_OPCODE
},
3199 { "ucomiss",{ XM
, EXd
}, 0 },
3201 { "ucomisd",{ XM
, EXq
}, 0 },
3206 { "comiss", { XM
, EXd
}, 0 },
3208 { "comisd", { XM
, EXq
}, 0 },
3213 { "sqrtps", { XM
, EXx
}, PREFIX_OPCODE
},
3214 { "sqrtss", { XM
, EXd
}, PREFIX_OPCODE
},
3215 { "sqrtpd", { XM
, EXx
}, PREFIX_OPCODE
},
3216 { "sqrtsd", { XM
, EXq
}, PREFIX_OPCODE
},
3221 { "rsqrtps",{ XM
, EXx
}, PREFIX_OPCODE
},
3222 { "rsqrtss",{ XM
, EXd
}, PREFIX_OPCODE
},
3227 { "rcpps", { XM
, EXx
}, PREFIX_OPCODE
},
3228 { "rcpss", { XM
, EXd
}, PREFIX_OPCODE
},
3233 { "addps", { XM
, EXx
}, PREFIX_OPCODE
},
3234 { "addss", { XM
, EXd
}, PREFIX_OPCODE
},
3235 { "addpd", { XM
, EXx
}, PREFIX_OPCODE
},
3236 { "addsd", { XM
, EXq
}, PREFIX_OPCODE
},
3241 { "mulps", { XM
, EXx
}, PREFIX_OPCODE
},
3242 { "mulss", { XM
, EXd
}, PREFIX_OPCODE
},
3243 { "mulpd", { XM
, EXx
}, PREFIX_OPCODE
},
3244 { "mulsd", { XM
, EXq
}, PREFIX_OPCODE
},
3249 { "cvtps2pd", { XM
, EXq
}, PREFIX_OPCODE
},
3250 { "cvtss2sd", { XM
, EXd
}, PREFIX_OPCODE
},
3251 { "cvtpd2ps", { XM
, EXx
}, PREFIX_OPCODE
},
3252 { "cvtsd2ss", { XM
, EXq
}, PREFIX_OPCODE
},
3257 { "cvtdq2ps", { XM
, EXx
}, PREFIX_OPCODE
},
3258 { "cvttps2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3259 { "cvtps2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3264 { "subps", { XM
, EXx
}, PREFIX_OPCODE
},
3265 { "subss", { XM
, EXd
}, PREFIX_OPCODE
},
3266 { "subpd", { XM
, EXx
}, PREFIX_OPCODE
},
3267 { "subsd", { XM
, EXq
}, PREFIX_OPCODE
},
3272 { "minps", { XM
, EXx
}, PREFIX_OPCODE
},
3273 { "minss", { XM
, EXd
}, PREFIX_OPCODE
},
3274 { "minpd", { XM
, EXx
}, PREFIX_OPCODE
},
3275 { "minsd", { XM
, EXq
}, PREFIX_OPCODE
},
3280 { "divps", { XM
, EXx
}, PREFIX_OPCODE
},
3281 { "divss", { XM
, EXd
}, PREFIX_OPCODE
},
3282 { "divpd", { XM
, EXx
}, PREFIX_OPCODE
},
3283 { "divsd", { XM
, EXq
}, PREFIX_OPCODE
},
3288 { "maxps", { XM
, EXx
}, PREFIX_OPCODE
},
3289 { "maxss", { XM
, EXd
}, PREFIX_OPCODE
},
3290 { "maxpd", { XM
, EXx
}, PREFIX_OPCODE
},
3291 { "maxsd", { XM
, EXq
}, PREFIX_OPCODE
},
3296 { "punpcklbw",{ MX
, EMd
}, PREFIX_OPCODE
},
3298 { "punpcklbw",{ MX
, EMx
}, PREFIX_OPCODE
},
3303 { "punpcklwd",{ MX
, EMd
}, PREFIX_OPCODE
},
3305 { "punpcklwd",{ MX
, EMx
}, PREFIX_OPCODE
},
3310 { "punpckldq",{ MX
, EMd
}, PREFIX_OPCODE
},
3312 { "punpckldq",{ MX
, EMx
}, PREFIX_OPCODE
},
3317 { "movq", { MX
, EM
}, PREFIX_OPCODE
},
3318 { "movdqu", { XM
, EXx
}, PREFIX_OPCODE
},
3319 { "movdqa", { XM
, EXx
}, PREFIX_OPCODE
},
3324 { "pshufw", { MX
, EM
, Ib
}, PREFIX_OPCODE
},
3325 { "pshufhw",{ XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3326 { "pshufd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3327 { "pshuflw",{ XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3332 {"vmread", { Em
, Gm
}, 0 },
3334 {"extrq", { XS
, Ib
, Ib
}, 0 },
3335 {"insertq", { XM
, XS
, Ib
, Ib
}, 0 },
3340 {"vmwrite", { Gm
, Em
}, 0 },
3342 {"extrq", { XM
, XS
}, 0 },
3343 {"insertq", { XM
, XS
}, 0 },
3350 { "haddpd", { XM
, EXx
}, PREFIX_OPCODE
},
3351 { "haddps", { XM
, EXx
}, PREFIX_OPCODE
},
3358 { "hsubpd", { XM
, EXx
}, PREFIX_OPCODE
},
3359 { "hsubps", { XM
, EXx
}, PREFIX_OPCODE
},
3364 { "movK", { Edq
, MX
}, PREFIX_OPCODE
},
3365 { "movq", { XM
, EXq
}, PREFIX_OPCODE
},
3366 { "movK", { Edq
, XM
}, PREFIX_OPCODE
},
3371 { "movq", { EMS
, MX
}, PREFIX_OPCODE
},
3372 { "movdqu", { EXxS
, XM
}, PREFIX_OPCODE
},
3373 { "movdqa", { EXxS
, XM
}, PREFIX_OPCODE
},
3376 /* PREFIX_0FAE_REG_0_MOD_3 */
3379 { "rdfsbase", { Ev
}, 0 },
3382 /* PREFIX_0FAE_REG_1_MOD_3 */
3385 { "rdgsbase", { Ev
}, 0 },
3388 /* PREFIX_0FAE_REG_2_MOD_3 */
3391 { "wrfsbase", { Ev
}, 0 },
3394 /* PREFIX_0FAE_REG_3_MOD_3 */
3397 { "wrgsbase", { Ev
}, 0 },
3400 /* PREFIX_0FAE_REG_4_MOD_0 */
3402 { "xsave", { FXSAVE
}, 0 },
3403 { "ptwrite{%LQ|}", { Edq
}, 0 },
3406 /* PREFIX_0FAE_REG_4_MOD_3 */
3409 { "ptwrite{%LQ|}", { Edq
}, 0 },
3412 /* PREFIX_0FAE_REG_5_MOD_3 */
3414 { "lfence", { Skip_MODRM
}, 0 },
3415 { "incsspK", { Edq
}, PREFIX_OPCODE
},
3418 /* PREFIX_0FAE_REG_6_MOD_0 */
3420 { "xsaveopt", { FXSAVE
}, PREFIX_OPCODE
},
3421 { "clrssbsy", { Mq
}, PREFIX_OPCODE
},
3422 { "clwb", { Mb
}, PREFIX_OPCODE
},
3425 /* PREFIX_0FAE_REG_6_MOD_3 */
3427 { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0
) },
3428 { "umonitor", { Eva
}, PREFIX_OPCODE
},
3429 { "tpause", { Edq
}, PREFIX_OPCODE
},
3430 { "umwait", { Edq
}, PREFIX_OPCODE
},
3433 /* PREFIX_0FAE_REG_7_MOD_0 */
3435 { "clflush", { Mb
}, 0 },
3437 { "clflushopt", { Mb
}, 0 },
3443 { "popcntS", { Gv
, Ev
}, 0 },
3448 { "bsfS", { Gv
, Ev
}, 0 },
3449 { "tzcntS", { Gv
, Ev
}, 0 },
3450 { "bsfS", { Gv
, Ev
}, 0 },
3455 { "bsrS", { Gv
, Ev
}, 0 },
3456 { "lzcntS", { Gv
, Ev
}, 0 },
3457 { "bsrS", { Gv
, Ev
}, 0 },
3462 { "cmpps", { XM
, EXx
, CMP
}, PREFIX_OPCODE
},
3463 { "cmpss", { XM
, EXd
, CMP
}, PREFIX_OPCODE
},
3464 { "cmppd", { XM
, EXx
, CMP
}, PREFIX_OPCODE
},
3465 { "cmpsd", { XM
, EXq
, CMP
}, PREFIX_OPCODE
},
3468 /* PREFIX_0FC7_REG_6_MOD_0 */
3470 { "vmptrld",{ Mq
}, 0 },
3471 { "vmxon", { Mq
}, 0 },
3472 { "vmclear",{ Mq
}, 0 },
3475 /* PREFIX_0FC7_REG_6_MOD_3 */
3477 { "rdrand", { Ev
}, 0 },
3478 { X86_64_TABLE (X86_64_0FC7_REG_6_MOD_3_PREFIX_1
) },
3479 { "rdrand", { Ev
}, 0 }
3482 /* PREFIX_0FC7_REG_7_MOD_3 */
3484 { "rdseed", { Ev
}, 0 },
3485 { "rdpid", { Em
}, 0 },
3486 { "rdseed", { Ev
}, 0 },
3493 { "addsubpd", { XM
, EXx
}, 0 },
3494 { "addsubps", { XM
, EXx
}, 0 },
3500 { "movq2dq",{ XM
, MS
}, 0 },
3501 { "movq", { EXqS
, XM
}, 0 },
3502 { "movdq2q",{ MX
, XS
}, 0 },
3508 { "cvtdq2pd", { XM
, EXq
}, PREFIX_OPCODE
},
3509 { "cvttpd2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3510 { "cvtpd2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3515 { "movntq", { Mq
, MX
}, PREFIX_OPCODE
},
3517 { MOD_TABLE (MOD_0FE7_PREFIX_2
) },
3525 { MOD_TABLE (MOD_0FF0_PREFIX_3
) },
3530 { "maskmovq", { MX
, MS
}, PREFIX_OPCODE
},
3532 { "maskmovdqu", { XM
, XS
}, PREFIX_OPCODE
},
3538 { REG_TABLE (REG_0F38D8_PREFIX_1
) },
3544 { MOD_TABLE (MOD_0F38DC_PREFIX_1
) },
3545 { "aesenc", { XM
, EXx
}, 0 },
3551 { MOD_TABLE (MOD_0F38DD_PREFIX_1
) },
3552 { "aesenclast", { XM
, EXx
}, 0 },
3558 { MOD_TABLE (MOD_0F38DE_PREFIX_1
) },
3559 { "aesdec", { XM
, EXx
}, 0 },
3565 { MOD_TABLE (MOD_0F38DF_PREFIX_1
) },
3566 { "aesdeclast", { XM
, EXx
}, 0 },
3571 { "movbeS", { Gv
, Mv
}, PREFIX_OPCODE
},
3573 { "movbeS", { Gv
, Mv
}, PREFIX_OPCODE
},
3574 { "crc32A", { Gdq
, Eb
}, PREFIX_OPCODE
},
3579 { "movbeS", { Mv
, Gv
}, PREFIX_OPCODE
},
3581 { "movbeS", { Mv
, Gv
}, PREFIX_OPCODE
},
3582 { "crc32Q", { Gdq
, Ev
}, PREFIX_OPCODE
},
3587 { MOD_TABLE (MOD_0F38F6_PREFIX_0
) },
3588 { "adoxS", { Gdq
, Edq
}, PREFIX_OPCODE
},
3589 { "adcxS", { Gdq
, Edq
}, PREFIX_OPCODE
},
3596 { MOD_TABLE (MOD_0F38F8_PREFIX_1
) },
3597 { MOD_TABLE (MOD_0F38F8_PREFIX_2
) },
3598 { MOD_TABLE (MOD_0F38F8_PREFIX_3
) },
3603 { MOD_TABLE (MOD_0F38FA_PREFIX_1
) },
3609 { MOD_TABLE (MOD_0F38FB_PREFIX_1
) },
3615 { MOD_TABLE (MOD_0F3A0F_PREFIX_1
)},
3618 /* PREFIX_VEX_0F10 */
3620 { "vmovups", { XM
, EXx
}, 0 },
3621 { "vmovss", { XMScalar
, VexScalarR
, EXxmm_md
}, 0 },
3622 { "vmovupd", { XM
, EXx
}, 0 },
3623 { "vmovsd", { XMScalar
, VexScalarR
, EXxmm_mq
}, 0 },
3626 /* PREFIX_VEX_0F11 */
3628 { "vmovups", { EXxS
, XM
}, 0 },
3629 { "vmovss", { EXdS
, VexScalarR
, XMScalar
}, 0 },
3630 { "vmovupd", { EXxS
, XM
}, 0 },
3631 { "vmovsd", { EXqS
, VexScalarR
, XMScalar
}, 0 },
3634 /* PREFIX_VEX_0F12 */
3636 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0
) },
3637 { "vmovsldup", { XM
, EXx
}, 0 },
3638 { MOD_TABLE (MOD_VEX_0F12_PREFIX_2
) },
3639 { "vmovddup", { XM
, EXymmq
}, 0 },
3642 /* PREFIX_VEX_0F16 */
3644 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0
) },
3645 { "vmovshdup", { XM
, EXx
}, 0 },
3646 { MOD_TABLE (MOD_VEX_0F16_PREFIX_2
) },
3649 /* PREFIX_VEX_0F2A */
3652 { "vcvtsi2ss{%LQ|}", { XMScalar
, VexScalar
, Edq
}, 0 },
3654 { "vcvtsi2sd{%LQ|}", { XMScalar
, VexScalar
, Edq
}, 0 },
3657 /* PREFIX_VEX_0F2C */
3660 { "vcvttss2si", { Gdq
, EXxmm_md
, EXxEVexS
}, 0 },
3662 { "vcvttsd2si", { Gdq
, EXxmm_mq
, EXxEVexS
}, 0 },
3665 /* PREFIX_VEX_0F2D */
3668 { "vcvtss2si", { Gdq
, EXxmm_md
, EXxEVexR
}, 0 },
3670 { "vcvtsd2si", { Gdq
, EXxmm_mq
, EXxEVexR
}, 0 },
3673 /* PREFIX_VEX_0F2E */
3675 { "vucomisX", { XMScalar
, EXxmm_md
, EXxEVexS
}, PREFIX_OPCODE
},
3677 { "vucomisX", { XMScalar
, EXxmm_mq
, EXxEVexS
}, PREFIX_OPCODE
},
3680 /* PREFIX_VEX_0F2F */
3682 { "vcomisX", { XMScalar
, EXxmm_md
, EXxEVexS
}, PREFIX_OPCODE
},
3684 { "vcomisX", { XMScalar
, EXxmm_mq
, EXxEVexS
}, PREFIX_OPCODE
},
3687 /* PREFIX_VEX_0F41_L_1_M_1_W_0 */
3689 { "kandw", { MaskG
, MaskVex
, MaskE
}, 0 },
3691 { "kandb", { MaskG
, MaskVex
, MaskE
}, 0 },
3694 /* PREFIX_VEX_0F41_L_1_M_1_W_1 */
3696 { "kandq", { MaskG
, MaskVex
, MaskE
}, 0 },
3698 { "kandd", { MaskG
, MaskVex
, MaskE
}, 0 },
3701 /* PREFIX_VEX_0F42_L_1_M_1_W_0 */
3703 { "kandnw", { MaskG
, MaskVex
, MaskE
}, 0 },
3705 { "kandnb", { MaskG
, MaskVex
, MaskE
}, 0 },
3708 /* PREFIX_VEX_0F42_L_1_M_1_W_1 */
3710 { "kandnq", { MaskG
, MaskVex
, MaskE
}, 0 },
3712 { "kandnd", { MaskG
, MaskVex
, MaskE
}, 0 },
3715 /* PREFIX_VEX_0F44_L_0_M_1_W_0 */
3717 { "knotw", { MaskG
, MaskE
}, 0 },
3719 { "knotb", { MaskG
, MaskE
}, 0 },
3722 /* PREFIX_VEX_0F44_L_0_M_1_W_1 */
3724 { "knotq", { MaskG
, MaskE
}, 0 },
3726 { "knotd", { MaskG
, MaskE
}, 0 },
3729 /* PREFIX_VEX_0F45_L_1_M_1_W_0 */
3731 { "korw", { MaskG
, MaskVex
, MaskE
}, 0 },
3733 { "korb", { MaskG
, MaskVex
, MaskE
}, 0 },
3736 /* PREFIX_VEX_0F45_L_1_M_1_W_1 */
3738 { "korq", { MaskG
, MaskVex
, MaskE
}, 0 },
3740 { "kord", { MaskG
, MaskVex
, MaskE
}, 0 },
3743 /* PREFIX_VEX_0F46_L_1_M_1_W_0 */
3745 { "kxnorw", { MaskG
, MaskVex
, MaskE
}, 0 },
3747 { "kxnorb", { MaskG
, MaskVex
, MaskE
}, 0 },
3750 /* PREFIX_VEX_0F46_L_1_M_1_W_1 */
3752 { "kxnorq", { MaskG
, MaskVex
, MaskE
}, 0 },
3754 { "kxnord", { MaskG
, MaskVex
, MaskE
}, 0 },
3757 /* PREFIX_VEX_0F47_L_1_M_1_W_0 */
3759 { "kxorw", { MaskG
, MaskVex
, MaskE
}, 0 },
3761 { "kxorb", { MaskG
, MaskVex
, MaskE
}, 0 },
3764 /* PREFIX_VEX_0F47_L_1_M_1_W_1 */
3766 { "kxorq", { MaskG
, MaskVex
, MaskE
}, 0 },
3768 { "kxord", { MaskG
, MaskVex
, MaskE
}, 0 },
3771 /* PREFIX_VEX_0F4A_L_1_M_1_W_0 */
3773 { "kaddw", { MaskG
, MaskVex
, MaskE
}, 0 },
3775 { "kaddb", { MaskG
, MaskVex
, MaskE
}, 0 },
3778 /* PREFIX_VEX_0F4A_L_1_M_1_W_1 */
3780 { "kaddq", { MaskG
, MaskVex
, MaskE
}, 0 },
3782 { "kaddd", { MaskG
, MaskVex
, MaskE
}, 0 },
3785 /* PREFIX_VEX_0F4B_L_1_M_1_W_0 */
3787 { "kunpckwd", { MaskG
, MaskVex
, MaskE
}, 0 },
3789 { "kunpckbw", { MaskG
, MaskVex
, MaskE
}, 0 },
3792 /* PREFIX_VEX_0F4B_L_1_M_1_W_1 */
3794 { "kunpckdq", { MaskG
, MaskVex
, MaskE
}, 0 },
3797 /* PREFIX_VEX_0F51 */
3799 { "vsqrtps", { XM
, EXx
}, 0 },
3800 { "vsqrtss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
3801 { "vsqrtpd", { XM
, EXx
}, 0 },
3802 { "vsqrtsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
3805 /* PREFIX_VEX_0F52 */
3807 { "vrsqrtps", { XM
, EXx
}, 0 },
3808 { "vrsqrtss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
3811 /* PREFIX_VEX_0F53 */
3813 { "vrcpps", { XM
, EXx
}, 0 },
3814 { "vrcpss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
3817 /* PREFIX_VEX_0F58 */
3819 { "vaddps", { XM
, Vex
, EXx
}, 0 },
3820 { "vaddss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
3821 { "vaddpd", { XM
, Vex
, EXx
}, 0 },
3822 { "vaddsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
3825 /* PREFIX_VEX_0F59 */
3827 { "vmulps", { XM
, Vex
, EXx
}, 0 },
3828 { "vmulss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
3829 { "vmulpd", { XM
, Vex
, EXx
}, 0 },
3830 { "vmulsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
3833 /* PREFIX_VEX_0F5A */
3835 { "vcvtps2pd", { XM
, EXxmmq
}, 0 },
3836 { "vcvtss2sd", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
3837 { "vcvtpd2ps%XY",{ XMM
, EXx
}, 0 },
3838 { "vcvtsd2ss", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
3841 /* PREFIX_VEX_0F5B */
3843 { "vcvtdq2ps", { XM
, EXx
}, 0 },
3844 { "vcvttps2dq", { XM
, EXx
}, 0 },
3845 { "vcvtps2dq", { XM
, EXx
}, 0 },
3848 /* PREFIX_VEX_0F5C */
3850 { "vsubps", { XM
, Vex
, EXx
}, 0 },
3851 { "vsubss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
3852 { "vsubpd", { XM
, Vex
, EXx
}, 0 },
3853 { "vsubsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
3856 /* PREFIX_VEX_0F5D */
3858 { "vminps", { XM
, Vex
, EXx
}, 0 },
3859 { "vminss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
3860 { "vminpd", { XM
, Vex
, EXx
}, 0 },
3861 { "vminsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
3864 /* PREFIX_VEX_0F5E */
3866 { "vdivps", { XM
, Vex
, EXx
}, 0 },
3867 { "vdivss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
3868 { "vdivpd", { XM
, Vex
, EXx
}, 0 },
3869 { "vdivsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
3872 /* PREFIX_VEX_0F5F */
3874 { "vmaxps", { XM
, Vex
, EXx
}, 0 },
3875 { "vmaxss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
3876 { "vmaxpd", { XM
, Vex
, EXx
}, 0 },
3877 { "vmaxsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
3880 /* PREFIX_VEX_0F6F */
3883 { "vmovdqu", { XM
, EXx
}, 0 },
3884 { "vmovdqa", { XM
, EXx
}, 0 },
3887 /* PREFIX_VEX_0F70 */
3890 { "vpshufhw", { XM
, EXx
, Ib
}, 0 },
3891 { "vpshufd", { XM
, EXx
, Ib
}, 0 },
3892 { "vpshuflw", { XM
, EXx
, Ib
}, 0 },
3895 /* PREFIX_VEX_0F7C */
3899 { "vhaddpd", { XM
, Vex
, EXx
}, 0 },
3900 { "vhaddps", { XM
, Vex
, EXx
}, 0 },
3903 /* PREFIX_VEX_0F7D */
3907 { "vhsubpd", { XM
, Vex
, EXx
}, 0 },
3908 { "vhsubps", { XM
, Vex
, EXx
}, 0 },
3911 /* PREFIX_VEX_0F7E */
3914 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1
) },
3915 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2
) },
3918 /* PREFIX_VEX_0F7F */
3921 { "vmovdqu", { EXxS
, XM
}, 0 },
3922 { "vmovdqa", { EXxS
, XM
}, 0 },
3925 /* PREFIX_VEX_0F90_L_0_W_0 */
3927 { "kmovw", { MaskG
, MaskE
}, 0 },
3929 { "kmovb", { MaskG
, MaskBDE
}, 0 },
3932 /* PREFIX_VEX_0F90_L_0_W_1 */
3934 { "kmovq", { MaskG
, MaskE
}, 0 },
3936 { "kmovd", { MaskG
, MaskBDE
}, 0 },
3939 /* PREFIX_VEX_0F91_L_0_M_0_W_0 */
3941 { "kmovw", { Ew
, MaskG
}, 0 },
3943 { "kmovb", { Eb
, MaskG
}, 0 },
3946 /* PREFIX_VEX_0F91_L_0_M_0_W_1 */
3948 { "kmovq", { Eq
, MaskG
}, 0 },
3950 { "kmovd", { Ed
, MaskG
}, 0 },
3953 /* PREFIX_VEX_0F92_L_0_M_1_W_0 */
3955 { "kmovw", { MaskG
, Edq
}, 0 },
3957 { "kmovb", { MaskG
, Edq
}, 0 },
3958 { "kmovd", { MaskG
, Edq
}, 0 },
3961 /* PREFIX_VEX_0F92_L_0_M_1_W_1 */
3966 { "kmovK", { MaskG
, Edq
}, 0 },
3969 /* PREFIX_VEX_0F93_L_0_M_1_W_0 */
3971 { "kmovw", { Gdq
, MaskE
}, 0 },
3973 { "kmovb", { Gdq
, MaskE
}, 0 },
3974 { "kmovd", { Gdq
, MaskE
}, 0 },
3977 /* PREFIX_VEX_0F93_L_0_M_1_W_1 */
3982 { "kmovK", { Gdq
, MaskE
}, 0 },
3985 /* PREFIX_VEX_0F98_L_0_M_1_W_0 */
3987 { "kortestw", { MaskG
, MaskE
}, 0 },
3989 { "kortestb", { MaskG
, MaskE
}, 0 },
3992 /* PREFIX_VEX_0F98_L_0_M_1_W_1 */
3994 { "kortestq", { MaskG
, MaskE
}, 0 },
3996 { "kortestd", { MaskG
, MaskE
}, 0 },
3999 /* PREFIX_VEX_0F99_L_0_M_1_W_0 */
4001 { "ktestw", { MaskG
, MaskE
}, 0 },
4003 { "ktestb", { MaskG
, MaskE
}, 0 },
4006 /* PREFIX_VEX_0F99_L_0_M_1_W_1 */
4008 { "ktestq", { MaskG
, MaskE
}, 0 },
4010 { "ktestd", { MaskG
, MaskE
}, 0 },
4013 /* PREFIX_VEX_0FC2 */
4015 { "vcmpps", { XM
, Vex
, EXx
, CMP
}, 0 },
4016 { "vcmpss", { XMScalar
, VexScalar
, EXxmm_md
, CMP
}, 0 },
4017 { "vcmppd", { XM
, Vex
, EXx
, CMP
}, 0 },
4018 { "vcmpsd", { XMScalar
, VexScalar
, EXxmm_mq
, CMP
}, 0 },
4021 /* PREFIX_VEX_0FD0 */
4025 { "vaddsubpd", { XM
, Vex
, EXx
}, 0 },
4026 { "vaddsubps", { XM
, Vex
, EXx
}, 0 },
4029 /* PREFIX_VEX_0FE6 */
4032 { "vcvtdq2pd", { XM
, EXxmmq
}, 0 },
4033 { "vcvttpd2dq%XY", { XMM
, EXx
}, 0 },
4034 { "vcvtpd2dq%XY", { XMM
, EXx
}, 0 },
4037 /* PREFIX_VEX_0FF0 */
4042 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3
) },
4045 /* PREFIX_VEX_0F3849_X86_64 */
4047 { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_0
) },
4049 { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_2
) },
4050 { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_3
) },
4053 /* PREFIX_VEX_0F384B_X86_64 */
4056 { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_1
) },
4057 { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_2
) },
4058 { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_3
) },
4061 /* PREFIX_VEX_0F385C_X86_64 */
4064 { VEX_W_TABLE (VEX_W_0F385C_X86_64_P_1
) },
4068 /* PREFIX_VEX_0F385E_X86_64 */
4070 { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_0
) },
4071 { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_1
) },
4072 { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_2
) },
4073 { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_3
) },
4076 /* PREFIX_VEX_0F38F5_L_0 */
4078 { "bzhiS", { Gdq
, Edq
, VexGdq
}, 0 },
4079 { "pextS", { Gdq
, VexGdq
, Edq
}, 0 },
4081 { "pdepS", { Gdq
, VexGdq
, Edq
}, 0 },
4084 /* PREFIX_VEX_0F38F6_L_0 */
4089 { "mulxS", { Gdq
, VexGdq
, Edq
}, 0 },
4092 /* PREFIX_VEX_0F38F7_L_0 */
4094 { "bextrS", { Gdq
, Edq
, VexGdq
}, 0 },
4095 { "sarxS", { Gdq
, Edq
, VexGdq
}, 0 },
4096 { "shlxS", { Gdq
, Edq
, VexGdq
}, 0 },
4097 { "shrxS", { Gdq
, Edq
, VexGdq
}, 0 },
4100 /* PREFIX_VEX_0F3AF0_L_0 */
4105 { "rorxS", { Gdq
, Edq
, Ib
}, 0 },
4108 #include "i386-dis-evex-prefix.h"
4111 static const struct dis386 x86_64_table
[][2] = {
4114 { "pushP", { es
}, 0 },
4119 { "popP", { es
}, 0 },
4124 { "pushP", { cs
}, 0 },
4129 { "pushP", { ss
}, 0 },
4134 { "popP", { ss
}, 0 },
4139 { "pushP", { ds
}, 0 },
4144 { "popP", { ds
}, 0 },
4149 { "daa", { XX
}, 0 },
4154 { "das", { XX
}, 0 },
4159 { "aaa", { XX
}, 0 },
4164 { "aas", { XX
}, 0 },
4169 { "pushaP", { XX
}, 0 },
4174 { "popaP", { XX
}, 0 },
4179 { MOD_TABLE (MOD_62_32BIT
) },
4180 { EVEX_TABLE (EVEX_0F
) },
4185 { "arpl", { Ew
, Gw
}, 0 },
4186 { "movs", { { OP_G
, movsxd_mode
}, { MOVSXD_Fixup
, movsxd_mode
} }, 0 },
4191 { "ins{R|}", { Yzr
, indirDX
}, 0 },
4192 { "ins{G|}", { Yzr
, indirDX
}, 0 },
4197 { "outs{R|}", { indirDXr
, Xz
}, 0 },
4198 { "outs{G|}", { indirDXr
, Xz
}, 0 },
4203 /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */
4204 { REG_TABLE (REG_80
) },
4209 { "{l|}call{P|}", { Ap
}, 0 },
4214 { "retP", { Iw
, BND
}, 0 },
4215 { "ret@", { Iw
, BND
}, 0 },
4220 { "retP", { BND
}, 0 },
4221 { "ret@", { BND
}, 0 },
4226 { MOD_TABLE (MOD_C4_32BIT
) },
4227 { VEX_C4_TABLE (VEX_0F
) },
4232 { MOD_TABLE (MOD_C5_32BIT
) },
4233 { VEX_C5_TABLE (VEX_0F
) },
4238 { "into", { XX
}, 0 },
4243 { "aam", { Ib
}, 0 },
4248 { "aad", { Ib
}, 0 },
4253 { "callP", { Jv
, BND
}, 0 },
4254 { "call@", { Jv
, BND
}, 0 }
4259 { "jmpP", { Jv
, BND
}, 0 },
4260 { "jmp@", { Jv
, BND
}, 0 }
4265 { "{l|}jmp{P|}", { Ap
}, 0 },
4268 /* X86_64_0F01_REG_0 */
4270 { "sgdt{Q|Q}", { M
}, 0 },
4271 { "sgdt", { M
}, 0 },
4274 /* X86_64_0F01_REG_1 */
4276 { "sidt{Q|Q}", { M
}, 0 },
4277 { "sidt", { M
}, 0 },
4280 /* X86_64_0F01_REG_1_RM_5_PREFIX_2 */
4283 { "seamret", { Skip_MODRM
}, 0 },
4286 /* X86_64_0F01_REG_1_RM_6_PREFIX_2 */
4289 { "seamops", { Skip_MODRM
}, 0 },
4292 /* X86_64_0F01_REG_1_RM_7_PREFIX_2 */
4295 { "seamcall", { Skip_MODRM
}, 0 },
4298 /* X86_64_0F01_REG_2 */
4300 { "lgdt{Q|Q}", { M
}, 0 },
4301 { "lgdt", { M
}, 0 },
4304 /* X86_64_0F01_REG_3 */
4306 { "lidt{Q|Q}", { M
}, 0 },
4307 { "lidt", { M
}, 0 },
4310 /* X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1 */
4313 { "uiret", { Skip_MODRM
}, 0 },
4316 /* X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1 */
4319 { "testui", { Skip_MODRM
}, 0 },
4322 /* X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1 */
4325 { "clui", { Skip_MODRM
}, 0 },
4328 /* X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1 */
4331 { "stui", { Skip_MODRM
}, 0 },
4334 /* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1 */
4337 { "rmpadjust", { Skip_MODRM
}, 0 },
4340 /* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3 */
4343 { "rmpupdate", { Skip_MODRM
}, 0 },
4346 /* X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1 */
4349 { "psmash", { Skip_MODRM
}, 0 },
4354 { "movZ", { Em
, Td
}, 0 },
4359 { "movZ", { Td
, Em
}, 0 },
4362 /* X86_64_0FC7_REG_6_MOD_3_PREFIX_1 */
4365 { "senduipi", { Eq
}, 0 },
4368 /* X86_64_VEX_0F3849 */
4371 { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64
) },
4374 /* X86_64_VEX_0F384B */
4377 { PREFIX_TABLE (PREFIX_VEX_0F384B_X86_64
) },
4380 /* X86_64_VEX_0F385C */
4383 { PREFIX_TABLE (PREFIX_VEX_0F385C_X86_64
) },
4386 /* X86_64_VEX_0F385E */
4389 { PREFIX_TABLE (PREFIX_VEX_0F385E_X86_64
) },
4393 static const struct dis386 three_byte_table
[][256] = {
4395 /* THREE_BYTE_0F38 */
4398 { "pshufb", { MX
, EM
}, PREFIX_OPCODE
},
4399 { "phaddw", { MX
, EM
}, PREFIX_OPCODE
},
4400 { "phaddd", { MX
, EM
}, PREFIX_OPCODE
},
4401 { "phaddsw", { MX
, EM
}, PREFIX_OPCODE
},
4402 { "pmaddubsw", { MX
, EM
}, PREFIX_OPCODE
},
4403 { "phsubw", { MX
, EM
}, PREFIX_OPCODE
},
4404 { "phsubd", { MX
, EM
}, PREFIX_OPCODE
},
4405 { "phsubsw", { MX
, EM
}, PREFIX_OPCODE
},
4407 { "psignb", { MX
, EM
}, PREFIX_OPCODE
},
4408 { "psignw", { MX
, EM
}, PREFIX_OPCODE
},
4409 { "psignd", { MX
, EM
}, PREFIX_OPCODE
},
4410 { "pmulhrsw", { MX
, EM
}, PREFIX_OPCODE
},
4416 { "pblendvb", { XM
, EXx
, XMM0
}, PREFIX_DATA
},
4420 { "blendvps", { XM
, EXx
, XMM0
}, PREFIX_DATA
},
4421 { "blendvpd", { XM
, EXx
, XMM0
}, PREFIX_DATA
},
4423 { "ptest", { XM
, EXx
}, PREFIX_DATA
},
4429 { "pabsb", { MX
, EM
}, PREFIX_OPCODE
},
4430 { "pabsw", { MX
, EM
}, PREFIX_OPCODE
},
4431 { "pabsd", { MX
, EM
}, PREFIX_OPCODE
},
4434 { "pmovsxbw", { XM
, EXq
}, PREFIX_DATA
},
4435 { "pmovsxbd", { XM
, EXd
}, PREFIX_DATA
},
4436 { "pmovsxbq", { XM
, EXw
}, PREFIX_DATA
},
4437 { "pmovsxwd", { XM
, EXq
}, PREFIX_DATA
},
4438 { "pmovsxwq", { XM
, EXd
}, PREFIX_DATA
},
4439 { "pmovsxdq", { XM
, EXq
}, PREFIX_DATA
},
4443 { "pmuldq", { XM
, EXx
}, PREFIX_DATA
},
4444 { "pcmpeqq", { XM
, EXx
}, PREFIX_DATA
},
4445 { MOD_TABLE (MOD_0F382A
) },
4446 { "packusdw", { XM
, EXx
}, PREFIX_DATA
},
4452 { "pmovzxbw", { XM
, EXq
}, PREFIX_DATA
},
4453 { "pmovzxbd", { XM
, EXd
}, PREFIX_DATA
},
4454 { "pmovzxbq", { XM
, EXw
}, PREFIX_DATA
},
4455 { "pmovzxwd", { XM
, EXq
}, PREFIX_DATA
},
4456 { "pmovzxwq", { XM
, EXd
}, PREFIX_DATA
},
4457 { "pmovzxdq", { XM
, EXq
}, PREFIX_DATA
},
4459 { "pcmpgtq", { XM
, EXx
}, PREFIX_DATA
},
4461 { "pminsb", { XM
, EXx
}, PREFIX_DATA
},
4462 { "pminsd", { XM
, EXx
}, PREFIX_DATA
},
4463 { "pminuw", { XM
, EXx
}, PREFIX_DATA
},
4464 { "pminud", { XM
, EXx
}, PREFIX_DATA
},
4465 { "pmaxsb", { XM
, EXx
}, PREFIX_DATA
},
4466 { "pmaxsd", { XM
, EXx
}, PREFIX_DATA
},
4467 { "pmaxuw", { XM
, EXx
}, PREFIX_DATA
},
4468 { "pmaxud", { XM
, EXx
}, PREFIX_DATA
},
4470 { "pmulld", { XM
, EXx
}, PREFIX_DATA
},
4471 { "phminposuw", { XM
, EXx
}, PREFIX_DATA
},
4542 { "invept", { Gm
, Mo
}, PREFIX_DATA
},
4543 { "invvpid", { Gm
, Mo
}, PREFIX_DATA
},
4544 { "invpcid", { Gm
, M
}, PREFIX_DATA
},
4623 { "sha1nexte", { XM
, EXxmm
}, PREFIX_OPCODE
},
4624 { "sha1msg1", { XM
, EXxmm
}, PREFIX_OPCODE
},
4625 { "sha1msg2", { XM
, EXxmm
}, PREFIX_OPCODE
},
4626 { "sha256rnds2", { XM
, EXxmm
, XMM0
}, PREFIX_OPCODE
},
4627 { "sha256msg1", { XM
, EXxmm
}, PREFIX_OPCODE
},
4628 { "sha256msg2", { XM
, EXxmm
}, PREFIX_OPCODE
},
4630 { "gf2p8mulb", { XM
, EXxmm
}, PREFIX_DATA
},
4641 { PREFIX_TABLE (PREFIX_0F38D8
) },
4644 { "aesimc", { XM
, EXx
}, PREFIX_DATA
},
4645 { PREFIX_TABLE (PREFIX_0F38DC
) },
4646 { PREFIX_TABLE (PREFIX_0F38DD
) },
4647 { PREFIX_TABLE (PREFIX_0F38DE
) },
4648 { PREFIX_TABLE (PREFIX_0F38DF
) },
4668 { PREFIX_TABLE (PREFIX_0F38F0
) },
4669 { PREFIX_TABLE (PREFIX_0F38F1
) },
4673 { MOD_TABLE (MOD_0F38F5
) },
4674 { PREFIX_TABLE (PREFIX_0F38F6
) },
4677 { PREFIX_TABLE (PREFIX_0F38F8
) },
4678 { MOD_TABLE (MOD_0F38F9
) },
4679 { PREFIX_TABLE (PREFIX_0F38FA
) },
4680 { PREFIX_TABLE (PREFIX_0F38FB
) },
4686 /* THREE_BYTE_0F3A */
4698 { "roundps", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4699 { "roundpd", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4700 { "roundss", { XM
, EXd
, Ib
}, PREFIX_DATA
},
4701 { "roundsd", { XM
, EXq
, Ib
}, PREFIX_DATA
},
4702 { "blendps", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4703 { "blendpd", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4704 { "pblendw", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4705 { "palignr", { MX
, EM
, Ib
}, PREFIX_OPCODE
},
4711 { "pextrb", { Edqb
, XM
, Ib
}, PREFIX_DATA
},
4712 { "pextrw", { Edqw
, XM
, Ib
}, PREFIX_DATA
},
4713 { "pextrK", { Edq
, XM
, Ib
}, PREFIX_DATA
},
4714 { "extractps", { Edqd
, XM
, Ib
}, PREFIX_DATA
},
4725 { "pinsrb", { XM
, Edqb
, Ib
}, PREFIX_DATA
},
4726 { "insertps", { XM
, EXd
, Ib
}, PREFIX_DATA
},
4727 { "pinsrK", { XM
, Edq
, Ib
}, PREFIX_DATA
},
4761 { "dpps", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4762 { "dppd", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4763 { "mpsadbw", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4765 { "pclmulqdq", { XM
, EXx
, PCLMUL
}, PREFIX_DATA
},
4797 { "pcmpestrm!%LQ", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4798 { "pcmpestri!%LQ", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4799 { "pcmpistrm", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4800 { "pcmpistri", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4918 { "sha1rnds4", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4920 { "gf2p8affineqb", { XM
, EXxmm
, Ib
}, PREFIX_DATA
},
4921 { "gf2p8affineinvqb", { XM
, EXxmm
, Ib
}, PREFIX_DATA
},
4939 { "aeskeygenassist", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4959 { PREFIX_TABLE (PREFIX_0F3A0F
) },
4979 static const struct dis386 xop_table
[][256] = {
5132 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_85
) },
5133 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_86
) },
5134 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_87
) },
5142 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8E
) },
5143 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8F
) },
5150 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_95
) },
5151 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_96
) },
5152 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_97
) },
5160 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9E
) },
5161 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9F
) },
5165 { "vpcmov", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
5166 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A3
) },
5169 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A6
) },
5187 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_B6
) },
5199 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C0
) },
5200 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C1
) },
5201 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C2
) },
5202 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C3
) },
5212 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC
) },
5213 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD
) },
5214 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE
) },
5215 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF
) },
5248 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC
) },
5249 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED
) },
5250 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE
) },
5251 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF
) },
5275 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_01
) },
5276 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_02
) },
5294 { MOD_TABLE (MOD_XOP_09_12
) },
5418 { VEX_W_TABLE (VEX_W_0FXOP_09_80
) },
5419 { VEX_W_TABLE (VEX_W_0FXOP_09_81
) },
5420 { VEX_W_TABLE (VEX_W_0FXOP_09_82
) },
5421 { VEX_W_TABLE (VEX_W_0FXOP_09_83
) },
5436 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_90
) },
5437 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_91
) },
5438 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_92
) },
5439 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_93
) },
5440 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_94
) },
5441 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_95
) },
5442 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_96
) },
5443 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_97
) },
5445 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_98
) },
5446 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_99
) },
5447 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9A
) },
5448 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9B
) },
5491 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C1
) },
5492 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C2
) },
5493 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C3
) },
5496 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C6
) },
5497 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C7
) },
5502 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_CB
) },
5509 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D1
) },
5510 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D2
) },
5511 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D3
) },
5514 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D6
) },
5515 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D7
) },
5520 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_DB
) },
5527 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E1
) },
5528 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E2
) },
5529 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E3
) },
5583 { "bextrS", { Gdq
, Edq
, Id
}, 0 },
5585 { VEX_LEN_TABLE (VEX_LEN_0FXOP_0A_12
) },
5855 static const struct dis386 vex_table
[][256] = {
5877 { PREFIX_TABLE (PREFIX_VEX_0F10
) },
5878 { PREFIX_TABLE (PREFIX_VEX_0F11
) },
5879 { PREFIX_TABLE (PREFIX_VEX_0F12
) },
5880 { MOD_TABLE (MOD_VEX_0F13
) },
5881 { "vunpcklpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
5882 { "vunpckhpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
5883 { PREFIX_TABLE (PREFIX_VEX_0F16
) },
5884 { MOD_TABLE (MOD_VEX_0F17
) },
5904 { "vmovapX", { XM
, EXx
}, PREFIX_OPCODE
},
5905 { "vmovapX", { EXxS
, XM
}, PREFIX_OPCODE
},
5906 { PREFIX_TABLE (PREFIX_VEX_0F2A
) },
5907 { MOD_TABLE (MOD_VEX_0F2B
) },
5908 { PREFIX_TABLE (PREFIX_VEX_0F2C
) },
5909 { PREFIX_TABLE (PREFIX_VEX_0F2D
) },
5910 { PREFIX_TABLE (PREFIX_VEX_0F2E
) },
5911 { PREFIX_TABLE (PREFIX_VEX_0F2F
) },
5932 { VEX_LEN_TABLE (VEX_LEN_0F41
) },
5933 { VEX_LEN_TABLE (VEX_LEN_0F42
) },
5935 { VEX_LEN_TABLE (VEX_LEN_0F44
) },
5936 { VEX_LEN_TABLE (VEX_LEN_0F45
) },
5937 { VEX_LEN_TABLE (VEX_LEN_0F46
) },
5938 { VEX_LEN_TABLE (VEX_LEN_0F47
) },
5942 { VEX_LEN_TABLE (VEX_LEN_0F4A
) },
5943 { VEX_LEN_TABLE (VEX_LEN_0F4B
) },
5949 { MOD_TABLE (MOD_VEX_0F50
) },
5950 { PREFIX_TABLE (PREFIX_VEX_0F51
) },
5951 { PREFIX_TABLE (PREFIX_VEX_0F52
) },
5952 { PREFIX_TABLE (PREFIX_VEX_0F53
) },
5953 { "vandpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
5954 { "vandnpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
5955 { "vorpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
5956 { "vxorpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
5958 { PREFIX_TABLE (PREFIX_VEX_0F58
) },
5959 { PREFIX_TABLE (PREFIX_VEX_0F59
) },
5960 { PREFIX_TABLE (PREFIX_VEX_0F5A
) },
5961 { PREFIX_TABLE (PREFIX_VEX_0F5B
) },
5962 { PREFIX_TABLE (PREFIX_VEX_0F5C
) },
5963 { PREFIX_TABLE (PREFIX_VEX_0F5D
) },
5964 { PREFIX_TABLE (PREFIX_VEX_0F5E
) },
5965 { PREFIX_TABLE (PREFIX_VEX_0F5F
) },
5967 { "vpunpcklbw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5968 { "vpunpcklwd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5969 { "vpunpckldq", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5970 { "vpacksswb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5971 { "vpcmpgtb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5972 { "vpcmpgtw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5973 { "vpcmpgtd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5974 { "vpackuswb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5976 { "vpunpckhbw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5977 { "vpunpckhwd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5978 { "vpunpckhdq", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5979 { "vpackssdw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5980 { "vpunpcklqdq", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5981 { "vpunpckhqdq", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5982 { VEX_LEN_TABLE (VEX_LEN_0F6E
) },
5983 { PREFIX_TABLE (PREFIX_VEX_0F6F
) },
5985 { PREFIX_TABLE (PREFIX_VEX_0F70
) },
5986 { MOD_TABLE (MOD_VEX_0F71
) },
5987 { MOD_TABLE (MOD_VEX_0F72
) },
5988 { MOD_TABLE (MOD_VEX_0F73
) },
5989 { "vpcmpeqb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5990 { "vpcmpeqw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5991 { "vpcmpeqd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
5992 { VEX_LEN_TABLE (VEX_LEN_0F77
) },
5998 { PREFIX_TABLE (PREFIX_VEX_0F7C
) },
5999 { PREFIX_TABLE (PREFIX_VEX_0F7D
) },
6000 { PREFIX_TABLE (PREFIX_VEX_0F7E
) },
6001 { PREFIX_TABLE (PREFIX_VEX_0F7F
) },
6021 { VEX_LEN_TABLE (VEX_LEN_0F90
) },
6022 { VEX_LEN_TABLE (VEX_LEN_0F91
) },
6023 { VEX_LEN_TABLE (VEX_LEN_0F92
) },
6024 { VEX_LEN_TABLE (VEX_LEN_0F93
) },
6030 { VEX_LEN_TABLE (VEX_LEN_0F98
) },
6031 { VEX_LEN_TABLE (VEX_LEN_0F99
) },
6054 { REG_TABLE (REG_VEX_0FAE
) },
6077 { PREFIX_TABLE (PREFIX_VEX_0FC2
) },
6079 { VEX_LEN_TABLE (VEX_LEN_0FC4
) },
6080 { VEX_LEN_TABLE (VEX_LEN_0FC5
) },
6081 { "vshufpX", { XM
, Vex
, EXx
, Ib
}, PREFIX_OPCODE
},
6093 { PREFIX_TABLE (PREFIX_VEX_0FD0
) },
6094 { "vpsrlw", { XM
, Vex
, EXxmm
}, PREFIX_DATA
},
6095 { "vpsrld", { XM
, Vex
, EXxmm
}, PREFIX_DATA
},
6096 { "vpsrlq", { XM
, Vex
, EXxmm
}, PREFIX_DATA
},
6097 { "vpaddq", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6098 { "vpmullw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6099 { VEX_LEN_TABLE (VEX_LEN_0FD6
) },
6100 { MOD_TABLE (MOD_VEX_0FD7
) },
6102 { "vpsubusb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6103 { "vpsubusw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6104 { "vpminub", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6105 { "vpand", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6106 { "vpaddusb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6107 { "vpaddusw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6108 { "vpmaxub", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6109 { "vpandn", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6111 { "vpavgb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6112 { "vpsraw", { XM
, Vex
, EXxmm
}, PREFIX_DATA
},
6113 { "vpsrad", { XM
, Vex
, EXxmm
}, PREFIX_DATA
},
6114 { "vpavgw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6115 { "vpmulhuw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6116 { "vpmulhw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6117 { PREFIX_TABLE (PREFIX_VEX_0FE6
) },
6118 { MOD_TABLE (MOD_VEX_0FE7
) },
6120 { "vpsubsb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6121 { "vpsubsw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6122 { "vpminsw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6123 { "vpor", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6124 { "vpaddsb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6125 { "vpaddsw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6126 { "vpmaxsw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6127 { "vpxor", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6129 { PREFIX_TABLE (PREFIX_VEX_0FF0
) },
6130 { "vpsllw", { XM
, Vex
, EXxmm
}, PREFIX_DATA
},
6131 { "vpslld", { XM
, Vex
, EXxmm
}, PREFIX_DATA
},
6132 { "vpsllq", { XM
, Vex
, EXxmm
}, PREFIX_DATA
},
6133 { "vpmuludq", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6134 { "vpmaddwd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6135 { "vpsadbw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6136 { VEX_LEN_TABLE (VEX_LEN_0FF7
) },
6138 { "vpsubb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6139 { "vpsubw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6140 { "vpsubd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6141 { "vpsubq", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6142 { "vpaddb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6143 { "vpaddw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6144 { "vpaddd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6150 { "vpshufb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6151 { "vphaddw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6152 { "vphaddd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6153 { "vphaddsw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6154 { "vpmaddubsw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6155 { "vphsubw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6156 { "vphsubd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6157 { "vphsubsw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6159 { "vpsignb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6160 { "vpsignw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6161 { "vpsignd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6162 { "vpmulhrsw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6163 { VEX_W_TABLE (VEX_W_0F380C
) },
6164 { VEX_W_TABLE (VEX_W_0F380D
) },
6165 { VEX_W_TABLE (VEX_W_0F380E
) },
6166 { VEX_W_TABLE (VEX_W_0F380F
) },
6171 { VEX_W_TABLE (VEX_W_0F3813
) },
6174 { VEX_LEN_TABLE (VEX_LEN_0F3816
) },
6175 { "vptest", { XM
, EXx
}, PREFIX_DATA
},
6177 { VEX_W_TABLE (VEX_W_0F3818
) },
6178 { VEX_LEN_TABLE (VEX_LEN_0F3819
) },
6179 { MOD_TABLE (MOD_VEX_0F381A
) },
6181 { "vpabsb", { XM
, EXx
}, PREFIX_DATA
},
6182 { "vpabsw", { XM
, EXx
}, PREFIX_DATA
},
6183 { "vpabsd", { XM
, EXx
}, PREFIX_DATA
},
6186 { "vpmovsxbw", { XM
, EXxmmq
}, PREFIX_DATA
},
6187 { "vpmovsxbd", { XM
, EXxmmqd
}, PREFIX_DATA
},
6188 { "vpmovsxbq", { XM
, EXxmmdw
}, PREFIX_DATA
},
6189 { "vpmovsxwd", { XM
, EXxmmq
}, PREFIX_DATA
},
6190 { "vpmovsxwq", { XM
, EXxmmqd
}, PREFIX_DATA
},
6191 { "vpmovsxdq", { XM
, EXxmmq
}, PREFIX_DATA
},
6195 { "vpmuldq", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6196 { "vpcmpeqq", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6197 { MOD_TABLE (MOD_VEX_0F382A
) },
6198 { "vpackusdw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6199 { MOD_TABLE (MOD_VEX_0F382C
) },
6200 { MOD_TABLE (MOD_VEX_0F382D
) },
6201 { MOD_TABLE (MOD_VEX_0F382E
) },
6202 { MOD_TABLE (MOD_VEX_0F382F
) },
6204 { "vpmovzxbw", { XM
, EXxmmq
}, PREFIX_DATA
},
6205 { "vpmovzxbd", { XM
, EXxmmqd
}, PREFIX_DATA
},
6206 { "vpmovzxbq", { XM
, EXxmmdw
}, PREFIX_DATA
},
6207 { "vpmovzxwd", { XM
, EXxmmq
}, PREFIX_DATA
},
6208 { "vpmovzxwq", { XM
, EXxmmqd
}, PREFIX_DATA
},
6209 { "vpmovzxdq", { XM
, EXxmmq
}, PREFIX_DATA
},
6210 { VEX_LEN_TABLE (VEX_LEN_0F3836
) },
6211 { "vpcmpgtq", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6213 { "vpminsb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6214 { "vpminsd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6215 { "vpminuw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6216 { "vpminud", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6217 { "vpmaxsb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6218 { "vpmaxsd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6219 { "vpmaxuw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6220 { "vpmaxud", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6222 { "vpmulld", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6223 { VEX_LEN_TABLE (VEX_LEN_0F3841
) },
6227 { "vpsrlv%DQ", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6228 { VEX_W_TABLE (VEX_W_0F3846
) },
6229 { "vpsllv%DQ", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6232 { X86_64_TABLE (X86_64_VEX_0F3849
) },
6234 { X86_64_TABLE (X86_64_VEX_0F384B
) },
6240 { VEX_W_TABLE (VEX_W_0F3850
) },
6241 { VEX_W_TABLE (VEX_W_0F3851
) },
6242 { VEX_W_TABLE (VEX_W_0F3852
) },
6243 { VEX_W_TABLE (VEX_W_0F3853
) },
6249 { VEX_W_TABLE (VEX_W_0F3858
) },
6250 { VEX_W_TABLE (VEX_W_0F3859
) },
6251 { MOD_TABLE (MOD_VEX_0F385A
) },
6253 { X86_64_TABLE (X86_64_VEX_0F385C
) },
6255 { X86_64_TABLE (X86_64_VEX_0F385E
) },
6285 { VEX_W_TABLE (VEX_W_0F3878
) },
6286 { VEX_W_TABLE (VEX_W_0F3879
) },
6307 { MOD_TABLE (MOD_VEX_0F388C
) },
6309 { MOD_TABLE (MOD_VEX_0F388E
) },
6312 { "vpgatherd%DQ", { XM
, MVexVSIBDWpX
, Vex
}, PREFIX_DATA
},
6313 { "vpgatherq%DQ", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
}, PREFIX_DATA
},
6314 { "vgatherdp%XW", { XM
, MVexVSIBDWpX
, Vex
}, PREFIX_DATA
},
6315 { "vgatherqp%XW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
}, PREFIX_DATA
},
6318 { "vfmaddsub132p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6319 { "vfmsubadd132p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6321 { "vfmadd132p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6322 { "vfmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, PREFIX_DATA
},
6323 { "vfmsub132p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6324 { "vfmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, PREFIX_DATA
},
6325 { "vfnmadd132p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6326 { "vfnmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, PREFIX_DATA
},
6327 { "vfnmsub132p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6328 { "vfnmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, PREFIX_DATA
},
6336 { "vfmaddsub213p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6337 { "vfmsubadd213p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6339 { "vfmadd213p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6340 { "vfmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, PREFIX_DATA
},
6341 { "vfmsub213p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6342 { "vfmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, PREFIX_DATA
},
6343 { "vfnmadd213p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6344 { "vfnmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, PREFIX_DATA
},
6345 { "vfnmsub213p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6346 { "vfnmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, PREFIX_DATA
},
6354 { "vfmaddsub231p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6355 { "vfmsubadd231p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6357 { "vfmadd231p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6358 { "vfmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, PREFIX_DATA
},
6359 { "vfmsub231p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6360 { "vfmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, PREFIX_DATA
},
6361 { "vfnmadd231p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6362 { "vfnmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, PREFIX_DATA
},
6363 { "vfnmsub231p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6364 { "vfnmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, PREFIX_DATA
},
6382 { VEX_W_TABLE (VEX_W_0F38CF
) },
6396 { VEX_LEN_TABLE (VEX_LEN_0F38DB
) },
6397 { "vaesenc", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6398 { "vaesenclast", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6399 { "vaesdec", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6400 { "vaesdeclast", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6422 { VEX_LEN_TABLE (VEX_LEN_0F38F2
) },
6423 { VEX_LEN_TABLE (VEX_LEN_0F38F3
) },
6425 { VEX_LEN_TABLE (VEX_LEN_0F38F5
) },
6426 { VEX_LEN_TABLE (VEX_LEN_0F38F6
) },
6427 { VEX_LEN_TABLE (VEX_LEN_0F38F7
) },
6441 { VEX_LEN_TABLE (VEX_LEN_0F3A00
) },
6442 { VEX_LEN_TABLE (VEX_LEN_0F3A01
) },
6443 { VEX_W_TABLE (VEX_W_0F3A02
) },
6445 { VEX_W_TABLE (VEX_W_0F3A04
) },
6446 { VEX_W_TABLE (VEX_W_0F3A05
) },
6447 { VEX_LEN_TABLE (VEX_LEN_0F3A06
) },
6450 { "vroundps", { XM
, EXx
, Ib
}, PREFIX_DATA
},
6451 { "vroundpd", { XM
, EXx
, Ib
}, PREFIX_DATA
},
6452 { "vroundss", { XMScalar
, VexScalar
, EXxmm_md
, Ib
}, PREFIX_DATA
},
6453 { "vroundsd", { XMScalar
, VexScalar
, EXxmm_mq
, Ib
}, PREFIX_DATA
},
6454 { "vblendps", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
6455 { "vblendpd", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
6456 { "vpblendw", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
6457 { "vpalignr", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
6463 { VEX_LEN_TABLE (VEX_LEN_0F3A14
) },
6464 { VEX_LEN_TABLE (VEX_LEN_0F3A15
) },
6465 { VEX_LEN_TABLE (VEX_LEN_0F3A16
) },
6466 { VEX_LEN_TABLE (VEX_LEN_0F3A17
) },
6468 { VEX_LEN_TABLE (VEX_LEN_0F3A18
) },
6469 { VEX_LEN_TABLE (VEX_LEN_0F3A19
) },
6473 { VEX_W_TABLE (VEX_W_0F3A1D
) },
6477 { VEX_LEN_TABLE (VEX_LEN_0F3A20
) },
6478 { VEX_LEN_TABLE (VEX_LEN_0F3A21
) },
6479 { VEX_LEN_TABLE (VEX_LEN_0F3A22
) },
6495 { VEX_LEN_TABLE (VEX_LEN_0F3A30
) },
6496 { VEX_LEN_TABLE (VEX_LEN_0F3A31
) },
6497 { VEX_LEN_TABLE (VEX_LEN_0F3A32
) },
6498 { VEX_LEN_TABLE (VEX_LEN_0F3A33
) },
6504 { VEX_LEN_TABLE (VEX_LEN_0F3A38
) },
6505 { VEX_LEN_TABLE (VEX_LEN_0F3A39
) },
6513 { "vdpps", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
6514 { VEX_LEN_TABLE (VEX_LEN_0F3A41
) },
6515 { "vmpsadbw", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
6517 { "vpclmulqdq", { XM
, Vex
, EXx
, PCLMUL
}, PREFIX_DATA
},
6519 { VEX_LEN_TABLE (VEX_LEN_0F3A46
) },
6522 { "vpermil2ps", { XM
, Vex
, EXx
, XMVexI4
, VexI4
}, PREFIX_DATA
},
6523 { "vpermil2pd", { XM
, Vex
, EXx
, XMVexI4
, VexI4
}, PREFIX_DATA
},
6524 { VEX_W_TABLE (VEX_W_0F3A4A
) },
6525 { VEX_W_TABLE (VEX_W_0F3A4B
) },
6526 { VEX_W_TABLE (VEX_W_0F3A4C
) },
6544 { "vfmaddsubps", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6545 { "vfmaddsubpd", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6546 { "vfmsubaddps", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6547 { "vfmsubaddpd", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6549 { VEX_LEN_TABLE (VEX_LEN_0F3A60
) },
6550 { VEX_LEN_TABLE (VEX_LEN_0F3A61
) },
6551 { VEX_LEN_TABLE (VEX_LEN_0F3A62
) },
6552 { VEX_LEN_TABLE (VEX_LEN_0F3A63
) },
6558 { "vfmaddps", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6559 { "vfmaddpd", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6560 { "vfmaddss", { XMScalar
, VexScalar
, EXxmm_md
, XMVexScalarI4
}, PREFIX_DATA
},
6561 { "vfmaddsd", { XMScalar
, VexScalar
, EXxmm_mq
, XMVexScalarI4
}, PREFIX_DATA
},
6562 { "vfmsubps", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6563 { "vfmsubpd", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6564 { "vfmsubss", { XMScalar
, VexScalar
, EXxmm_md
, XMVexScalarI4
}, PREFIX_DATA
},
6565 { "vfmsubsd", { XMScalar
, VexScalar
, EXxmm_mq
, XMVexScalarI4
}, PREFIX_DATA
},
6576 { "vfnmaddps", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6577 { "vfnmaddpd", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6578 { "vfnmaddss", { XMScalar
, VexScalar
, EXxmm_md
, XMVexScalarI4
}, PREFIX_DATA
},
6579 { "vfnmaddsd", { XMScalar
, VexScalar
, EXxmm_mq
, XMVexScalarI4
}, PREFIX_DATA
},
6580 { "vfnmsubps", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6581 { "vfnmsubpd", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6582 { "vfnmsubss", { XMScalar
, VexScalar
, EXxmm_md
, XMVexScalarI4
}, PREFIX_DATA
},
6583 { "vfnmsubsd", { XMScalar
, VexScalar
, EXxmm_mq
, XMVexScalarI4
}, PREFIX_DATA
},
6672 { VEX_W_TABLE (VEX_W_0F3ACE
) },
6673 { VEX_W_TABLE (VEX_W_0F3ACF
) },
6691 { VEX_LEN_TABLE (VEX_LEN_0F3ADF
) },
6711 { VEX_LEN_TABLE (VEX_LEN_0F3AF0
) },
6731 #include "i386-dis-evex.h"
6733 static const struct dis386 vex_len_table
[][2] = {
6734 /* VEX_LEN_0F12_P_0_M_0 / VEX_LEN_0F12_P_2_M_0 */
6736 { "vmovlpX", { XM
, Vex
, EXq
}, 0 },
6739 /* VEX_LEN_0F12_P_0_M_1 */
6741 { "vmovhlps", { XM
, Vex
, EXq
}, 0 },
6744 /* VEX_LEN_0F13_M_0 */
6746 { "vmovlpX", { EXq
, XM
}, PREFIX_OPCODE
},
6749 /* VEX_LEN_0F16_P_0_M_0 / VEX_LEN_0F16_P_2_M_0 */
6751 { "vmovhpX", { XM
, Vex
, EXq
}, 0 },
6754 /* VEX_LEN_0F16_P_0_M_1 */
6756 { "vmovlhps", { XM
, Vex
, EXq
}, 0 },
6759 /* VEX_LEN_0F17_M_0 */
6761 { "vmovhpX", { EXq
, XM
}, PREFIX_OPCODE
},
6767 { MOD_TABLE (MOD_VEX_0F41_L_1
) },
6773 { MOD_TABLE (MOD_VEX_0F42_L_1
) },
6778 { MOD_TABLE (MOD_VEX_0F44_L_0
) },
6784 { MOD_TABLE (MOD_VEX_0F45_L_1
) },
6790 { MOD_TABLE (MOD_VEX_0F46_L_1
) },
6796 { MOD_TABLE (MOD_VEX_0F47_L_1
) },
6802 { MOD_TABLE (MOD_VEX_0F4A_L_1
) },
6808 { MOD_TABLE (MOD_VEX_0F4B_L_1
) },
6813 { "vmovK", { XMScalar
, Edq
}, PREFIX_DATA
},
6818 { "vzeroupper", { XX
}, 0 },
6819 { "vzeroall", { XX
}, 0 },
6822 /* VEX_LEN_0F7E_P_1 */
6824 { "vmovq", { XMScalar
, EXxmm_mq
}, 0 },
6827 /* VEX_LEN_0F7E_P_2 */
6829 { "vmovK", { Edq
, XMScalar
}, 0 },
6834 { VEX_W_TABLE (VEX_W_0F90_L_0
) },
6839 { MOD_TABLE (MOD_VEX_0F91_L_0
) },
6844 { MOD_TABLE (MOD_VEX_0F92_L_0
) },
6849 { MOD_TABLE (MOD_VEX_0F93_L_0
) },
6854 { MOD_TABLE (MOD_VEX_0F98_L_0
) },
6859 { MOD_TABLE (MOD_VEX_0F99_L_0
) },
6862 /* VEX_LEN_0FAE_R_2_M_0 */
6864 { "vldmxcsr", { Md
}, 0 },
6867 /* VEX_LEN_0FAE_R_3_M_0 */
6869 { "vstmxcsr", { Md
}, 0 },
6874 { "vpinsrw", { XM
, Vex
, Edqw
, Ib
}, PREFIX_DATA
},
6879 { "vpextrw", { Gdq
, XS
, Ib
}, PREFIX_DATA
},
6884 { "vmovq", { EXqS
, XMScalar
}, PREFIX_DATA
},
6889 { "vmaskmovdqu", { XM
, XS
}, PREFIX_DATA
},
6892 /* VEX_LEN_0F3816 */
6895 { VEX_W_TABLE (VEX_W_0F3816_L_1
) },
6898 /* VEX_LEN_0F3819 */
6901 { VEX_W_TABLE (VEX_W_0F3819_L_1
) },
6904 /* VEX_LEN_0F381A_M_0 */
6907 { VEX_W_TABLE (VEX_W_0F381A_M_0_L_1
) },
6910 /* VEX_LEN_0F3836 */
6913 { VEX_W_TABLE (VEX_W_0F3836
) },
6916 /* VEX_LEN_0F3841 */
6918 { "vphminposuw", { XM
, EXx
}, PREFIX_DATA
},
6921 /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_0 */
6923 { "ldtilecfg", { M
}, 0 },
6926 /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0 */
6928 { "tilerelease", { Skip_MODRM
}, 0 },
6931 /* VEX_LEN_0F3849_X86_64_P_2_W_0_M_0 */
6933 { "sttilecfg", { M
}, 0 },
6936 /* VEX_LEN_0F3849_X86_64_P_3_W_0_M_0 */
6938 { "tilezero", { TMM
, Skip_MODRM
}, 0 },
6941 /* VEX_LEN_0F384B_X86_64_P_1_W_0_M_0 */
6943 { "tilestored", { MVexSIBMEM
, TMM
}, 0 },
6945 /* VEX_LEN_0F384B_X86_64_P_2_W_0_M_0 */
6947 { "tileloaddt1", { TMM
, MVexSIBMEM
}, 0 },
6950 /* VEX_LEN_0F384B_X86_64_P_3_W_0_M_0 */
6952 { "tileloadd", { TMM
, MVexSIBMEM
}, 0 },
6955 /* VEX_LEN_0F385A_M_0 */
6958 { VEX_W_TABLE (VEX_W_0F385A_M_0_L_0
) },
6961 /* VEX_LEN_0F385C_X86_64_P_1_W_0_M_0 */
6963 { "tdpbf16ps", { TMM
, EXtmm
, VexTmm
}, 0 },
6966 /* VEX_LEN_0F385E_X86_64_P_0_W_0_M_0 */
6968 { "tdpbuud", {TMM
, EXtmm
, VexTmm
}, 0 },
6971 /* VEX_LEN_0F385E_X86_64_P_1_W_0_M_0 */
6973 { "tdpbsud", {TMM
, EXtmm
, VexTmm
}, 0 },
6976 /* VEX_LEN_0F385E_X86_64_P_2_W_0_M_0 */
6978 { "tdpbusd", {TMM
, EXtmm
, VexTmm
}, 0 },
6981 /* VEX_LEN_0F385E_X86_64_P_3_W_0_M_0 */
6983 { "tdpbssd", {TMM
, EXtmm
, VexTmm
}, 0 },
6986 /* VEX_LEN_0F38DB */
6988 { "vaesimc", { XM
, EXx
}, PREFIX_DATA
},
6991 /* VEX_LEN_0F38F2 */
6993 { "andnS", { Gdq
, VexGdq
, Edq
}, PREFIX_OPCODE
},
6996 /* VEX_LEN_0F38F3 */
6998 { REG_TABLE(REG_VEX_0F38F3_L_0
) },
7001 /* VEX_LEN_0F38F5 */
7003 { PREFIX_TABLE(PREFIX_VEX_0F38F5_L_0
) },
7006 /* VEX_LEN_0F38F6 */
7008 { PREFIX_TABLE(PREFIX_VEX_0F38F6_L_0
) },
7011 /* VEX_LEN_0F38F7 */
7013 { PREFIX_TABLE(PREFIX_VEX_0F38F7_L_0
) },
7016 /* VEX_LEN_0F3A00 */
7019 { VEX_W_TABLE (VEX_W_0F3A00_L_1
) },
7022 /* VEX_LEN_0F3A01 */
7025 { VEX_W_TABLE (VEX_W_0F3A01_L_1
) },
7028 /* VEX_LEN_0F3A06 */
7031 { VEX_W_TABLE (VEX_W_0F3A06_L_1
) },
7034 /* VEX_LEN_0F3A14 */
7036 { "vpextrb", { Edqb
, XM
, Ib
}, PREFIX_DATA
},
7039 /* VEX_LEN_0F3A15 */
7041 { "vpextrw", { Edqw
, XM
, Ib
}, PREFIX_DATA
},
7044 /* VEX_LEN_0F3A16 */
7046 { "vpextrK", { Edq
, XM
, Ib
}, PREFIX_DATA
},
7049 /* VEX_LEN_0F3A17 */
7051 { "vextractps", { Edqd
, XM
, Ib
}, PREFIX_DATA
},
7054 /* VEX_LEN_0F3A18 */
7057 { VEX_W_TABLE (VEX_W_0F3A18_L_1
) },
7060 /* VEX_LEN_0F3A19 */
7063 { VEX_W_TABLE (VEX_W_0F3A19_L_1
) },
7066 /* VEX_LEN_0F3A20 */
7068 { "vpinsrb", { XM
, Vex
, Edqb
, Ib
}, PREFIX_DATA
},
7071 /* VEX_LEN_0F3A21 */
7073 { "vinsertps", { XM
, Vex
, EXd
, Ib
}, PREFIX_DATA
},
7076 /* VEX_LEN_0F3A22 */
7078 { "vpinsrK", { XM
, Vex
, Edq
, Ib
}, PREFIX_DATA
},
7081 /* VEX_LEN_0F3A30 */
7083 { MOD_TABLE (MOD_VEX_0F3A30_L_0
) },
7086 /* VEX_LEN_0F3A31 */
7088 { MOD_TABLE (MOD_VEX_0F3A31_L_0
) },
7091 /* VEX_LEN_0F3A32 */
7093 { MOD_TABLE (MOD_VEX_0F3A32_L_0
) },
7096 /* VEX_LEN_0F3A33 */
7098 { MOD_TABLE (MOD_VEX_0F3A33_L_0
) },
7101 /* VEX_LEN_0F3A38 */
7104 { VEX_W_TABLE (VEX_W_0F3A38_L_1
) },
7107 /* VEX_LEN_0F3A39 */
7110 { VEX_W_TABLE (VEX_W_0F3A39_L_1
) },
7113 /* VEX_LEN_0F3A41 */
7115 { "vdppd", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
7118 /* VEX_LEN_0F3A46 */
7121 { VEX_W_TABLE (VEX_W_0F3A46_L_1
) },
7124 /* VEX_LEN_0F3A60 */
7126 { "vpcmpestrm!%LQ", { XM
, EXx
, Ib
}, PREFIX_DATA
},
7129 /* VEX_LEN_0F3A61 */
7131 { "vpcmpestri!%LQ", { XM
, EXx
, Ib
}, PREFIX_DATA
},
7134 /* VEX_LEN_0F3A62 */
7136 { "vpcmpistrm", { XM
, EXx
, Ib
}, PREFIX_DATA
},
7139 /* VEX_LEN_0F3A63 */
7141 { "vpcmpistri", { XM
, EXx
, Ib
}, PREFIX_DATA
},
7144 /* VEX_LEN_0F3ADF */
7146 { "vaeskeygenassist", { XM
, EXx
, Ib
}, PREFIX_DATA
},
7149 /* VEX_LEN_0F3AF0 */
7151 { PREFIX_TABLE (PREFIX_VEX_0F3AF0_L_0
) },
7154 /* VEX_LEN_0FXOP_08_85 */
7156 { VEX_W_TABLE (VEX_W_0FXOP_08_85_L_0
) },
7159 /* VEX_LEN_0FXOP_08_86 */
7161 { VEX_W_TABLE (VEX_W_0FXOP_08_86_L_0
) },
7164 /* VEX_LEN_0FXOP_08_87 */
7166 { VEX_W_TABLE (VEX_W_0FXOP_08_87_L_0
) },
7169 /* VEX_LEN_0FXOP_08_8E */
7171 { VEX_W_TABLE (VEX_W_0FXOP_08_8E_L_0
) },
7174 /* VEX_LEN_0FXOP_08_8F */
7176 { VEX_W_TABLE (VEX_W_0FXOP_08_8F_L_0
) },
7179 /* VEX_LEN_0FXOP_08_95 */
7181 { VEX_W_TABLE (VEX_W_0FXOP_08_95_L_0
) },
7184 /* VEX_LEN_0FXOP_08_96 */
7186 { VEX_W_TABLE (VEX_W_0FXOP_08_96_L_0
) },
7189 /* VEX_LEN_0FXOP_08_97 */
7191 { VEX_W_TABLE (VEX_W_0FXOP_08_97_L_0
) },
7194 /* VEX_LEN_0FXOP_08_9E */
7196 { VEX_W_TABLE (VEX_W_0FXOP_08_9E_L_0
) },
7199 /* VEX_LEN_0FXOP_08_9F */
7201 { VEX_W_TABLE (VEX_W_0FXOP_08_9F_L_0
) },
7204 /* VEX_LEN_0FXOP_08_A3 */
7206 { "vpperm", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7209 /* VEX_LEN_0FXOP_08_A6 */
7211 { VEX_W_TABLE (VEX_W_0FXOP_08_A6_L_0
) },
7214 /* VEX_LEN_0FXOP_08_B6 */
7216 { VEX_W_TABLE (VEX_W_0FXOP_08_B6_L_0
) },
7219 /* VEX_LEN_0FXOP_08_C0 */
7221 { VEX_W_TABLE (VEX_W_0FXOP_08_C0_L_0
) },
7224 /* VEX_LEN_0FXOP_08_C1 */
7226 { VEX_W_TABLE (VEX_W_0FXOP_08_C1_L_0
) },
7229 /* VEX_LEN_0FXOP_08_C2 */
7231 { VEX_W_TABLE (VEX_W_0FXOP_08_C2_L_0
) },
7234 /* VEX_LEN_0FXOP_08_C3 */
7236 { VEX_W_TABLE (VEX_W_0FXOP_08_C3_L_0
) },
7239 /* VEX_LEN_0FXOP_08_CC */
7241 { VEX_W_TABLE (VEX_W_0FXOP_08_CC_L_0
) },
7244 /* VEX_LEN_0FXOP_08_CD */
7246 { VEX_W_TABLE (VEX_W_0FXOP_08_CD_L_0
) },
7249 /* VEX_LEN_0FXOP_08_CE */
7251 { VEX_W_TABLE (VEX_W_0FXOP_08_CE_L_0
) },
7254 /* VEX_LEN_0FXOP_08_CF */
7256 { VEX_W_TABLE (VEX_W_0FXOP_08_CF_L_0
) },
7259 /* VEX_LEN_0FXOP_08_EC */
7261 { VEX_W_TABLE (VEX_W_0FXOP_08_EC_L_0
) },
7264 /* VEX_LEN_0FXOP_08_ED */
7266 { VEX_W_TABLE (VEX_W_0FXOP_08_ED_L_0
) },
7269 /* VEX_LEN_0FXOP_08_EE */
7271 { VEX_W_TABLE (VEX_W_0FXOP_08_EE_L_0
) },
7274 /* VEX_LEN_0FXOP_08_EF */
7276 { VEX_W_TABLE (VEX_W_0FXOP_08_EF_L_0
) },
7279 /* VEX_LEN_0FXOP_09_01 */
7281 { REG_TABLE (REG_XOP_09_01_L_0
) },
7284 /* VEX_LEN_0FXOP_09_02 */
7286 { REG_TABLE (REG_XOP_09_02_L_0
) },
7289 /* VEX_LEN_0FXOP_09_12_M_1 */
7291 { REG_TABLE (REG_XOP_09_12_M_1_L_0
) },
7294 /* VEX_LEN_0FXOP_09_82_W_0 */
7296 { "vfrczss", { XM
, EXd
}, 0 },
7299 /* VEX_LEN_0FXOP_09_83_W_0 */
7301 { "vfrczsd", { XM
, EXq
}, 0 },
7304 /* VEX_LEN_0FXOP_09_90 */
7306 { "vprotb", { XM
, EXx
, VexW
}, 0 },
7309 /* VEX_LEN_0FXOP_09_91 */
7311 { "vprotw", { XM
, EXx
, VexW
}, 0 },
7314 /* VEX_LEN_0FXOP_09_92 */
7316 { "vprotd", { XM
, EXx
, VexW
}, 0 },
7319 /* VEX_LEN_0FXOP_09_93 */
7321 { "vprotq", { XM
, EXx
, VexW
}, 0 },
7324 /* VEX_LEN_0FXOP_09_94 */
7326 { "vpshlb", { XM
, EXx
, VexW
}, 0 },
7329 /* VEX_LEN_0FXOP_09_95 */
7331 { "vpshlw", { XM
, EXx
, VexW
}, 0 },
7334 /* VEX_LEN_0FXOP_09_96 */
7336 { "vpshld", { XM
, EXx
, VexW
}, 0 },
7339 /* VEX_LEN_0FXOP_09_97 */
7341 { "vpshlq", { XM
, EXx
, VexW
}, 0 },
7344 /* VEX_LEN_0FXOP_09_98 */
7346 { "vpshab", { XM
, EXx
, VexW
}, 0 },
7349 /* VEX_LEN_0FXOP_09_99 */
7351 { "vpshaw", { XM
, EXx
, VexW
}, 0 },
7354 /* VEX_LEN_0FXOP_09_9A */
7356 { "vpshad", { XM
, EXx
, VexW
}, 0 },
7359 /* VEX_LEN_0FXOP_09_9B */
7361 { "vpshaq", { XM
, EXx
, VexW
}, 0 },
7364 /* VEX_LEN_0FXOP_09_C1 */
7366 { VEX_W_TABLE (VEX_W_0FXOP_09_C1_L_0
) },
7369 /* VEX_LEN_0FXOP_09_C2 */
7371 { VEX_W_TABLE (VEX_W_0FXOP_09_C2_L_0
) },
7374 /* VEX_LEN_0FXOP_09_C3 */
7376 { VEX_W_TABLE (VEX_W_0FXOP_09_C3_L_0
) },
7379 /* VEX_LEN_0FXOP_09_C6 */
7381 { VEX_W_TABLE (VEX_W_0FXOP_09_C6_L_0
) },
7384 /* VEX_LEN_0FXOP_09_C7 */
7386 { VEX_W_TABLE (VEX_W_0FXOP_09_C7_L_0
) },
7389 /* VEX_LEN_0FXOP_09_CB */
7391 { VEX_W_TABLE (VEX_W_0FXOP_09_CB_L_0
) },
7394 /* VEX_LEN_0FXOP_09_D1 */
7396 { VEX_W_TABLE (VEX_W_0FXOP_09_D1_L_0
) },
7399 /* VEX_LEN_0FXOP_09_D2 */
7401 { VEX_W_TABLE (VEX_W_0FXOP_09_D2_L_0
) },
7404 /* VEX_LEN_0FXOP_09_D3 */
7406 { VEX_W_TABLE (VEX_W_0FXOP_09_D3_L_0
) },
7409 /* VEX_LEN_0FXOP_09_D6 */
7411 { VEX_W_TABLE (VEX_W_0FXOP_09_D6_L_0
) },
7414 /* VEX_LEN_0FXOP_09_D7 */
7416 { VEX_W_TABLE (VEX_W_0FXOP_09_D7_L_0
) },
7419 /* VEX_LEN_0FXOP_09_DB */
7421 { VEX_W_TABLE (VEX_W_0FXOP_09_DB_L_0
) },
7424 /* VEX_LEN_0FXOP_09_E1 */
7426 { VEX_W_TABLE (VEX_W_0FXOP_09_E1_L_0
) },
7429 /* VEX_LEN_0FXOP_09_E2 */
7431 { VEX_W_TABLE (VEX_W_0FXOP_09_E2_L_0
) },
7434 /* VEX_LEN_0FXOP_09_E3 */
7436 { VEX_W_TABLE (VEX_W_0FXOP_09_E3_L_0
) },
7439 /* VEX_LEN_0FXOP_0A_12 */
7441 { REG_TABLE (REG_XOP_0A_12_L_0
) },
7445 #include "i386-dis-evex-len.h"
7447 static const struct dis386 vex_w_table
[][2] = {
7449 /* VEX_W_0F41_L_1_M_1 */
7450 { PREFIX_TABLE (PREFIX_VEX_0F41_L_1_M_1_W_0
) },
7451 { PREFIX_TABLE (PREFIX_VEX_0F41_L_1_M_1_W_1
) },
7454 /* VEX_W_0F42_L_1_M_1 */
7455 { PREFIX_TABLE (PREFIX_VEX_0F42_L_1_M_1_W_0
) },
7456 { PREFIX_TABLE (PREFIX_VEX_0F42_L_1_M_1_W_1
) },
7459 /* VEX_W_0F44_L_0_M_1 */
7460 { PREFIX_TABLE (PREFIX_VEX_0F44_L_0_M_1_W_0
) },
7461 { PREFIX_TABLE (PREFIX_VEX_0F44_L_0_M_1_W_1
) },
7464 /* VEX_W_0F45_L_1_M_1 */
7465 { PREFIX_TABLE (PREFIX_VEX_0F45_L_1_M_1_W_0
) },
7466 { PREFIX_TABLE (PREFIX_VEX_0F45_L_1_M_1_W_1
) },
7469 /* VEX_W_0F46_L_1_M_1 */
7470 { PREFIX_TABLE (PREFIX_VEX_0F46_L_1_M_1_W_0
) },
7471 { PREFIX_TABLE (PREFIX_VEX_0F46_L_1_M_1_W_1
) },
7474 /* VEX_W_0F47_L_1_M_1 */
7475 { PREFIX_TABLE (PREFIX_VEX_0F47_L_1_M_1_W_0
) },
7476 { PREFIX_TABLE (PREFIX_VEX_0F47_L_1_M_1_W_1
) },
7479 /* VEX_W_0F4A_L_1_M_1 */
7480 { PREFIX_TABLE (PREFIX_VEX_0F4A_L_1_M_1_W_0
) },
7481 { PREFIX_TABLE (PREFIX_VEX_0F4A_L_1_M_1_W_1
) },
7484 /* VEX_W_0F4B_L_1_M_1 */
7485 { PREFIX_TABLE (PREFIX_VEX_0F4B_L_1_M_1_W_0
) },
7486 { PREFIX_TABLE (PREFIX_VEX_0F4B_L_1_M_1_W_1
) },
7489 /* VEX_W_0F90_L_0 */
7490 { PREFIX_TABLE (PREFIX_VEX_0F90_L_0_W_0
) },
7491 { PREFIX_TABLE (PREFIX_VEX_0F90_L_0_W_1
) },
7494 /* VEX_W_0F91_L_0_M_0 */
7495 { PREFIX_TABLE (PREFIX_VEX_0F91_L_0_M_0_W_0
) },
7496 { PREFIX_TABLE (PREFIX_VEX_0F91_L_0_M_0_W_1
) },
7499 /* VEX_W_0F92_L_0_M_1 */
7500 { PREFIX_TABLE (PREFIX_VEX_0F92_L_0_M_1_W_0
) },
7501 { PREFIX_TABLE (PREFIX_VEX_0F92_L_0_M_1_W_1
) },
7504 /* VEX_W_0F93_L_0_M_1 */
7505 { PREFIX_TABLE (PREFIX_VEX_0F93_L_0_M_1_W_0
) },
7506 { PREFIX_TABLE (PREFIX_VEX_0F93_L_0_M_1_W_1
) },
7509 /* VEX_W_0F98_L_0_M_1 */
7510 { PREFIX_TABLE (PREFIX_VEX_0F98_L_0_M_1_W_0
) },
7511 { PREFIX_TABLE (PREFIX_VEX_0F98_L_0_M_1_W_1
) },
7514 /* VEX_W_0F99_L_0_M_1 */
7515 { PREFIX_TABLE (PREFIX_VEX_0F99_L_0_M_1_W_0
) },
7516 { PREFIX_TABLE (PREFIX_VEX_0F99_L_0_M_1_W_1
) },
7520 { "vpermilps", { XM
, Vex
, EXx
}, PREFIX_DATA
},
7524 { "vpermilpd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
7528 { "vtestps", { XM
, EXx
}, PREFIX_DATA
},
7532 { "vtestpd", { XM
, EXx
}, PREFIX_DATA
},
7536 { "vcvtph2ps", { XM
, EXxmmq
}, PREFIX_DATA
},
7539 /* VEX_W_0F3816_L_1 */
7540 { "vpermps", { XM
, Vex
, EXx
}, PREFIX_DATA
},
7544 { "vbroadcastss", { XM
, EXxmm_md
}, PREFIX_DATA
},
7547 /* VEX_W_0F3819_L_1 */
7548 { "vbroadcastsd", { XM
, EXxmm_mq
}, PREFIX_DATA
},
7551 /* VEX_W_0F381A_M_0_L_1 */
7552 { "vbroadcastf128", { XM
, Mxmm
}, PREFIX_DATA
},
7555 /* VEX_W_0F382C_M_0 */
7556 { "vmaskmovps", { XM
, Vex
, Mx
}, PREFIX_DATA
},
7559 /* VEX_W_0F382D_M_0 */
7560 { "vmaskmovpd", { XM
, Vex
, Mx
}, PREFIX_DATA
},
7563 /* VEX_W_0F382E_M_0 */
7564 { "vmaskmovps", { Mx
, Vex
, XM
}, PREFIX_DATA
},
7567 /* VEX_W_0F382F_M_0 */
7568 { "vmaskmovpd", { Mx
, Vex
, XM
}, PREFIX_DATA
},
7572 { "vpermd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
7576 { "vpsravd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
7579 /* VEX_W_0F3849_X86_64_P_0 */
7580 { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_0_W_0
) },
7583 /* VEX_W_0F3849_X86_64_P_2 */
7584 { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_2_W_0
) },
7587 /* VEX_W_0F3849_X86_64_P_3 */
7588 { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_3_W_0
) },
7591 /* VEX_W_0F384B_X86_64_P_1 */
7592 { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_1_W_0
) },
7595 /* VEX_W_0F384B_X86_64_P_2 */
7596 { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_2_W_0
) },
7599 /* VEX_W_0F384B_X86_64_P_3 */
7600 { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_3_W_0
) },
7604 { "%XV vpdpbusd", { XM
, Vex
, EXx
}, 0 },
7608 { "%XV vpdpbusds", { XM
, Vex
, EXx
}, 0 },
7612 { "%XV vpdpwssd", { XM
, Vex
, EXx
}, 0 },
7616 { "%XV vpdpwssds", { XM
, Vex
, EXx
}, 0 },
7620 { "vpbroadcastd", { XM
, EXxmm_md
}, PREFIX_DATA
},
7624 { "vpbroadcastq", { XM
, EXxmm_mq
}, PREFIX_DATA
},
7627 /* VEX_W_0F385A_M_0_L_0 */
7628 { "vbroadcasti128", { XM
, Mxmm
}, PREFIX_DATA
},
7631 /* VEX_W_0F385C_X86_64_P_1 */
7632 { MOD_TABLE (MOD_VEX_0F385C_X86_64_P_1_W_0
) },
7635 /* VEX_W_0F385E_X86_64_P_0 */
7636 { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_0_W_0
) },
7639 /* VEX_W_0F385E_X86_64_P_1 */
7640 { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_1_W_0
) },
7643 /* VEX_W_0F385E_X86_64_P_2 */
7644 { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_2_W_0
) },
7647 /* VEX_W_0F385E_X86_64_P_3 */
7648 { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_3_W_0
) },
7652 { "vpbroadcastb", { XM
, EXxmm_mb
}, PREFIX_DATA
},
7656 { "vpbroadcastw", { XM
, EXxmm_mw
}, PREFIX_DATA
},
7660 { "vgf2p8mulb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
7663 /* VEX_W_0F3A00_L_1 */
7665 { "vpermq", { XM
, EXx
, Ib
}, PREFIX_DATA
},
7668 /* VEX_W_0F3A01_L_1 */
7670 { "vpermpd", { XM
, EXx
, Ib
}, PREFIX_DATA
},
7674 { "vpblendd", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
7678 { "vpermilps", { XM
, EXx
, Ib
}, PREFIX_DATA
},
7682 { "vpermilpd", { XM
, EXx
, Ib
}, PREFIX_DATA
},
7685 /* VEX_W_0F3A06_L_1 */
7686 { "vperm2f128", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
7689 /* VEX_W_0F3A18_L_1 */
7690 { "vinsertf128", { XM
, Vex
, EXxmm
, Ib
}, PREFIX_DATA
},
7693 /* VEX_W_0F3A19_L_1 */
7694 { "vextractf128", { EXxmm
, XM
, Ib
}, PREFIX_DATA
},
7698 { "vcvtps2ph", { EXxmmq
, XM
, EXxEVexS
, Ib
}, PREFIX_DATA
},
7701 /* VEX_W_0F3A38_L_1 */
7702 { "vinserti128", { XM
, Vex
, EXxmm
, Ib
}, PREFIX_DATA
},
7705 /* VEX_W_0F3A39_L_1 */
7706 { "vextracti128", { EXxmm
, XM
, Ib
}, PREFIX_DATA
},
7709 /* VEX_W_0F3A46_L_1 */
7710 { "vperm2i128", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
7714 { "vblendvps", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
7718 { "vblendvpd", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
7722 { "vpblendvb", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
7727 { "vgf2p8affineqb", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
7732 { "vgf2p8affineinvqb", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
7734 /* VEX_W_0FXOP_08_85_L_0 */
7736 { "vpmacssww", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7738 /* VEX_W_0FXOP_08_86_L_0 */
7740 { "vpmacsswd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7742 /* VEX_W_0FXOP_08_87_L_0 */
7744 { "vpmacssdql", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7746 /* VEX_W_0FXOP_08_8E_L_0 */
7748 { "vpmacssdd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7750 /* VEX_W_0FXOP_08_8F_L_0 */
7752 { "vpmacssdqh", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7754 /* VEX_W_0FXOP_08_95_L_0 */
7756 { "vpmacsww", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7758 /* VEX_W_0FXOP_08_96_L_0 */
7760 { "vpmacswd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7762 /* VEX_W_0FXOP_08_97_L_0 */
7764 { "vpmacsdql", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7766 /* VEX_W_0FXOP_08_9E_L_0 */
7768 { "vpmacsdd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7770 /* VEX_W_0FXOP_08_9F_L_0 */
7772 { "vpmacsdqh", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7774 /* VEX_W_0FXOP_08_A6_L_0 */
7776 { "vpmadcsswd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7778 /* VEX_W_0FXOP_08_B6_L_0 */
7780 { "vpmadcswd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7782 /* VEX_W_0FXOP_08_C0_L_0 */
7784 { "vprotb", { XM
, EXx
, Ib
}, 0 },
7786 /* VEX_W_0FXOP_08_C1_L_0 */
7788 { "vprotw", { XM
, EXx
, Ib
}, 0 },
7790 /* VEX_W_0FXOP_08_C2_L_0 */
7792 { "vprotd", { XM
, EXx
, Ib
}, 0 },
7794 /* VEX_W_0FXOP_08_C3_L_0 */
7796 { "vprotq", { XM
, EXx
, Ib
}, 0 },
7798 /* VEX_W_0FXOP_08_CC_L_0 */
7800 { "vpcomb", { XM
, Vex
, EXx
, VPCOM
}, 0 },
7802 /* VEX_W_0FXOP_08_CD_L_0 */
7804 { "vpcomw", { XM
, Vex
, EXx
, VPCOM
}, 0 },
7806 /* VEX_W_0FXOP_08_CE_L_0 */
7808 { "vpcomd", { XM
, Vex
, EXx
, VPCOM
}, 0 },
7810 /* VEX_W_0FXOP_08_CF_L_0 */
7812 { "vpcomq", { XM
, Vex
, EXx
, VPCOM
}, 0 },
7814 /* VEX_W_0FXOP_08_EC_L_0 */
7816 { "vpcomub", { XM
, Vex
, EXx
, VPCOM
}, 0 },
7818 /* VEX_W_0FXOP_08_ED_L_0 */
7820 { "vpcomuw", { XM
, Vex
, EXx
, VPCOM
}, 0 },
7822 /* VEX_W_0FXOP_08_EE_L_0 */
7824 { "vpcomud", { XM
, Vex
, EXx
, VPCOM
}, 0 },
7826 /* VEX_W_0FXOP_08_EF_L_0 */
7828 { "vpcomuq", { XM
, Vex
, EXx
, VPCOM
}, 0 },
7830 /* VEX_W_0FXOP_09_80 */
7832 { "vfrczps", { XM
, EXx
}, 0 },
7834 /* VEX_W_0FXOP_09_81 */
7836 { "vfrczpd", { XM
, EXx
}, 0 },
7838 /* VEX_W_0FXOP_09_82 */
7840 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_82_W_0
) },
7842 /* VEX_W_0FXOP_09_83 */
7844 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_83_W_0
) },
7846 /* VEX_W_0FXOP_09_C1_L_0 */
7848 { "vphaddbw", { XM
, EXxmm
}, 0 },
7850 /* VEX_W_0FXOP_09_C2_L_0 */
7852 { "vphaddbd", { XM
, EXxmm
}, 0 },
7854 /* VEX_W_0FXOP_09_C3_L_0 */
7856 { "vphaddbq", { XM
, EXxmm
}, 0 },
7858 /* VEX_W_0FXOP_09_C6_L_0 */
7860 { "vphaddwd", { XM
, EXxmm
}, 0 },
7862 /* VEX_W_0FXOP_09_C7_L_0 */
7864 { "vphaddwq", { XM
, EXxmm
}, 0 },
7866 /* VEX_W_0FXOP_09_CB_L_0 */
7868 { "vphadddq", { XM
, EXxmm
}, 0 },
7870 /* VEX_W_0FXOP_09_D1_L_0 */
7872 { "vphaddubw", { XM
, EXxmm
}, 0 },
7874 /* VEX_W_0FXOP_09_D2_L_0 */
7876 { "vphaddubd", { XM
, EXxmm
}, 0 },
7878 /* VEX_W_0FXOP_09_D3_L_0 */
7880 { "vphaddubq", { XM
, EXxmm
}, 0 },
7882 /* VEX_W_0FXOP_09_D6_L_0 */
7884 { "vphadduwd", { XM
, EXxmm
}, 0 },
7886 /* VEX_W_0FXOP_09_D7_L_0 */
7888 { "vphadduwq", { XM
, EXxmm
}, 0 },
7890 /* VEX_W_0FXOP_09_DB_L_0 */
7892 { "vphaddudq", { XM
, EXxmm
}, 0 },
7894 /* VEX_W_0FXOP_09_E1_L_0 */
7896 { "vphsubbw", { XM
, EXxmm
}, 0 },
7898 /* VEX_W_0FXOP_09_E2_L_0 */
7900 { "vphsubwd", { XM
, EXxmm
}, 0 },
7902 /* VEX_W_0FXOP_09_E3_L_0 */
7904 { "vphsubdq", { XM
, EXxmm
}, 0 },
7907 #include "i386-dis-evex-w.h"
7910 static const struct dis386 mod_table
[][2] = {
7913 { "bound{S|}", { Gv
, Ma
}, 0 },
7914 { EVEX_TABLE (EVEX_0F
) },
7918 { "leaS", { Gv
, M
}, 0 },
7922 { "lesS", { Gv
, Mp
}, 0 },
7923 { VEX_C4_TABLE (VEX_0F
) },
7927 { "ldsS", { Gv
, Mp
}, 0 },
7928 { VEX_C5_TABLE (VEX_0F
) },
7933 { RM_TABLE (RM_C6_REG_7
) },
7938 { RM_TABLE (RM_C7_REG_7
) },
7942 { "{l|}call^", { indirEp
}, 0 },
7946 { "{l|}jmp^", { indirEp
}, 0 },
7949 /* MOD_0F01_REG_0 */
7950 { X86_64_TABLE (X86_64_0F01_REG_0
) },
7951 { RM_TABLE (RM_0F01_REG_0
) },
7954 /* MOD_0F01_REG_1 */
7955 { X86_64_TABLE (X86_64_0F01_REG_1
) },
7956 { RM_TABLE (RM_0F01_REG_1
) },
7959 /* MOD_0F01_REG_2 */
7960 { X86_64_TABLE (X86_64_0F01_REG_2
) },
7961 { RM_TABLE (RM_0F01_REG_2
) },
7964 /* MOD_0F01_REG_3 */
7965 { X86_64_TABLE (X86_64_0F01_REG_3
) },
7966 { RM_TABLE (RM_0F01_REG_3
) },
7969 /* MOD_0F01_REG_5 */
7970 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0
) },
7971 { RM_TABLE (RM_0F01_REG_5_MOD_3
) },
7974 /* MOD_0F01_REG_7 */
7975 { "invlpg", { Mb
}, 0 },
7976 { RM_TABLE (RM_0F01_REG_7_MOD_3
) },
7979 /* MOD_0F12_PREFIX_0 */
7980 { "movlpX", { XM
, EXq
}, 0 },
7981 { "movhlps", { XM
, EXq
}, 0 },
7984 /* MOD_0F12_PREFIX_2 */
7985 { "movlpX", { XM
, EXq
}, 0 },
7989 { "movlpX", { EXq
, XM
}, PREFIX_OPCODE
},
7992 /* MOD_0F16_PREFIX_0 */
7993 { "movhpX", { XM
, EXq
}, 0 },
7994 { "movlhps", { XM
, EXq
}, 0 },
7997 /* MOD_0F16_PREFIX_2 */
7998 { "movhpX", { XM
, EXq
}, 0 },
8002 { "movhpX", { EXq
, XM
}, PREFIX_OPCODE
},
8005 /* MOD_0F18_REG_0 */
8006 { "prefetchnta", { Mb
}, 0 },
8007 { "nopQ", { Ev
}, 0 },
8010 /* MOD_0F18_REG_1 */
8011 { "prefetcht0", { Mb
}, 0 },
8012 { "nopQ", { Ev
}, 0 },
8015 /* MOD_0F18_REG_2 */
8016 { "prefetcht1", { Mb
}, 0 },
8017 { "nopQ", { Ev
}, 0 },
8020 /* MOD_0F18_REG_3 */
8021 { "prefetcht2", { Mb
}, 0 },
8022 { "nopQ", { Ev
}, 0 },
8025 /* MOD_0F1A_PREFIX_0 */
8026 { "bndldx", { Gbnd
, Mv_bnd
}, 0 },
8027 { "nopQ", { Ev
}, 0 },
8030 /* MOD_0F1B_PREFIX_0 */
8031 { "bndstx", { Mv_bnd
, Gbnd
}, 0 },
8032 { "nopQ", { Ev
}, 0 },
8035 /* MOD_0F1B_PREFIX_1 */
8036 { "bndmk", { Gbnd
, Mv_bnd
}, 0 },
8037 { "nopQ", { Ev
}, PREFIX_IGNORED
},
8040 /* MOD_0F1C_PREFIX_0 */
8041 { REG_TABLE (REG_0F1C_P_0_MOD_0
) },
8042 { "nopQ", { Ev
}, 0 },
8045 /* MOD_0F1E_PREFIX_1 */
8046 { "nopQ", { Ev
}, PREFIX_IGNORED
},
8047 { REG_TABLE (REG_0F1E_P_1_MOD_3
) },
8050 /* MOD_0F2B_PREFIX_0 */
8051 {"movntps", { Mx
, XM
}, PREFIX_OPCODE
},
8054 /* MOD_0F2B_PREFIX_1 */
8055 {"movntss", { Md
, XM
}, PREFIX_OPCODE
},
8058 /* MOD_0F2B_PREFIX_2 */
8059 {"movntpd", { Mx
, XM
}, PREFIX_OPCODE
},
8062 /* MOD_0F2B_PREFIX_3 */
8063 {"movntsd", { Mq
, XM
}, PREFIX_OPCODE
},
8068 { "movmskpX", { Gdq
, XS
}, PREFIX_OPCODE
},
8073 { REG_TABLE (REG_0F71_MOD_0
) },
8078 { REG_TABLE (REG_0F72_MOD_0
) },
8083 { REG_TABLE (REG_0F73_MOD_0
) },
8086 /* MOD_0FAE_REG_0 */
8087 { "fxsave", { FXSAVE
}, 0 },
8088 { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3
) },
8091 /* MOD_0FAE_REG_1 */
8092 { "fxrstor", { FXSAVE
}, 0 },
8093 { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3
) },
8096 /* MOD_0FAE_REG_2 */
8097 { "ldmxcsr", { Md
}, 0 },
8098 { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3
) },
8101 /* MOD_0FAE_REG_3 */
8102 { "stmxcsr", { Md
}, 0 },
8103 { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3
) },
8106 /* MOD_0FAE_REG_4 */
8107 { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0
) },
8108 { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3
) },
8111 /* MOD_0FAE_REG_5 */
8112 { "xrstor", { FXSAVE
}, PREFIX_OPCODE
},
8113 { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3
) },
8116 /* MOD_0FAE_REG_6 */
8117 { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0
) },
8118 { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3
) },
8121 /* MOD_0FAE_REG_7 */
8122 { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0
) },
8123 { RM_TABLE (RM_0FAE_REG_7_MOD_3
) },
8127 { "lssS", { Gv
, Mp
}, 0 },
8131 { "lfsS", { Gv
, Mp
}, 0 },
8135 { "lgsS", { Gv
, Mp
}, 0 },
8139 { "movntiS", { Edq
, Gdq
}, PREFIX_OPCODE
},
8142 /* MOD_0FC7_REG_3 */
8143 { "xrstors", { FXSAVE
}, 0 },
8146 /* MOD_0FC7_REG_4 */
8147 { "xsavec", { FXSAVE
}, 0 },
8150 /* MOD_0FC7_REG_5 */
8151 { "xsaves", { FXSAVE
}, 0 },
8154 /* MOD_0FC7_REG_6 */
8155 { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0
) },
8156 { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3
) }
8159 /* MOD_0FC7_REG_7 */
8160 { "vmptrst", { Mq
}, 0 },
8161 { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3
) }
8166 { "pmovmskb", { Gdq
, MS
}, 0 },
8169 /* MOD_0FE7_PREFIX_2 */
8170 { "movntdq", { Mx
, XM
}, 0 },
8173 /* MOD_0FF0_PREFIX_3 */
8174 { "lddqu", { XM
, M
}, 0 },
8178 { "movntdqa", { XM
, Mx
}, PREFIX_DATA
},
8181 /* MOD_0F38DC_PREFIX_1 */
8182 { "aesenc128kl", { XM
, M
}, 0 },
8183 { "loadiwkey", { XM
, EXx
}, 0 },
8186 /* MOD_0F38DD_PREFIX_1 */
8187 { "aesdec128kl", { XM
, M
}, 0 },
8190 /* MOD_0F38DE_PREFIX_1 */
8191 { "aesenc256kl", { XM
, M
}, 0 },
8194 /* MOD_0F38DF_PREFIX_1 */
8195 { "aesdec256kl", { XM
, M
}, 0 },
8199 { "wrussK", { M
, Gdq
}, PREFIX_DATA
},
8202 /* MOD_0F38F6_PREFIX_0 */
8203 { "wrssK", { M
, Gdq
}, PREFIX_OPCODE
},
8206 /* MOD_0F38F8_PREFIX_1 */
8207 { "enqcmds", { Gva
, M
}, PREFIX_OPCODE
},
8210 /* MOD_0F38F8_PREFIX_2 */
8211 { "movdir64b", { Gva
, M
}, PREFIX_OPCODE
},
8214 /* MOD_0F38F8_PREFIX_3 */
8215 { "enqcmd", { Gva
, M
}, PREFIX_OPCODE
},
8219 { "movdiri", { Edq
, Gdq
}, PREFIX_OPCODE
},
8222 /* MOD_0F38FA_PREFIX_1 */
8224 { "encodekey128", { Gd
, Ed
}, 0 },
8227 /* MOD_0F38FB_PREFIX_1 */
8229 { "encodekey256", { Gd
, Ed
}, 0 },
8232 /* MOD_0F3A0F_PREFIX_1 */
8234 { REG_TABLE (REG_0F3A0F_PREFIX_1_MOD_3
) },
8237 /* MOD_VEX_0F12_PREFIX_0 */
8238 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0
) },
8239 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1
) },
8242 /* MOD_VEX_0F12_PREFIX_2 */
8243 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2_M_0
) },
8247 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0
) },
8250 /* MOD_VEX_0F16_PREFIX_0 */
8251 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0
) },
8252 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1
) },
8255 /* MOD_VEX_0F16_PREFIX_2 */
8256 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2_M_0
) },
8260 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0
) },
8264 { "vmovntpX", { Mx
, XM
}, PREFIX_OPCODE
},
8267 /* MOD_VEX_0F41_L_1 */
8269 { VEX_W_TABLE (VEX_W_0F41_L_1_M_1
) },
8272 /* MOD_VEX_0F42_L_1 */
8274 { VEX_W_TABLE (VEX_W_0F42_L_1_M_1
) },
8277 /* MOD_VEX_0F44_L_0 */
8279 { VEX_W_TABLE (VEX_W_0F44_L_0_M_1
) },
8282 /* MOD_VEX_0F45_L_1 */
8284 { VEX_W_TABLE (VEX_W_0F45_L_1_M_1
) },
8287 /* MOD_VEX_0F46_L_1 */
8289 { VEX_W_TABLE (VEX_W_0F46_L_1_M_1
) },
8292 /* MOD_VEX_0F47_L_1 */
8294 { VEX_W_TABLE (VEX_W_0F47_L_1_M_1
) },
8297 /* MOD_VEX_0F4A_L_1 */
8299 { VEX_W_TABLE (VEX_W_0F4A_L_1_M_1
) },
8302 /* MOD_VEX_0F4B_L_1 */
8304 { VEX_W_TABLE (VEX_W_0F4B_L_1_M_1
) },
8309 { "vmovmskpX", { Gdq
, XS
}, PREFIX_OPCODE
},
8314 { REG_TABLE (REG_VEX_0F71_M_0
) },
8319 { REG_TABLE (REG_VEX_0F72_M_0
) },
8324 { REG_TABLE (REG_VEX_0F73_M_0
) },
8327 /* MOD_VEX_0F91_L_0 */
8328 { VEX_W_TABLE (VEX_W_0F91_L_0_M_0
) },
8331 /* MOD_VEX_0F92_L_0 */
8333 { VEX_W_TABLE (VEX_W_0F92_L_0_M_1
) },
8336 /* MOD_VEX_0F93_L_0 */
8338 { VEX_W_TABLE (VEX_W_0F93_L_0_M_1
) },
8341 /* MOD_VEX_0F98_L_0 */
8343 { VEX_W_TABLE (VEX_W_0F98_L_0_M_1
) },
8346 /* MOD_VEX_0F99_L_0 */
8348 { VEX_W_TABLE (VEX_W_0F99_L_0_M_1
) },
8351 /* MOD_VEX_0FAE_REG_2 */
8352 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0
) },
8355 /* MOD_VEX_0FAE_REG_3 */
8356 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0
) },
8361 { "vpmovmskb", { Gdq
, XS
}, PREFIX_DATA
},
8365 { "vmovntdq", { Mx
, XM
}, PREFIX_DATA
},
8368 /* MOD_VEX_0FF0_PREFIX_3 */
8369 { "vlddqu", { XM
, M
}, 0 },
8372 /* MOD_VEX_0F381A */
8373 { VEX_LEN_TABLE (VEX_LEN_0F381A_M_0
) },
8376 /* MOD_VEX_0F382A */
8377 { "vmovntdqa", { XM
, Mx
}, PREFIX_DATA
},
8380 /* MOD_VEX_0F382C */
8381 { VEX_W_TABLE (VEX_W_0F382C_M_0
) },
8384 /* MOD_VEX_0F382D */
8385 { VEX_W_TABLE (VEX_W_0F382D_M_0
) },
8388 /* MOD_VEX_0F382E */
8389 { VEX_W_TABLE (VEX_W_0F382E_M_0
) },
8392 /* MOD_VEX_0F382F */
8393 { VEX_W_TABLE (VEX_W_0F382F_M_0
) },
8396 /* MOD_VEX_0F3849_X86_64_P_0_W_0 */
8397 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0
) },
8398 { REG_TABLE (REG_VEX_0F3849_X86_64_P_0_W_0_M_1
) },
8401 /* MOD_VEX_0F3849_X86_64_P_2_W_0 */
8402 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0
) },
8405 /* MOD_VEX_0F3849_X86_64_P_3_W_0 */
8407 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0
) },
8410 /* MOD_VEX_0F384B_X86_64_P_1_W_0 */
8411 { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0
) },
8414 /* MOD_VEX_0F384B_X86_64_P_2_W_0 */
8415 { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0
) },
8418 /* MOD_VEX_0F384B_X86_64_P_3_W_0 */
8419 { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0
) },
8422 /* MOD_VEX_0F385A */
8423 { VEX_LEN_TABLE (VEX_LEN_0F385A_M_0
) },
8426 /* MOD_VEX_0F385C_X86_64_P_1_W_0 */
8428 { VEX_LEN_TABLE (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0
) },
8431 /* MOD_VEX_0F385E_X86_64_P_0_W_0 */
8433 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0
) },
8436 /* MOD_VEX_0F385E_X86_64_P_1_W_0 */
8438 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0
) },
8441 /* MOD_VEX_0F385E_X86_64_P_2_W_0 */
8443 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0
) },
8446 /* MOD_VEX_0F385E_X86_64_P_3_W_0 */
8448 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0
) },
8451 /* MOD_VEX_0F388C */
8452 { "vpmaskmov%DQ", { XM
, Vex
, Mx
}, PREFIX_DATA
},
8455 /* MOD_VEX_0F388E */
8456 { "vpmaskmov%DQ", { Mx
, Vex
, XM
}, PREFIX_DATA
},
8459 /* MOD_VEX_0F3A30_L_0 */
8461 { "kshiftr%BW", { MaskG
, MaskE
, Ib
}, PREFIX_DATA
},
8464 /* MOD_VEX_0F3A31_L_0 */
8466 { "kshiftr%DQ", { MaskG
, MaskE
, Ib
}, PREFIX_DATA
},
8469 /* MOD_VEX_0F3A32_L_0 */
8471 { "kshiftl%BW", { MaskG
, MaskE
, Ib
}, PREFIX_DATA
},
8474 /* MOD_VEX_0F3A33_L_0 */
8476 { "kshiftl%DQ", { MaskG
, MaskE
, Ib
}, PREFIX_DATA
},
8481 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_12_M_1
) },
8484 #include "i386-dis-evex-mod.h"
8487 static const struct dis386 rm_table
[][8] = {
8490 { "xabort", { Skip_MODRM
, Ib
}, 0 },
8494 { "xbeginT", { Skip_MODRM
, Jdqw
}, 0 },
8498 { "enclv", { Skip_MODRM
}, 0 },
8499 { "vmcall", { Skip_MODRM
}, 0 },
8500 { "vmlaunch", { Skip_MODRM
}, 0 },
8501 { "vmresume", { Skip_MODRM
}, 0 },
8502 { "vmxoff", { Skip_MODRM
}, 0 },
8503 { "pconfig", { Skip_MODRM
}, 0 },
8507 { "monitor", { { OP_Monitor
, 0 } }, 0 },
8508 { "mwait", { { OP_Mwait
, 0 } }, 0 },
8509 { "clac", { Skip_MODRM
}, 0 },
8510 { "stac", { Skip_MODRM
}, 0 },
8511 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_4
) },
8512 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_5
) },
8513 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_6
) },
8514 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_7
) },
8518 { "xgetbv", { Skip_MODRM
}, 0 },
8519 { "xsetbv", { Skip_MODRM
}, 0 },
8522 { "vmfunc", { Skip_MODRM
}, 0 },
8523 { "xend", { Skip_MODRM
}, 0 },
8524 { "xtest", { Skip_MODRM
}, 0 },
8525 { "enclu", { Skip_MODRM
}, 0 },
8529 { "vmrun", { Skip_MODRM
}, 0 },
8530 { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1
) },
8531 { "vmload", { Skip_MODRM
}, 0 },
8532 { "vmsave", { Skip_MODRM
}, 0 },
8533 { "stgi", { Skip_MODRM
}, 0 },
8534 { "clgi", { Skip_MODRM
}, 0 },
8535 { "skinit", { Skip_MODRM
}, 0 },
8536 { "invlpga", { Skip_MODRM
}, 0 },
8539 /* RM_0F01_REG_5_MOD_3 */
8540 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0
) },
8541 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1
) },
8542 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2
) },
8544 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_4
) },
8545 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_5
) },
8546 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_6
) },
8547 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_7
) },
8550 /* RM_0F01_REG_7_MOD_3 */
8551 { "swapgs", { Skip_MODRM
}, 0 },
8552 { "rdtscp", { Skip_MODRM
}, 0 },
8553 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2
) },
8554 { "mwaitx", { { OP_Mwait
, eBX_reg
} }, PREFIX_OPCODE
},
8555 { "clzero", { Skip_MODRM
}, 0 },
8556 { "rdpru", { Skip_MODRM
}, 0 },
8557 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_6
) },
8558 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_7
) },
8561 /* RM_0F1E_P_1_MOD_3_REG_7 */
8562 { "nopQ", { Ev
}, PREFIX_IGNORED
},
8563 { "nopQ", { Ev
}, PREFIX_IGNORED
},
8564 { "endbr64", { Skip_MODRM
}, 0 },
8565 { "endbr32", { Skip_MODRM
}, 0 },
8566 { "nopQ", { Ev
}, PREFIX_IGNORED
},
8567 { "nopQ", { Ev
}, PREFIX_IGNORED
},
8568 { "nopQ", { Ev
}, PREFIX_IGNORED
},
8569 { "nopQ", { Ev
}, PREFIX_IGNORED
},
8572 /* RM_0FAE_REG_6_MOD_3 */
8573 { "mfence", { Skip_MODRM
}, 0 },
8576 /* RM_0FAE_REG_7_MOD_3 */
8577 { "sfence", { Skip_MODRM
}, 0 },
8580 /* RM_0F3A0F_P_1_MOD_3_REG_0 */
8581 { "hreset", { Skip_MODRM
, Ib
}, 0 },
8584 /* RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0 */
8585 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0
) },
8589 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
8591 /* We use the high bit to indicate different name for the same
8593 #define REP_PREFIX (0xf3 | 0x100)
8594 #define XACQUIRE_PREFIX (0xf2 | 0x200)
8595 #define XRELEASE_PREFIX (0xf3 | 0x400)
8596 #define BND_PREFIX (0xf2 | 0x400)
8597 #define NOTRACK_PREFIX (0x3e | 0x100)
8599 /* Remember if the current op is a jump instruction. */
8600 static bfd_boolean op_is_jump
= FALSE
;
8605 int newrex
, i
, length
;
8610 last_lock_prefix
= -1;
8611 last_repz_prefix
= -1;
8612 last_repnz_prefix
= -1;
8613 last_data_prefix
= -1;
8614 last_addr_prefix
= -1;
8615 last_rex_prefix
= -1;
8616 last_seg_prefix
= -1;
8618 active_seg_prefix
= 0;
8619 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
8620 all_prefixes
[i
] = 0;
8623 /* The maximum instruction length is 15bytes. */
8624 while (length
< MAX_CODE_LENGTH
- 1)
8626 FETCH_DATA (the_info
, codep
+ 1);
8630 /* REX prefixes family. */
8647 if (address_mode
== mode_64bit
)
8651 last_rex_prefix
= i
;
8654 prefixes
|= PREFIX_REPZ
;
8655 last_repz_prefix
= i
;
8658 prefixes
|= PREFIX_REPNZ
;
8659 last_repnz_prefix
= i
;
8662 prefixes
|= PREFIX_LOCK
;
8663 last_lock_prefix
= i
;
8666 prefixes
|= PREFIX_CS
;
8667 last_seg_prefix
= i
;
8669 if (address_mode
!= mode_64bit
)
8670 active_seg_prefix
= PREFIX_CS
;
8674 prefixes
|= PREFIX_SS
;
8675 last_seg_prefix
= i
;
8677 if (address_mode
!= mode_64bit
)
8678 active_seg_prefix
= PREFIX_SS
;
8682 prefixes
|= PREFIX_DS
;
8683 last_seg_prefix
= i
;
8685 if (address_mode
!= mode_64bit
)
8686 active_seg_prefix
= PREFIX_DS
;
8690 prefixes
|= PREFIX_ES
;
8691 last_seg_prefix
= i
;
8693 if (address_mode
!= mode_64bit
)
8694 active_seg_prefix
= PREFIX_ES
;
8698 prefixes
|= PREFIX_FS
;
8699 last_seg_prefix
= i
;
8700 active_seg_prefix
= PREFIX_FS
;
8703 prefixes
|= PREFIX_GS
;
8704 last_seg_prefix
= i
;
8705 active_seg_prefix
= PREFIX_GS
;
8708 prefixes
|= PREFIX_DATA
;
8709 last_data_prefix
= i
;
8712 prefixes
|= PREFIX_ADDR
;
8713 last_addr_prefix
= i
;
8716 /* fwait is really an instruction. If there are prefixes
8717 before the fwait, they belong to the fwait, *not* to the
8718 following instruction. */
8720 if (prefixes
|| rex
)
8722 prefixes
|= PREFIX_FWAIT
;
8724 /* This ensures that the previous REX prefixes are noticed
8725 as unused prefixes, as in the return case below. */
8729 prefixes
= PREFIX_FWAIT
;
8734 /* Rex is ignored when followed by another prefix. */
8740 if (*codep
!= FWAIT_OPCODE
)
8741 all_prefixes
[i
++] = *codep
;
8749 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
8753 prefix_name (int pref
, int sizeflag
)
8755 static const char *rexes
[16] =
8760 "rex.XB", /* 0x43 */
8762 "rex.RB", /* 0x45 */
8763 "rex.RX", /* 0x46 */
8764 "rex.RXB", /* 0x47 */
8766 "rex.WB", /* 0x49 */
8767 "rex.WX", /* 0x4a */
8768 "rex.WXB", /* 0x4b */
8769 "rex.WR", /* 0x4c */
8770 "rex.WRB", /* 0x4d */
8771 "rex.WRX", /* 0x4e */
8772 "rex.WRXB", /* 0x4f */
8777 /* REX prefixes family. */
8794 return rexes
[pref
- 0x40];
8814 return (sizeflag
& DFLAG
) ? "data16" : "data32";
8816 if (address_mode
== mode_64bit
)
8817 return (sizeflag
& AFLAG
) ? "addr32" : "addr64";
8819 return (sizeflag
& AFLAG
) ? "addr16" : "addr32";
8824 case XACQUIRE_PREFIX
:
8826 case XRELEASE_PREFIX
:
8830 case NOTRACK_PREFIX
:
8837 static char op_out
[MAX_OPERANDS
][100];
8838 static int op_ad
, op_index
[MAX_OPERANDS
];
8839 static int two_source_ops
;
8840 static bfd_vma op_address
[MAX_OPERANDS
];
8841 static bfd_vma op_riprel
[MAX_OPERANDS
];
8842 static bfd_vma start_pc
;
8845 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
8846 * (see topic "Redundant prefixes" in the "Differences from 8086"
8847 * section of the "Virtual 8086 Mode" chapter.)
8848 * 'pc' should be the address of this instruction, it will
8849 * be used to print the target address if this is a relative jump or call
8850 * The function returns the length of this instruction in bytes.
8853 static char intel_syntax
;
8854 static char intel_mnemonic
= !SYSV386_COMPAT
;
8855 static char open_char
;
8856 static char close_char
;
8857 static char separator_char
;
8858 static char scale_char
;
8866 static enum x86_64_isa isa64
;
8868 /* Here for backwards compatibility. When gdb stops using
8869 print_insn_i386_att and print_insn_i386_intel these functions can
8870 disappear, and print_insn_i386 be merged into print_insn. */
8872 print_insn_i386_att (bfd_vma pc
, disassemble_info
*info
)
8876 return print_insn (pc
, info
);
8880 print_insn_i386_intel (bfd_vma pc
, disassemble_info
*info
)
8884 return print_insn (pc
, info
);
8888 print_insn_i386 (bfd_vma pc
, disassemble_info
*info
)
8892 return print_insn (pc
, info
);
8896 print_i386_disassembler_options (FILE *stream
)
8898 fprintf (stream
, _("\n\
8899 The following i386/x86-64 specific disassembler options are supported for use\n\
8900 with the -M switch (multiple options should be separated by commas):\n"));
8902 fprintf (stream
, _(" x86-64 Disassemble in 64bit mode\n"));
8903 fprintf (stream
, _(" i386 Disassemble in 32bit mode\n"));
8904 fprintf (stream
, _(" i8086 Disassemble in 16bit mode\n"));
8905 fprintf (stream
, _(" att Display instruction in AT&T syntax\n"));
8906 fprintf (stream
, _(" intel Display instruction in Intel syntax\n"));
8907 fprintf (stream
, _(" att-mnemonic\n"
8908 " Display instruction in AT&T mnemonic\n"));
8909 fprintf (stream
, _(" intel-mnemonic\n"
8910 " Display instruction in Intel mnemonic\n"));
8911 fprintf (stream
, _(" addr64 Assume 64bit address size\n"));
8912 fprintf (stream
, _(" addr32 Assume 32bit address size\n"));
8913 fprintf (stream
, _(" addr16 Assume 16bit address size\n"));
8914 fprintf (stream
, _(" data32 Assume 32bit data size\n"));
8915 fprintf (stream
, _(" data16 Assume 16bit data size\n"));
8916 fprintf (stream
, _(" suffix Always display instruction suffix in AT&T syntax\n"));
8917 fprintf (stream
, _(" amd64 Display instruction in AMD64 ISA\n"));
8918 fprintf (stream
, _(" intel64 Display instruction in Intel64 ISA\n"));
8922 static const struct dis386 bad_opcode
= { "(bad)", { XX
}, 0 };
8924 /* Get a pointer to struct dis386 with a valid name. */
8926 static const struct dis386
*
8927 get_valid_dis386 (const struct dis386
*dp
, disassemble_info
*info
)
8929 int vindex
, vex_table_index
;
8931 if (dp
->name
!= NULL
)
8934 switch (dp
->op
[0].bytemode
)
8937 dp
= ®_table
[dp
->op
[1].bytemode
][modrm
.reg
];
8941 vindex
= modrm
.mod
== 0x3 ? 1 : 0;
8942 dp
= &mod_table
[dp
->op
[1].bytemode
][vindex
];
8946 dp
= &rm_table
[dp
->op
[1].bytemode
][modrm
.rm
];
8949 case USE_PREFIX_TABLE
:
8952 /* The prefix in VEX is implicit. */
8958 case REPE_PREFIX_OPCODE
:
8961 case DATA_PREFIX_OPCODE
:
8964 case REPNE_PREFIX_OPCODE
:
8974 int last_prefix
= -1;
8977 /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
8978 When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
8980 if ((prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0)
8982 if (last_repz_prefix
> last_repnz_prefix
)
8985 prefix
= PREFIX_REPZ
;
8986 last_prefix
= last_repz_prefix
;
8991 prefix
= PREFIX_REPNZ
;
8992 last_prefix
= last_repnz_prefix
;
8995 /* Check if prefix should be ignored. */
8996 if ((((prefix_table
[dp
->op
[1].bytemode
][vindex
].prefix_requirement
8997 & PREFIX_IGNORED
) >> PREFIX_IGNORED_SHIFT
)
8999 && !prefix_table
[dp
->op
[1].bytemode
][vindex
].name
)
9003 if (vindex
== 0 && (prefixes
& PREFIX_DATA
) != 0)
9006 prefix
= PREFIX_DATA
;
9007 last_prefix
= last_data_prefix
;
9012 used_prefixes
|= prefix
;
9013 all_prefixes
[last_prefix
] = 0;
9016 dp
= &prefix_table
[dp
->op
[1].bytemode
][vindex
];
9019 case USE_X86_64_TABLE
:
9020 vindex
= address_mode
== mode_64bit
? 1 : 0;
9021 dp
= &x86_64_table
[dp
->op
[1].bytemode
][vindex
];
9024 case USE_3BYTE_TABLE
:
9025 FETCH_DATA (info
, codep
+ 2);
9027 dp
= &three_byte_table
[dp
->op
[1].bytemode
][vindex
];
9029 modrm
.mod
= (*codep
>> 6) & 3;
9030 modrm
.reg
= (*codep
>> 3) & 7;
9031 modrm
.rm
= *codep
& 7;
9034 case USE_VEX_LEN_TABLE
:
9044 /* This allows re-using in particular table entries where only
9045 128-bit operand size (VEX.L=0 / EVEX.L'L=0) are valid. */
9058 dp
= &vex_len_table
[dp
->op
[1].bytemode
][vindex
];
9061 case USE_EVEX_LEN_TABLE
:
9081 dp
= &evex_len_table
[dp
->op
[1].bytemode
][vindex
];
9084 case USE_XOP_8F_TABLE
:
9085 FETCH_DATA (info
, codep
+ 3);
9086 rex
= ~(*codep
>> 5) & 0x7;
9088 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
9089 switch ((*codep
& 0x1f))
9095 vex_table_index
= XOP_08
;
9098 vex_table_index
= XOP_09
;
9101 vex_table_index
= XOP_0A
;
9105 vex
.w
= *codep
& 0x80;
9106 if (vex
.w
&& address_mode
== mode_64bit
)
9109 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
9110 if (address_mode
!= mode_64bit
)
9112 /* In 16/32-bit mode REX_B is silently ignored. */
9116 vex
.length
= (*codep
& 0x4) ? 256 : 128;
9117 switch ((*codep
& 0x3))
9122 vex
.prefix
= DATA_PREFIX_OPCODE
;
9125 vex
.prefix
= REPE_PREFIX_OPCODE
;
9128 vex
.prefix
= REPNE_PREFIX_OPCODE
;
9134 dp
= &xop_table
[vex_table_index
][vindex
];
9137 FETCH_DATA (info
, codep
+ 1);
9138 modrm
.mod
= (*codep
>> 6) & 3;
9139 modrm
.reg
= (*codep
>> 3) & 7;
9140 modrm
.rm
= *codep
& 7;
9142 /* No XOP encoding so far allows for a non-zero embedded prefix. Avoid
9143 having to decode the bits for every otherwise valid encoding. */
9148 case USE_VEX_C4_TABLE
:
9150 FETCH_DATA (info
, codep
+ 3);
9151 rex
= ~(*codep
>> 5) & 0x7;
9152 switch ((*codep
& 0x1f))
9158 vex_table_index
= VEX_0F
;
9161 vex_table_index
= VEX_0F38
;
9164 vex_table_index
= VEX_0F3A
;
9168 vex
.w
= *codep
& 0x80;
9169 if (address_mode
== mode_64bit
)
9176 /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
9177 is ignored, other REX bits are 0 and the highest bit in
9178 VEX.vvvv is also ignored (but we mustn't clear it here). */
9181 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
9182 vex
.length
= (*codep
& 0x4) ? 256 : 128;
9183 switch ((*codep
& 0x3))
9188 vex
.prefix
= DATA_PREFIX_OPCODE
;
9191 vex
.prefix
= REPE_PREFIX_OPCODE
;
9194 vex
.prefix
= REPNE_PREFIX_OPCODE
;
9200 dp
= &vex_table
[vex_table_index
][vindex
];
9202 /* There is no MODRM byte for VEX0F 77. */
9203 if (vex_table_index
!= VEX_0F
|| vindex
!= 0x77)
9205 FETCH_DATA (info
, codep
+ 1);
9206 modrm
.mod
= (*codep
>> 6) & 3;
9207 modrm
.reg
= (*codep
>> 3) & 7;
9208 modrm
.rm
= *codep
& 7;
9212 case USE_VEX_C5_TABLE
:
9214 FETCH_DATA (info
, codep
+ 2);
9215 rex
= (*codep
& 0x80) ? 0 : REX_R
;
9217 /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
9219 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
9220 vex
.length
= (*codep
& 0x4) ? 256 : 128;
9221 switch ((*codep
& 0x3))
9226 vex
.prefix
= DATA_PREFIX_OPCODE
;
9229 vex
.prefix
= REPE_PREFIX_OPCODE
;
9232 vex
.prefix
= REPNE_PREFIX_OPCODE
;
9238 dp
= &vex_table
[dp
->op
[1].bytemode
][vindex
];
9240 /* There is no MODRM byte for VEX 77. */
9243 FETCH_DATA (info
, codep
+ 1);
9244 modrm
.mod
= (*codep
>> 6) & 3;
9245 modrm
.reg
= (*codep
>> 3) & 7;
9246 modrm
.rm
= *codep
& 7;
9250 case USE_VEX_W_TABLE
:
9254 dp
= &vex_w_table
[dp
->op
[1].bytemode
][vex
.w
? 1 : 0];
9257 case USE_EVEX_TABLE
:
9261 FETCH_DATA (info
, codep
+ 4);
9262 /* The first byte after 0x62. */
9263 rex
= ~(*codep
>> 5) & 0x7;
9264 vex
.r
= *codep
& 0x10;
9265 switch ((*codep
& 0xf))
9270 vex_table_index
= EVEX_0F
;
9273 vex_table_index
= EVEX_0F38
;
9276 vex_table_index
= EVEX_0F3A
;
9280 /* The second byte after 0x62. */
9282 vex
.w
= *codep
& 0x80;
9283 if (vex
.w
&& address_mode
== mode_64bit
)
9286 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
9289 if (!(*codep
& 0x4))
9292 switch ((*codep
& 0x3))
9297 vex
.prefix
= DATA_PREFIX_OPCODE
;
9300 vex
.prefix
= REPE_PREFIX_OPCODE
;
9303 vex
.prefix
= REPNE_PREFIX_OPCODE
;
9307 /* The third byte after 0x62. */
9310 /* Remember the static rounding bits. */
9311 vex
.ll
= (*codep
>> 5) & 3;
9312 vex
.b
= (*codep
& 0x10) != 0;
9314 vex
.v
= *codep
& 0x8;
9315 vex
.mask_register_specifier
= *codep
& 0x7;
9316 vex
.zeroing
= *codep
& 0x80;
9318 if (address_mode
!= mode_64bit
)
9320 /* In 16/32-bit mode silently ignore following bits. */
9329 dp
= &evex_table
[vex_table_index
][vindex
];
9331 FETCH_DATA (info
, codep
+ 1);
9332 modrm
.mod
= (*codep
>> 6) & 3;
9333 modrm
.reg
= (*codep
>> 3) & 7;
9334 modrm
.rm
= *codep
& 7;
9336 /* Set vector length. */
9337 if (modrm
.mod
== 3 && vex
.b
)
9366 if (dp
->name
!= NULL
)
9369 return get_valid_dis386 (dp
, info
);
9373 get_sib (disassemble_info
*info
, int sizeflag
)
9375 /* If modrm.mod == 3, operand must be register. */
9377 && ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
9381 FETCH_DATA (info
, codep
+ 2);
9382 sib
.index
= (codep
[1] >> 3) & 7;
9383 sib
.scale
= (codep
[1] >> 6) & 3;
9384 sib
.base
= codep
[1] & 7;
9389 print_insn (bfd_vma pc
, disassemble_info
*info
)
9391 const struct dis386
*dp
;
9393 char *op_txt
[MAX_OPERANDS
];
9395 int sizeflag
, orig_sizeflag
;
9397 struct dis_private priv
;
9400 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
9401 if ((info
->mach
& bfd_mach_i386_i386
) != 0)
9402 address_mode
= mode_32bit
;
9403 else if (info
->mach
== bfd_mach_i386_i8086
)
9405 address_mode
= mode_16bit
;
9406 priv
.orig_sizeflag
= 0;
9409 address_mode
= mode_64bit
;
9411 if (intel_syntax
== (char) -1)
9412 intel_syntax
= (info
->mach
& bfd_mach_i386_intel_syntax
) != 0;
9414 for (p
= info
->disassembler_options
; p
!= NULL
; )
9416 if (CONST_STRNEQ (p
, "amd64"))
9418 else if (CONST_STRNEQ (p
, "intel64"))
9420 else if (CONST_STRNEQ (p
, "x86-64"))
9422 address_mode
= mode_64bit
;
9423 priv
.orig_sizeflag
|= AFLAG
| DFLAG
;
9425 else if (CONST_STRNEQ (p
, "i386"))
9427 address_mode
= mode_32bit
;
9428 priv
.orig_sizeflag
|= AFLAG
| DFLAG
;
9430 else if (CONST_STRNEQ (p
, "i8086"))
9432 address_mode
= mode_16bit
;
9433 priv
.orig_sizeflag
&= ~(AFLAG
| DFLAG
);
9435 else if (CONST_STRNEQ (p
, "intel"))
9438 if (CONST_STRNEQ (p
+ 5, "-mnemonic"))
9441 else if (CONST_STRNEQ (p
, "att"))
9444 if (CONST_STRNEQ (p
+ 3, "-mnemonic"))
9447 else if (CONST_STRNEQ (p
, "addr"))
9449 if (address_mode
== mode_64bit
)
9451 if (p
[4] == '3' && p
[5] == '2')
9452 priv
.orig_sizeflag
&= ~AFLAG
;
9453 else if (p
[4] == '6' && p
[5] == '4')
9454 priv
.orig_sizeflag
|= AFLAG
;
9458 if (p
[4] == '1' && p
[5] == '6')
9459 priv
.orig_sizeflag
&= ~AFLAG
;
9460 else if (p
[4] == '3' && p
[5] == '2')
9461 priv
.orig_sizeflag
|= AFLAG
;
9464 else if (CONST_STRNEQ (p
, "data"))
9466 if (p
[4] == '1' && p
[5] == '6')
9467 priv
.orig_sizeflag
&= ~DFLAG
;
9468 else if (p
[4] == '3' && p
[5] == '2')
9469 priv
.orig_sizeflag
|= DFLAG
;
9471 else if (CONST_STRNEQ (p
, "suffix"))
9472 priv
.orig_sizeflag
|= SUFFIX_ALWAYS
;
9474 p
= strchr (p
, ',');
9479 if (address_mode
== mode_64bit
&& sizeof (bfd_vma
) < 8)
9481 (*info
->fprintf_func
) (info
->stream
,
9482 _("64-bit address is disabled"));
9488 names64
= intel_names64
;
9489 names32
= intel_names32
;
9490 names16
= intel_names16
;
9491 names8
= intel_names8
;
9492 names8rex
= intel_names8rex
;
9493 names_seg
= intel_names_seg
;
9494 names_mm
= intel_names_mm
;
9495 names_bnd
= intel_names_bnd
;
9496 names_xmm
= intel_names_xmm
;
9497 names_ymm
= intel_names_ymm
;
9498 names_zmm
= intel_names_zmm
;
9499 names_tmm
= intel_names_tmm
;
9500 index64
= intel_index64
;
9501 index32
= intel_index32
;
9502 names_mask
= intel_names_mask
;
9503 index16
= intel_index16
;
9506 separator_char
= '+';
9511 names64
= att_names64
;
9512 names32
= att_names32
;
9513 names16
= att_names16
;
9514 names8
= att_names8
;
9515 names8rex
= att_names8rex
;
9516 names_seg
= att_names_seg
;
9517 names_mm
= att_names_mm
;
9518 names_bnd
= att_names_bnd
;
9519 names_xmm
= att_names_xmm
;
9520 names_ymm
= att_names_ymm
;
9521 names_zmm
= att_names_zmm
;
9522 names_tmm
= att_names_tmm
;
9523 index64
= att_index64
;
9524 index32
= att_index32
;
9525 names_mask
= att_names_mask
;
9526 index16
= att_index16
;
9529 separator_char
= ',';
9533 /* The output looks better if we put 7 bytes on a line, since that
9534 puts most long word instructions on a single line. Use 8 bytes
9536 if ((info
->mach
& bfd_mach_l1om
) != 0)
9537 info
->bytes_per_line
= 8;
9539 info
->bytes_per_line
= 7;
9541 info
->private_data
= &priv
;
9542 priv
.max_fetched
= priv
.the_buffer
;
9543 priv
.insn_start
= pc
;
9546 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
9554 start_codep
= priv
.the_buffer
;
9555 codep
= priv
.the_buffer
;
9557 if (OPCODES_SIGSETJMP (priv
.bailout
) != 0)
9561 /* Getting here means we tried for data but didn't get it. That
9562 means we have an incomplete instruction of some sort. Just
9563 print the first byte as a prefix or a .byte pseudo-op. */
9564 if (codep
> priv
.the_buffer
)
9566 name
= prefix_name (priv
.the_buffer
[0], priv
.orig_sizeflag
);
9568 (*info
->fprintf_func
) (info
->stream
, "%s", name
);
9571 /* Just print the first byte as a .byte instruction. */
9572 (*info
->fprintf_func
) (info
->stream
, ".byte 0x%x",
9573 (unsigned int) priv
.the_buffer
[0]);
9583 sizeflag
= priv
.orig_sizeflag
;
9585 if (!ckprefix () || rex_used
)
9587 /* Too many prefixes or unused REX prefixes. */
9589 i
< (int) ARRAY_SIZE (all_prefixes
) && all_prefixes
[i
];
9591 (*info
->fprintf_func
) (info
->stream
, "%s%s",
9593 prefix_name (all_prefixes
[i
], sizeflag
));
9599 FETCH_DATA (info
, codep
+ 1);
9600 two_source_ops
= (*codep
== 0x62) || (*codep
== 0xc8);
9602 if (((prefixes
& PREFIX_FWAIT
)
9603 && ((*codep
< 0xd8) || (*codep
> 0xdf))))
9605 /* Handle prefixes before fwait. */
9606 for (i
= 0; i
< fwait_prefix
&& all_prefixes
[i
];
9608 (*info
->fprintf_func
) (info
->stream
, "%s ",
9609 prefix_name (all_prefixes
[i
], sizeflag
));
9610 (*info
->fprintf_func
) (info
->stream
, "fwait");
9616 unsigned char threebyte
;
9619 FETCH_DATA (info
, codep
+ 1);
9621 dp
= &dis386_twobyte
[threebyte
];
9622 need_modrm
= twobyte_has_modrm
[threebyte
];
9627 dp
= &dis386
[*codep
];
9628 need_modrm
= onebyte_has_modrm
[*codep
];
9632 /* Save sizeflag for printing the extra prefixes later before updating
9633 it for mnemonic and operand processing. The prefix names depend
9634 only on the address mode. */
9635 orig_sizeflag
= sizeflag
;
9636 if (prefixes
& PREFIX_ADDR
)
9638 if ((prefixes
& PREFIX_DATA
))
9644 FETCH_DATA (info
, codep
+ 1);
9645 modrm
.mod
= (*codep
>> 6) & 3;
9646 modrm
.reg
= (*codep
>> 3) & 7;
9647 modrm
.rm
= *codep
& 7;
9650 memset (&modrm
, 0, sizeof (modrm
));
9653 memset (&vex
, 0, sizeof (vex
));
9655 if (dp
->name
== NULL
&& dp
->op
[0].bytemode
== FLOATCODE
)
9657 get_sib (info
, sizeflag
);
9662 dp
= get_valid_dis386 (dp
, info
);
9663 if (dp
!= NULL
&& putop (dp
->name
, sizeflag
) == 0)
9665 get_sib (info
, sizeflag
);
9666 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
9669 op_ad
= MAX_OPERANDS
- 1 - i
;
9671 (*dp
->op
[i
].rtn
) (dp
->op
[i
].bytemode
, sizeflag
);
9672 /* For EVEX instruction after the last operand masking
9673 should be printed. */
9674 if (i
== 0 && vex
.evex
)
9676 /* Don't print {%k0}. */
9677 if (vex
.mask_register_specifier
)
9680 oappend (names_mask
[vex
.mask_register_specifier
]);
9690 /* Clear instruction information. */
9693 the_info
->insn_info_valid
= 0;
9694 the_info
->branch_delay_insns
= 0;
9695 the_info
->data_size
= 0;
9696 the_info
->insn_type
= dis_noninsn
;
9697 the_info
->target
= 0;
9698 the_info
->target2
= 0;
9701 /* Reset jump operation indicator. */
9705 int jump_detection
= 0;
9707 /* Extract flags. */
9708 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
9710 if ((dp
->op
[i
].rtn
== OP_J
)
9711 || (dp
->op
[i
].rtn
== OP_indirE
))
9712 jump_detection
|= 1;
9713 else if ((dp
->op
[i
].rtn
== BND_Fixup
)
9714 || (!dp
->op
[i
].rtn
&& !dp
->op
[i
].bytemode
))
9715 jump_detection
|= 2;
9716 else if ((dp
->op
[i
].bytemode
== cond_jump_mode
)
9717 || (dp
->op
[i
].bytemode
== loop_jcxz_mode
))
9718 jump_detection
|= 4;
9721 /* Determine if this is a jump or branch. */
9722 if ((jump_detection
& 0x3) == 0x3)
9725 if (jump_detection
& 0x4)
9726 the_info
->insn_type
= dis_condbranch
;
9728 the_info
->insn_type
=
9729 (dp
->name
&& !strncmp(dp
->name
, "call", 4))
9730 ? dis_jsr
: dis_branch
;
9734 /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
9735 are all 0s in inverted form. */
9736 if (need_vex
&& vex
.register_specifier
!= 0)
9738 (*info
->fprintf_func
) (info
->stream
, "(bad)");
9739 return end_codep
- priv
.the_buffer
;
9742 switch (dp
->prefix_requirement
)
9745 /* If only the data prefix is marked as mandatory, its absence renders
9746 the encoding invalid. Most other PREFIX_OPCODE rules still apply. */
9747 if (need_vex
? !vex
.prefix
: !(prefixes
& PREFIX_DATA
))
9749 (*info
->fprintf_func
) (info
->stream
, "(bad)");
9750 return end_codep
- priv
.the_buffer
;
9752 used_prefixes
|= PREFIX_DATA
;
9755 /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
9756 unused, opcode is invalid. Since the PREFIX_DATA prefix may be
9757 used by putop and MMX/SSE operand and may be overridden by the
9758 PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
9761 ? vex
.prefix
== REPE_PREFIX_OPCODE
9762 || vex
.prefix
== REPNE_PREFIX_OPCODE
9764 & (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0)
9766 & (PREFIX_REPZ
| PREFIX_REPNZ
)) == 0)
9768 ? vex
.prefix
== DATA_PREFIX_OPCODE
9770 & (PREFIX_REPZ
| PREFIX_REPNZ
| PREFIX_DATA
))
9772 && (used_prefixes
& PREFIX_DATA
) == 0))
9773 || (vex
.evex
&& dp
->prefix_requirement
!= PREFIX_DATA
9774 && !vex
.w
!= !(used_prefixes
& PREFIX_DATA
)))
9776 (*info
->fprintf_func
) (info
->stream
, "(bad)");
9777 return end_codep
- priv
.the_buffer
;
9781 case PREFIX_IGNORED
:
9782 /* Zap data size and rep prefixes from used_prefixes and reinstate their
9783 origins in all_prefixes. */
9784 used_prefixes
&= ~PREFIX_OPCODE
;
9785 if (last_data_prefix
>= 0)
9786 all_prefixes
[last_repz_prefix
] = 0x66;
9787 if (last_repz_prefix
>= 0)
9788 all_prefixes
[last_repz_prefix
] = 0xf3;
9789 if (last_repnz_prefix
>= 0)
9790 all_prefixes
[last_repnz_prefix
] = 0xf2;
9794 /* Check if the REX prefix is used. */
9795 if ((rex
^ rex_used
) == 0 && !need_vex
&& last_rex_prefix
>= 0)
9796 all_prefixes
[last_rex_prefix
] = 0;
9798 /* Check if the SEG prefix is used. */
9799 if ((prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
| PREFIX_ES
9800 | PREFIX_FS
| PREFIX_GS
)) != 0
9801 && (used_prefixes
& active_seg_prefix
) != 0)
9802 all_prefixes
[last_seg_prefix
] = 0;
9804 /* Check if the ADDR prefix is used. */
9805 if ((prefixes
& PREFIX_ADDR
) != 0
9806 && (used_prefixes
& PREFIX_ADDR
) != 0)
9807 all_prefixes
[last_addr_prefix
] = 0;
9809 /* Check if the DATA prefix is used. */
9810 if ((prefixes
& PREFIX_DATA
) != 0
9811 && (used_prefixes
& PREFIX_DATA
) != 0
9813 all_prefixes
[last_data_prefix
] = 0;
9815 /* Print the extra prefixes. */
9817 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
9818 if (all_prefixes
[i
])
9821 name
= prefix_name (all_prefixes
[i
], orig_sizeflag
);
9824 prefix_length
+= strlen (name
) + 1;
9825 (*info
->fprintf_func
) (info
->stream
, "%s ", name
);
9828 /* Check maximum code length. */
9829 if ((codep
- start_codep
) > MAX_CODE_LENGTH
)
9831 (*info
->fprintf_func
) (info
->stream
, "(bad)");
9832 return MAX_CODE_LENGTH
;
9835 obufp
= mnemonicendp
;
9836 for (i
= strlen (obuf
) + prefix_length
; i
< 6; i
++)
9839 (*info
->fprintf_func
) (info
->stream
, "%s", obuf
);
9841 /* The enter and bound instructions are printed with operands in the same
9842 order as the intel book; everything else is printed in reverse order. */
9843 if (intel_syntax
|| two_source_ops
)
9847 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
9848 op_txt
[i
] = op_out
[i
];
9850 if (intel_syntax
&& dp
&& dp
->op
[2].rtn
== OP_Rounding
9851 && dp
->op
[3].rtn
== OP_E
&& dp
->op
[4].rtn
== NULL
)
9853 op_txt
[2] = op_out
[3];
9854 op_txt
[3] = op_out
[2];
9857 for (i
= 0; i
< (MAX_OPERANDS
>> 1); ++i
)
9859 op_ad
= op_index
[i
];
9860 op_index
[i
] = op_index
[MAX_OPERANDS
- 1 - i
];
9861 op_index
[MAX_OPERANDS
- 1 - i
] = op_ad
;
9862 riprel
= op_riprel
[i
];
9863 op_riprel
[i
] = op_riprel
[MAX_OPERANDS
- 1 - i
];
9864 op_riprel
[MAX_OPERANDS
- 1 - i
] = riprel
;
9869 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
9870 op_txt
[MAX_OPERANDS
- 1 - i
] = op_out
[i
];
9874 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
9878 (*info
->fprintf_func
) (info
->stream
, ",");
9879 if (op_index
[i
] != -1 && !op_riprel
[i
])
9881 bfd_vma target
= (bfd_vma
) op_address
[op_index
[i
]];
9883 if (the_info
&& op_is_jump
)
9885 the_info
->insn_info_valid
= 1;
9886 the_info
->branch_delay_insns
= 0;
9887 the_info
->data_size
= 0;
9888 the_info
->target
= target
;
9889 the_info
->target2
= 0;
9891 (*info
->print_address_func
) (target
, info
);
9894 (*info
->fprintf_func
) (info
->stream
, "%s", op_txt
[i
]);
9898 for (i
= 0; i
< MAX_OPERANDS
; i
++)
9899 if (op_index
[i
] != -1 && op_riprel
[i
])
9901 (*info
->fprintf_func
) (info
->stream
, " # ");
9902 (*info
->print_address_func
) ((bfd_vma
) (start_pc
+ (codep
- start_codep
)
9903 + op_address
[op_index
[i
]]), info
);
9906 return codep
- priv
.the_buffer
;
9909 static const char *float_mem
[] = {
9984 static const unsigned char float_mem_mode
[] = {
10059 #define ST { OP_ST, 0 }
10060 #define STi { OP_STi, 0 }
10062 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
10063 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
10064 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
10065 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
10066 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
10067 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
10068 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
10069 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
10070 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
10072 static const struct dis386 float_reg
[][8] = {
10075 { "fadd", { ST
, STi
}, 0 },
10076 { "fmul", { ST
, STi
}, 0 },
10077 { "fcom", { STi
}, 0 },
10078 { "fcomp", { STi
}, 0 },
10079 { "fsub", { ST
, STi
}, 0 },
10080 { "fsubr", { ST
, STi
}, 0 },
10081 { "fdiv", { ST
, STi
}, 0 },
10082 { "fdivr", { ST
, STi
}, 0 },
10086 { "fld", { STi
}, 0 },
10087 { "fxch", { STi
}, 0 },
10097 { "fcmovb", { ST
, STi
}, 0 },
10098 { "fcmove", { ST
, STi
}, 0 },
10099 { "fcmovbe",{ ST
, STi
}, 0 },
10100 { "fcmovu", { ST
, STi
}, 0 },
10108 { "fcmovnb",{ ST
, STi
}, 0 },
10109 { "fcmovne",{ ST
, STi
}, 0 },
10110 { "fcmovnbe",{ ST
, STi
}, 0 },
10111 { "fcmovnu",{ ST
, STi
}, 0 },
10113 { "fucomi", { ST
, STi
}, 0 },
10114 { "fcomi", { ST
, STi
}, 0 },
10119 { "fadd", { STi
, ST
}, 0 },
10120 { "fmul", { STi
, ST
}, 0 },
10123 { "fsub{!M|r}", { STi
, ST
}, 0 },
10124 { "fsub{M|}", { STi
, ST
}, 0 },
10125 { "fdiv{!M|r}", { STi
, ST
}, 0 },
10126 { "fdiv{M|}", { STi
, ST
}, 0 },
10130 { "ffree", { STi
}, 0 },
10132 { "fst", { STi
}, 0 },
10133 { "fstp", { STi
}, 0 },
10134 { "fucom", { STi
}, 0 },
10135 { "fucomp", { STi
}, 0 },
10141 { "faddp", { STi
, ST
}, 0 },
10142 { "fmulp", { STi
, ST
}, 0 },
10145 { "fsub{!M|r}p", { STi
, ST
}, 0 },
10146 { "fsub{M|}p", { STi
, ST
}, 0 },
10147 { "fdiv{!M|r}p", { STi
, ST
}, 0 },
10148 { "fdiv{M|}p", { STi
, ST
}, 0 },
10152 { "ffreep", { STi
}, 0 },
10157 { "fucomip", { ST
, STi
}, 0 },
10158 { "fcomip", { ST
, STi
}, 0 },
10163 static char *fgrps
[][8] = {
10166 "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10171 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10176 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
10181 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
10186 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
10191 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
10196 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10201 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
10202 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
10207 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10212 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10217 swap_operand (void)
10219 mnemonicendp
[0] = '.';
10220 mnemonicendp
[1] = 's';
10225 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED
,
10226 int sizeflag ATTRIBUTE_UNUSED
)
10228 /* Skip mod/rm byte. */
10234 dofloat (int sizeflag
)
10236 const struct dis386
*dp
;
10237 unsigned char floatop
;
10239 floatop
= codep
[-1];
10241 if (modrm
.mod
!= 3)
10243 int fp_indx
= (floatop
- 0xd8) * 8 + modrm
.reg
;
10245 putop (float_mem
[fp_indx
], sizeflag
);
10248 OP_E (float_mem_mode
[fp_indx
], sizeflag
);
10251 /* Skip mod/rm byte. */
10255 dp
= &float_reg
[floatop
- 0xd8][modrm
.reg
];
10256 if (dp
->name
== NULL
)
10258 putop (fgrps
[dp
->op
[0].bytemode
][modrm
.rm
], sizeflag
);
10260 /* Instruction fnstsw is only one with strange arg. */
10261 if (floatop
== 0xdf && codep
[-1] == 0xe0)
10262 strcpy (op_out
[0], names16
[0]);
10266 putop (dp
->name
, sizeflag
);
10271 (*dp
->op
[0].rtn
) (dp
->op
[0].bytemode
, sizeflag
);
10276 (*dp
->op
[1].rtn
) (dp
->op
[1].bytemode
, sizeflag
);
10280 /* Like oappend (below), but S is a string starting with '%'.
10281 In Intel syntax, the '%' is elided. */
10283 oappend_maybe_intel (const char *s
)
10285 oappend (s
+ intel_syntax
);
10289 OP_ST (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
10291 oappend_maybe_intel ("%st");
10295 OP_STi (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
10297 sprintf (scratchbuf
, "%%st(%d)", modrm
.rm
);
10298 oappend_maybe_intel (scratchbuf
);
10301 /* Capital letters in template are macros. */
10303 putop (const char *in_template
, int sizeflag
)
10308 unsigned int l
= 0, len
= 0;
10311 for (p
= in_template
; *p
; p
++)
10315 if (l
>= sizeof (last
) || !ISUPPER (*p
))
10334 while (*++p
!= '|')
10335 if (*p
== '}' || *p
== '\0')
10341 while (*++p
!= '}')
10353 if ((need_modrm
&& modrm
.mod
!= 3)
10354 || (sizeflag
& SUFFIX_ALWAYS
))
10363 if (sizeflag
& SUFFIX_ALWAYS
)
10366 else if (l
== 1 && last
[0] == 'L')
10368 if (address_mode
== mode_64bit
10369 && !(prefixes
& PREFIX_ADDR
))
10382 if (intel_syntax
&& !alt
)
10384 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
10386 if (sizeflag
& DFLAG
)
10387 *obufp
++ = intel_syntax
? 'd' : 'l';
10389 *obufp
++ = intel_syntax
? 'w' : 's';
10390 used_prefixes
|= (prefixes
& PREFIX_DATA
);
10394 if (intel_syntax
|| !(sizeflag
& SUFFIX_ALWAYS
))
10397 if (modrm
.mod
== 3)
10403 if (sizeflag
& DFLAG
)
10404 *obufp
++ = intel_syntax
? 'd' : 'l';
10407 used_prefixes
|= (prefixes
& PREFIX_DATA
);
10413 case 'E': /* For jcxz/jecxz */
10414 if (address_mode
== mode_64bit
)
10416 if (sizeflag
& AFLAG
)
10422 if (sizeflag
& AFLAG
)
10424 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
10429 if ((prefixes
& PREFIX_ADDR
) || (sizeflag
& SUFFIX_ALWAYS
))
10431 if (sizeflag
& AFLAG
)
10432 *obufp
++ = address_mode
== mode_64bit
? 'q' : 'l';
10434 *obufp
++ = address_mode
== mode_64bit
? 'l' : 'w';
10435 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
10439 if (intel_syntax
|| (obufp
[-1] != 's' && !(sizeflag
& SUFFIX_ALWAYS
)))
10441 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
10445 if (!(rex
& REX_W
))
10446 used_prefixes
|= (prefixes
& PREFIX_DATA
);
10451 if ((prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_CS
10452 || (prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_DS
)
10454 used_prefixes
|= prefixes
& (PREFIX_CS
| PREFIX_DS
);
10458 /* Set active_seg_prefix even if not set in 64-bit mode
10459 because here it is a valid branch hint. */
10460 if (prefixes
& PREFIX_DS
)
10462 active_seg_prefix
= PREFIX_DS
;
10467 active_seg_prefix
= PREFIX_CS
;
10482 if (intel_mnemonic
!= cond
)
10486 if ((prefixes
& PREFIX_FWAIT
) == 0)
10489 used_prefixes
|= PREFIX_FWAIT
;
10495 else if (intel_syntax
&& (sizeflag
& DFLAG
))
10499 if (!(rex
& REX_W
))
10500 used_prefixes
|= (prefixes
& PREFIX_DATA
);
10503 if (address_mode
== mode_64bit
10504 && (isa64
== intel64
|| (rex
& REX_W
)
10505 || !(prefixes
& PREFIX_DATA
)))
10507 if (sizeflag
& SUFFIX_ALWAYS
)
10511 /* Fall through. */
10515 if ((modrm
.mod
== 3 || !cond
)
10516 && !(sizeflag
& SUFFIX_ALWAYS
))
10518 /* Fall through. */
10520 if ((!(rex
& REX_W
) && (prefixes
& PREFIX_DATA
))
10521 || ((sizeflag
& SUFFIX_ALWAYS
)
10522 && address_mode
!= mode_64bit
))
10524 *obufp
++ = (sizeflag
& DFLAG
) ?
10525 intel_syntax
? 'd' : 'l' : 'w';
10526 used_prefixes
|= (prefixes
& PREFIX_DATA
);
10528 else if (sizeflag
& SUFFIX_ALWAYS
)
10531 else if (l
== 1 && last
[0] == 'L')
10533 if ((prefixes
& PREFIX_DATA
)
10535 || (sizeflag
& SUFFIX_ALWAYS
))
10542 if (sizeflag
& DFLAG
)
10543 *obufp
++ = intel_syntax
? 'd' : 'l';
10546 used_prefixes
|= (prefixes
& PREFIX_DATA
);
10556 if (intel_syntax
&& !alt
)
10559 if ((need_modrm
&& modrm
.mod
!= 3)
10560 || (sizeflag
& SUFFIX_ALWAYS
))
10566 if (sizeflag
& DFLAG
)
10567 *obufp
++ = intel_syntax
? 'd' : 'l';
10570 used_prefixes
|= (prefixes
& PREFIX_DATA
);
10574 else if (l
== 1 && last
[0] == 'D')
10575 *obufp
++ = vex
.w
? 'q' : 'd';
10576 else if (l
== 1 && last
[0] == 'L')
10578 if (cond
? modrm
.mod
== 3 && !(sizeflag
& SUFFIX_ALWAYS
)
10579 : address_mode
!= mode_64bit
)
10586 else if((address_mode
== mode_64bit
&& cond
)
10587 || (sizeflag
& SUFFIX_ALWAYS
))
10588 *obufp
++ = intel_syntax
? 'd' : 'l';
10597 else if (sizeflag
& DFLAG
)
10606 if (intel_syntax
&& !p
[1]
10607 && ((rex
& REX_W
) || (sizeflag
& DFLAG
)))
10609 if (!(rex
& REX_W
))
10610 used_prefixes
|= (prefixes
& PREFIX_DATA
);
10618 if (sizeflag
& SUFFIX_ALWAYS
)
10624 if (sizeflag
& DFLAG
)
10628 used_prefixes
|= (prefixes
& PREFIX_DATA
);
10632 else if (l
== 1 && last
[0] == 'L')
10634 if (address_mode
== mode_64bit
10635 && !(prefixes
& PREFIX_ADDR
))
10651 && (last
[0] == 'L' || last
[0] == 'X'))
10653 if (last
[0] == 'X')
10661 else if (rex
& REX_W
)
10674 /* operand size flag for cwtl, cbtw */
10683 else if (sizeflag
& DFLAG
)
10687 if (!(rex
& REX_W
))
10688 used_prefixes
|= (prefixes
& PREFIX_DATA
);
10694 if (last
[0] == 'X')
10695 *obufp
++ = vex
.w
? 'd': 's';
10696 else if (last
[0] == 'B')
10697 *obufp
++ = vex
.w
? 'w': 'b';
10708 ? vex
.prefix
== DATA_PREFIX_OPCODE
10709 : prefixes
& PREFIX_DATA
)
10712 used_prefixes
|= PREFIX_DATA
;
10718 if (l
== 1 && last
[0] == 'X')
10723 || ((modrm
.mod
== 3 || vex
.b
) && !(sizeflag
& SUFFIX_ALWAYS
)))
10725 switch (vex
.length
)
10745 /* These insns ignore ModR/M.mod: Force it to 3 for OP_E(). */
10747 if (!intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
10748 *obufp
++ = address_mode
== mode_64bit
? 'q' : 'l';
10750 else if (l
== 1 && last
[0] == 'X')
10755 || ((modrm
.mod
== 3 || vex
.b
) && !(sizeflag
& SUFFIX_ALWAYS
)))
10757 switch (vex
.length
)
10778 if (isa64
== intel64
&& (rex
& REX_W
))
10784 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
10786 if (sizeflag
& DFLAG
)
10790 used_prefixes
|= (prefixes
& PREFIX_DATA
);
10799 mnemonicendp
= obufp
;
10804 oappend (const char *s
)
10806 obufp
= stpcpy (obufp
, s
);
10812 /* Only print the active segment register. */
10813 if (!active_seg_prefix
)
10816 used_prefixes
|= active_seg_prefix
;
10817 switch (active_seg_prefix
)
10820 oappend_maybe_intel ("%cs:");
10823 oappend_maybe_intel ("%ds:");
10826 oappend_maybe_intel ("%ss:");
10829 oappend_maybe_intel ("%es:");
10832 oappend_maybe_intel ("%fs:");
10835 oappend_maybe_intel ("%gs:");
10843 OP_indirE (int bytemode
, int sizeflag
)
10847 OP_E (bytemode
, sizeflag
);
10851 print_operand_value (char *buf
, int hex
, bfd_vma disp
)
10853 if (address_mode
== mode_64bit
)
10861 sprintf_vma (tmp
, disp
);
10862 for (i
= 0; tmp
[i
] == '0' && tmp
[i
+ 1]; i
++);
10863 strcpy (buf
+ 2, tmp
+ i
);
10867 bfd_signed_vma v
= disp
;
10874 /* Check for possible overflow on 0x8000000000000000. */
10877 strcpy (buf
, "9223372036854775808");
10891 tmp
[28 - i
] = (v
% 10) + '0';
10895 strcpy (buf
, tmp
+ 29 - i
);
10901 sprintf (buf
, "0x%x", (unsigned int) disp
);
10903 sprintf (buf
, "%d", (int) disp
);
10907 /* Put DISP in BUF as signed hex number. */
10910 print_displacement (char *buf
, bfd_vma disp
)
10912 bfd_signed_vma val
= disp
;
10921 /* Check for possible overflow. */
10924 switch (address_mode
)
10927 strcpy (buf
+ j
, "0x8000000000000000");
10930 strcpy (buf
+ j
, "0x80000000");
10933 strcpy (buf
+ j
, "0x8000");
10943 sprintf_vma (tmp
, (bfd_vma
) val
);
10944 for (i
= 0; tmp
[i
] == '0'; i
++)
10946 if (tmp
[i
] == '\0')
10948 strcpy (buf
+ j
, tmp
+ i
);
10952 intel_operand_size (int bytemode
, int sizeflag
)
10955 && (bytemode
== x_mode
10956 || bytemode
== evex_half_bcst_xmmq_mode
))
10959 oappend ("QWORD PTR ");
10961 oappend ("DWORD PTR ");
10970 oappend ("BYTE PTR ");
10975 oappend ("WORD PTR ");
10978 if (address_mode
== mode_64bit
&& isa64
== intel64
)
10980 oappend ("QWORD PTR ");
10983 /* Fall through. */
10985 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
10987 oappend ("QWORD PTR ");
10990 /* Fall through. */
10996 oappend ("QWORD PTR ");
10997 else if (bytemode
== dq_mode
)
10998 oappend ("DWORD PTR ");
11001 if (sizeflag
& DFLAG
)
11002 oappend ("DWORD PTR ");
11004 oappend ("WORD PTR ");
11005 used_prefixes
|= (prefixes
& PREFIX_DATA
);
11009 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
11011 oappend ("WORD PTR ");
11012 if (!(rex
& REX_W
))
11013 used_prefixes
|= (prefixes
& PREFIX_DATA
);
11016 if (sizeflag
& DFLAG
)
11017 oappend ("QWORD PTR ");
11019 oappend ("DWORD PTR ");
11020 used_prefixes
|= (prefixes
& PREFIX_DATA
);
11023 if (!(sizeflag
& DFLAG
) && isa64
== intel64
)
11024 oappend ("WORD PTR ");
11026 oappend ("DWORD PTR ");
11027 used_prefixes
|= (prefixes
& PREFIX_DATA
);
11032 oappend ("DWORD PTR ");
11036 oappend ("QWORD PTR ");
11039 if (address_mode
== mode_64bit
)
11040 oappend ("QWORD PTR ");
11042 oappend ("DWORD PTR ");
11045 if (sizeflag
& DFLAG
)
11046 oappend ("FWORD PTR ");
11048 oappend ("DWORD PTR ");
11049 used_prefixes
|= (prefixes
& PREFIX_DATA
);
11052 oappend ("TBYTE PTR ");
11056 case evex_x_gscat_mode
:
11057 case evex_x_nobcst_mode
:
11061 switch (vex
.length
)
11064 oappend ("XMMWORD PTR ");
11067 oappend ("YMMWORD PTR ");
11070 oappend ("ZMMWORD PTR ");
11077 oappend ("XMMWORD PTR ");
11080 oappend ("XMMWORD PTR ");
11083 oappend ("YMMWORD PTR ");
11086 case evex_half_bcst_xmmq_mode
:
11090 switch (vex
.length
)
11093 oappend ("QWORD PTR ");
11096 oappend ("XMMWORD PTR ");
11099 oappend ("YMMWORD PTR ");
11109 switch (vex
.length
)
11114 oappend ("BYTE PTR ");
11124 switch (vex
.length
)
11129 oappend ("WORD PTR ");
11139 switch (vex
.length
)
11144 oappend ("DWORD PTR ");
11154 switch (vex
.length
)
11159 oappend ("QWORD PTR ");
11169 switch (vex
.length
)
11172 oappend ("WORD PTR ");
11175 oappend ("DWORD PTR ");
11178 oappend ("QWORD PTR ");
11188 switch (vex
.length
)
11191 oappend ("DWORD PTR ");
11194 oappend ("QWORD PTR ");
11197 oappend ("XMMWORD PTR ");
11207 switch (vex
.length
)
11210 oappend ("QWORD PTR ");
11213 oappend ("YMMWORD PTR ");
11216 oappend ("ZMMWORD PTR ");
11226 switch (vex
.length
)
11230 oappend ("XMMWORD PTR ");
11237 oappend ("OWORD PTR ");
11239 case vex_scalar_w_dq_mode
:
11244 oappend ("QWORD PTR ");
11246 oappend ("DWORD PTR ");
11248 case vex_vsib_d_w_dq_mode
:
11249 case vex_vsib_q_w_dq_mode
:
11254 oappend ("QWORD PTR ");
11256 oappend ("DWORD PTR ");
11259 if (!need_vex
|| vex
.length
!= 128)
11262 oappend ("DWORD PTR ");
11264 oappend ("BYTE PTR ");
11270 oappend ("QWORD PTR ");
11272 oappend ("WORD PTR ");
11282 OP_E_register (int bytemode
, int sizeflag
)
11284 int reg
= modrm
.rm
;
11285 const char **names
;
11291 if ((sizeflag
& SUFFIX_ALWAYS
)
11292 && (bytemode
== b_swap_mode
11293 || bytemode
== bnd_swap_mode
11294 || bytemode
== v_swap_mode
))
11321 names
= address_mode
== mode_64bit
? names64
: names32
;
11324 case bnd_swap_mode
:
11333 if (address_mode
== mode_64bit
&& isa64
== intel64
)
11338 /* Fall through. */
11340 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
11346 /* Fall through. */
11356 else if (bytemode
!= v_mode
&& bytemode
!= v_swap_mode
)
11360 if (sizeflag
& DFLAG
)
11364 used_prefixes
|= (prefixes
& PREFIX_DATA
);
11368 if (!(sizeflag
& DFLAG
) && isa64
== intel64
)
11372 used_prefixes
|= (prefixes
& PREFIX_DATA
);
11375 names
= (address_mode
== mode_64bit
11376 ? names64
: names32
);
11377 if (!(prefixes
& PREFIX_ADDR
))
11378 names
= (address_mode
== mode_16bit
11379 ? names16
: names
);
11382 /* Remove "addr16/addr32". */
11383 all_prefixes
[last_addr_prefix
] = 0;
11384 names
= (address_mode
!= mode_32bit
11385 ? names32
: names16
);
11386 used_prefixes
|= PREFIX_ADDR
;
11396 names
= names_mask
;
11401 oappend (INTERNAL_DISASSEMBLER_ERROR
);
11404 oappend (names
[reg
]);
11408 OP_E_memory (int bytemode
, int sizeflag
)
11411 int add
= (rex
& REX_B
) ? 8 : 0;
11417 /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */
11419 && bytemode
!= x_mode
11420 && bytemode
!= evex_half_bcst_xmmq_mode
)
11438 if (address_mode
!= mode_64bit
)
11448 case vex_scalar_w_dq_mode
:
11449 case vex_vsib_d_w_dq_mode
:
11450 case vex_vsib_q_w_dq_mode
:
11451 case evex_x_gscat_mode
:
11452 shift
= vex
.w
? 3 : 2;
11455 case evex_half_bcst_xmmq_mode
:
11458 shift
= vex
.w
? 3 : 2;
11461 /* Fall through. */
11466 case evex_x_nobcst_mode
:
11468 switch (vex
.length
)
11482 /* Make necessary corrections to shift for modes that need it. */
11483 if (bytemode
== xmmq_mode
11484 || bytemode
== evex_half_bcst_xmmq_mode
11485 || (bytemode
== ymmq_mode
&& vex
.length
== 128))
11487 else if (bytemode
== xmmqd_mode
)
11489 else if (bytemode
== xmmdw_mode
)
11504 shift
= vex
.w
? 1 : 0;
11515 intel_operand_size (bytemode
, sizeflag
);
11518 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
11520 /* 32/64 bit address mode */
11530 int addr32flag
= !((sizeflag
& AFLAG
)
11531 || bytemode
== v_bnd_mode
11532 || bytemode
== v_bndmk_mode
11533 || bytemode
== bnd_mode
11534 || bytemode
== bnd_swap_mode
);
11535 const char **indexes64
= names64
;
11536 const char **indexes32
= names32
;
11546 vindex
= sib
.index
;
11552 case vex_vsib_d_w_dq_mode
:
11553 case vex_vsib_q_w_dq_mode
:
11563 switch (vex
.length
)
11566 indexes64
= indexes32
= names_xmm
;
11570 || bytemode
== vex_vsib_q_w_dq_mode
)
11571 indexes64
= indexes32
= names_ymm
;
11573 indexes64
= indexes32
= names_xmm
;
11577 || bytemode
== vex_vsib_q_w_dq_mode
)
11578 indexes64
= indexes32
= names_zmm
;
11580 indexes64
= indexes32
= names_ymm
;
11587 haveindex
= vindex
!= 4;
11596 /* mandatory non-vector SIB must have sib */
11597 if (bytemode
== vex_sibmem_mode
)
11603 rbase
= base
+ add
;
11611 if (address_mode
== mode_64bit
&& !havesib
)
11614 if (riprel
&& bytemode
== v_bndmk_mode
)
11622 FETCH_DATA (the_info
, codep
+ 1);
11624 if ((disp
& 0x80) != 0)
11626 if (vex
.evex
&& shift
> 0)
11639 && address_mode
!= mode_16bit
)
11641 if (address_mode
== mode_64bit
)
11645 /* Without base nor index registers, zero-extend the
11646 lower 32-bit displacement to 64 bits. */
11647 disp
= (unsigned int) disp
;
11654 /* In 32-bit mode, we need index register to tell [offset]
11655 from [eiz*1 + offset]. */
11660 havedisp
= (havebase
11662 || (havesib
&& (haveindex
|| scale
!= 0)));
11665 if (modrm
.mod
!= 0 || base
== 5)
11667 if (havedisp
|| riprel
)
11668 print_displacement (scratchbuf
, disp
);
11670 print_operand_value (scratchbuf
, 1, disp
);
11671 oappend (scratchbuf
);
11675 oappend (!addr32flag
? "(%rip)" : "(%eip)");
11679 if ((havebase
|| haveindex
|| needindex
|| needaddr32
|| riprel
)
11680 && (address_mode
!= mode_64bit
11681 || ((bytemode
!= v_bnd_mode
)
11682 && (bytemode
!= v_bndmk_mode
)
11683 && (bytemode
!= bnd_mode
)
11684 && (bytemode
!= bnd_swap_mode
))))
11685 used_prefixes
|= PREFIX_ADDR
;
11687 if (havedisp
|| (intel_syntax
&& riprel
))
11689 *obufp
++ = open_char
;
11690 if (intel_syntax
&& riprel
)
11693 oappend (!addr32flag
? "rip" : "eip");
11697 oappend (address_mode
== mode_64bit
&& !addr32flag
11698 ? names64
[rbase
] : names32
[rbase
]);
11701 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
11702 print index to tell base + index from base. */
11706 || (havebase
&& base
!= ESP_REG_NUM
))
11708 if (!intel_syntax
|| havebase
)
11710 *obufp
++ = separator_char
;
11714 oappend (address_mode
== mode_64bit
&& !addr32flag
11715 ? indexes64
[vindex
] : indexes32
[vindex
]);
11717 oappend (address_mode
== mode_64bit
&& !addr32flag
11718 ? index64
: index32
);
11720 *obufp
++ = scale_char
;
11722 sprintf (scratchbuf
, "%d", 1 << scale
);
11723 oappend (scratchbuf
);
11727 && (disp
|| modrm
.mod
!= 0 || base
== 5))
11729 if (!havedisp
|| (bfd_signed_vma
) disp
>= 0)
11734 else if (modrm
.mod
!= 1 && disp
!= -disp
)
11742 print_displacement (scratchbuf
, disp
);
11744 print_operand_value (scratchbuf
, 1, disp
);
11745 oappend (scratchbuf
);
11748 *obufp
++ = close_char
;
11751 else if (intel_syntax
)
11753 if (modrm
.mod
!= 0 || base
== 5)
11755 if (!active_seg_prefix
)
11757 oappend (names_seg
[ds_reg
- es_reg
]);
11760 print_operand_value (scratchbuf
, 1, disp
);
11761 oappend (scratchbuf
);
11765 else if (bytemode
== v_bnd_mode
11766 || bytemode
== v_bndmk_mode
11767 || bytemode
== bnd_mode
11768 || bytemode
== bnd_swap_mode
)
11775 /* 16 bit address mode */
11776 used_prefixes
|= prefixes
& PREFIX_ADDR
;
11783 if ((disp
& 0x8000) != 0)
11788 FETCH_DATA (the_info
, codep
+ 1);
11790 if ((disp
& 0x80) != 0)
11792 if (vex
.evex
&& shift
> 0)
11797 if ((disp
& 0x8000) != 0)
11803 if (modrm
.mod
!= 0 || modrm
.rm
== 6)
11805 print_displacement (scratchbuf
, disp
);
11806 oappend (scratchbuf
);
11809 if (modrm
.mod
!= 0 || modrm
.rm
!= 6)
11811 *obufp
++ = open_char
;
11813 oappend (index16
[modrm
.rm
]);
11815 && (disp
|| modrm
.mod
!= 0 || modrm
.rm
== 6))
11817 if ((bfd_signed_vma
) disp
>= 0)
11822 else if (modrm
.mod
!= 1)
11829 print_displacement (scratchbuf
, disp
);
11830 oappend (scratchbuf
);
11833 *obufp
++ = close_char
;
11836 else if (intel_syntax
)
11838 if (!active_seg_prefix
)
11840 oappend (names_seg
[ds_reg
- es_reg
]);
11843 print_operand_value (scratchbuf
, 1, disp
& 0xffff);
11844 oappend (scratchbuf
);
11848 && (bytemode
== x_mode
11849 || bytemode
== evex_half_bcst_xmmq_mode
))
11852 || bytemode
== evex_half_bcst_xmmq_mode
)
11854 switch (vex
.length
)
11857 oappend ("{1to2}");
11860 oappend ("{1to4}");
11863 oappend ("{1to8}");
11871 switch (vex
.length
)
11874 oappend ("{1to4}");
11877 oappend ("{1to8}");
11880 oappend ("{1to16}");
11890 OP_E (int bytemode
, int sizeflag
)
11892 /* Skip mod/rm byte. */
11896 if (modrm
.mod
== 3)
11897 OP_E_register (bytemode
, sizeflag
);
11899 OP_E_memory (bytemode
, sizeflag
);
11903 OP_G (int bytemode
, int sizeflag
)
11906 const char **names
;
11916 oappend (names8rex
[modrm
.reg
+ add
]);
11918 oappend (names8
[modrm
.reg
+ add
]);
11921 oappend (names16
[modrm
.reg
+ add
]);
11926 oappend (names32
[modrm
.reg
+ add
]);
11929 oappend (names64
[modrm
.reg
+ add
]);
11932 if (modrm
.reg
> 0x3)
11937 oappend (names_bnd
[modrm
.reg
]);
11947 oappend (names64
[modrm
.reg
+ add
]);
11948 else if (bytemode
!= v_mode
&& bytemode
!= movsxd_mode
)
11949 oappend (names32
[modrm
.reg
+ add
]);
11952 if (sizeflag
& DFLAG
)
11953 oappend (names32
[modrm
.reg
+ add
]);
11955 oappend (names16
[modrm
.reg
+ add
]);
11956 used_prefixes
|= (prefixes
& PREFIX_DATA
);
11960 names
= (address_mode
== mode_64bit
11961 ? names64
: names32
);
11962 if (!(prefixes
& PREFIX_ADDR
))
11964 if (address_mode
== mode_16bit
)
11969 /* Remove "addr16/addr32". */
11970 all_prefixes
[last_addr_prefix
] = 0;
11971 names
= (address_mode
!= mode_32bit
11972 ? names32
: names16
);
11973 used_prefixes
|= PREFIX_ADDR
;
11975 oappend (names
[modrm
.reg
+ add
]);
11978 if (address_mode
== mode_64bit
)
11979 oappend (names64
[modrm
.reg
+ add
]);
11981 oappend (names32
[modrm
.reg
+ add
]);
11985 if ((modrm
.reg
+ add
) > 0x7)
11990 oappend (names_mask
[modrm
.reg
+ add
]);
11993 oappend (INTERNAL_DISASSEMBLER_ERROR
);
12006 FETCH_DATA (the_info
, codep
+ 8);
12007 a
= *codep
++ & 0xff;
12008 a
|= (*codep
++ & 0xff) << 8;
12009 a
|= (*codep
++ & 0xff) << 16;
12010 a
|= (*codep
++ & 0xffu
) << 24;
12011 b
= *codep
++ & 0xff;
12012 b
|= (*codep
++ & 0xff) << 8;
12013 b
|= (*codep
++ & 0xff) << 16;
12014 b
|= (*codep
++ & 0xffu
) << 24;
12015 x
= a
+ ((bfd_vma
) b
<< 32);
12023 static bfd_signed_vma
12028 FETCH_DATA (the_info
, codep
+ 4);
12029 x
= *codep
++ & (bfd_vma
) 0xff;
12030 x
|= (*codep
++ & (bfd_vma
) 0xff) << 8;
12031 x
|= (*codep
++ & (bfd_vma
) 0xff) << 16;
12032 x
|= (*codep
++ & (bfd_vma
) 0xff) << 24;
12036 static bfd_signed_vma
12041 FETCH_DATA (the_info
, codep
+ 4);
12042 x
= *codep
++ & (bfd_vma
) 0xff;
12043 x
|= (*codep
++ & (bfd_vma
) 0xff) << 8;
12044 x
|= (*codep
++ & (bfd_vma
) 0xff) << 16;
12045 x
|= (*codep
++ & (bfd_vma
) 0xff) << 24;
12047 x
= (x
^ ((bfd_vma
) 1 << 31)) - ((bfd_vma
) 1 << 31);
12057 FETCH_DATA (the_info
, codep
+ 2);
12058 x
= *codep
++ & 0xff;
12059 x
|= (*codep
++ & 0xff) << 8;
12064 set_op (bfd_vma op
, int riprel
)
12066 op_index
[op_ad
] = op_ad
;
12067 if (address_mode
== mode_64bit
)
12069 op_address
[op_ad
] = op
;
12070 op_riprel
[op_ad
] = riprel
;
12074 /* Mask to get a 32-bit address. */
12075 op_address
[op_ad
] = op
& 0xffffffff;
12076 op_riprel
[op_ad
] = riprel
& 0xffffffff;
12081 OP_REG (int code
, int sizeflag
)
12088 case es_reg
: case ss_reg
: case cs_reg
:
12089 case ds_reg
: case fs_reg
: case gs_reg
:
12090 oappend (names_seg
[code
- es_reg
]);
12102 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
12103 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
12104 s
= names16
[code
- ax_reg
+ add
];
12106 case ah_reg
: case ch_reg
: case dh_reg
: case bh_reg
:
12108 /* Fall through. */
12109 case al_reg
: case cl_reg
: case dl_reg
: case bl_reg
:
12111 s
= names8rex
[code
- al_reg
+ add
];
12113 s
= names8
[code
- al_reg
];
12115 case rAX_reg
: case rCX_reg
: case rDX_reg
: case rBX_reg
:
12116 case rSP_reg
: case rBP_reg
: case rSI_reg
: case rDI_reg
:
12117 if (address_mode
== mode_64bit
12118 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
12120 s
= names64
[code
- rAX_reg
+ add
];
12123 code
+= eAX_reg
- rAX_reg
;
12124 /* Fall through. */
12125 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
12126 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
12129 s
= names64
[code
- eAX_reg
+ add
];
12132 if (sizeflag
& DFLAG
)
12133 s
= names32
[code
- eAX_reg
+ add
];
12135 s
= names16
[code
- eAX_reg
+ add
];
12136 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12140 s
= INTERNAL_DISASSEMBLER_ERROR
;
12147 OP_IMREG (int code
, int sizeflag
)
12159 case al_reg
: case cl_reg
:
12160 s
= names8
[code
- al_reg
];
12169 /* Fall through. */
12170 case z_mode_ax_reg
:
12171 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
12175 if (!(rex
& REX_W
))
12176 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12179 s
= INTERNAL_DISASSEMBLER_ERROR
;
12186 OP_I (int bytemode
, int sizeflag
)
12189 bfd_signed_vma mask
= -1;
12194 FETCH_DATA (the_info
, codep
+ 1);
12204 if (sizeflag
& DFLAG
)
12214 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12230 oappend (INTERNAL_DISASSEMBLER_ERROR
);
12235 scratchbuf
[0] = '$';
12236 print_operand_value (scratchbuf
+ 1, 1, op
);
12237 oappend_maybe_intel (scratchbuf
);
12238 scratchbuf
[0] = '\0';
12242 OP_I64 (int bytemode
, int sizeflag
)
12244 if (bytemode
!= v_mode
|| address_mode
!= mode_64bit
|| !(rex
& REX_W
))
12246 OP_I (bytemode
, sizeflag
);
12252 scratchbuf
[0] = '$';
12253 print_operand_value (scratchbuf
+ 1, 1, get64 ());
12254 oappend_maybe_intel (scratchbuf
);
12255 scratchbuf
[0] = '\0';
12259 OP_sI (int bytemode
, int sizeflag
)
12267 FETCH_DATA (the_info
, codep
+ 1);
12269 if ((op
& 0x80) != 0)
12271 if (bytemode
== b_T_mode
)
12273 if (address_mode
!= mode_64bit
12274 || !((sizeflag
& DFLAG
) || (rex
& REX_W
)))
12276 /* The operand-size prefix is overridden by a REX prefix. */
12277 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
12285 if (!(rex
& REX_W
))
12287 if (sizeflag
& DFLAG
)
12295 /* The operand-size prefix is overridden by a REX prefix. */
12296 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
12302 oappend (INTERNAL_DISASSEMBLER_ERROR
);
12306 scratchbuf
[0] = '$';
12307 print_operand_value (scratchbuf
+ 1, 1, op
);
12308 oappend_maybe_intel (scratchbuf
);
12312 OP_J (int bytemode
, int sizeflag
)
12316 bfd_vma segment
= 0;
12321 FETCH_DATA (the_info
, codep
+ 1);
12323 if ((disp
& 0x80) != 0)
12328 if ((sizeflag
& DFLAG
)
12329 || (address_mode
== mode_64bit
12330 && ((isa64
== intel64
&& bytemode
!= dqw_mode
)
12331 || (rex
& REX_W
))))
12336 if ((disp
& 0x8000) != 0)
12338 /* In 16bit mode, address is wrapped around at 64k within
12339 the same segment. Otherwise, a data16 prefix on a jump
12340 instruction means that the pc is masked to 16 bits after
12341 the displacement is added! */
12343 if ((prefixes
& PREFIX_DATA
) == 0)
12344 segment
= ((start_pc
+ (codep
- start_codep
))
12345 & ~((bfd_vma
) 0xffff));
12347 if (address_mode
!= mode_64bit
12348 || (isa64
!= intel64
&& !(rex
& REX_W
)))
12349 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12352 oappend (INTERNAL_DISASSEMBLER_ERROR
);
12355 disp
= ((start_pc
+ (codep
- start_codep
) + disp
) & mask
) | segment
;
12357 print_operand_value (scratchbuf
, 1, disp
);
12358 oappend (scratchbuf
);
12362 OP_SEG (int bytemode
, int sizeflag
)
12364 if (bytemode
== w_mode
)
12365 oappend (names_seg
[modrm
.reg
]);
12367 OP_E (modrm
.mod
== 3 ? bytemode
: w_mode
, sizeflag
);
12371 OP_DIR (int dummy ATTRIBUTE_UNUSED
, int sizeflag
)
12375 if (sizeflag
& DFLAG
)
12385 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12387 sprintf (scratchbuf
, "0x%x:0x%x", seg
, offset
);
12389 sprintf (scratchbuf
, "$0x%x,$0x%x", seg
, offset
);
12390 oappend (scratchbuf
);
12394 OP_OFF (int bytemode
, int sizeflag
)
12398 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
12399 intel_operand_size (bytemode
, sizeflag
);
12402 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
12409 if (!active_seg_prefix
)
12411 oappend (names_seg
[ds_reg
- es_reg
]);
12415 print_operand_value (scratchbuf
, 1, off
);
12416 oappend (scratchbuf
);
12420 OP_OFF64 (int bytemode
, int sizeflag
)
12424 if (address_mode
!= mode_64bit
12425 || (prefixes
& PREFIX_ADDR
))
12427 OP_OFF (bytemode
, sizeflag
);
12431 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
12432 intel_operand_size (bytemode
, sizeflag
);
12439 if (!active_seg_prefix
)
12441 oappend (names_seg
[ds_reg
- es_reg
]);
12445 print_operand_value (scratchbuf
, 1, off
);
12446 oappend (scratchbuf
);
12450 ptr_reg (int code
, int sizeflag
)
12454 *obufp
++ = open_char
;
12455 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
12456 if (address_mode
== mode_64bit
)
12458 if (!(sizeflag
& AFLAG
))
12459 s
= names32
[code
- eAX_reg
];
12461 s
= names64
[code
- eAX_reg
];
12463 else if (sizeflag
& AFLAG
)
12464 s
= names32
[code
- eAX_reg
];
12466 s
= names16
[code
- eAX_reg
];
12468 *obufp
++ = close_char
;
12473 OP_ESreg (int code
, int sizeflag
)
12479 case 0x6d: /* insw/insl */
12480 intel_operand_size (z_mode
, sizeflag
);
12482 case 0xa5: /* movsw/movsl/movsq */
12483 case 0xa7: /* cmpsw/cmpsl/cmpsq */
12484 case 0xab: /* stosw/stosl */
12485 case 0xaf: /* scasw/scasl */
12486 intel_operand_size (v_mode
, sizeflag
);
12489 intel_operand_size (b_mode
, sizeflag
);
12492 oappend_maybe_intel ("%es:");
12493 ptr_reg (code
, sizeflag
);
12497 OP_DSreg (int code
, int sizeflag
)
12503 case 0x6f: /* outsw/outsl */
12504 intel_operand_size (z_mode
, sizeflag
);
12506 case 0xa5: /* movsw/movsl/movsq */
12507 case 0xa7: /* cmpsw/cmpsl/cmpsq */
12508 case 0xad: /* lodsw/lodsl/lodsq */
12509 intel_operand_size (v_mode
, sizeflag
);
12512 intel_operand_size (b_mode
, sizeflag
);
12515 /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
12516 default segment register DS is printed. */
12517 if (!active_seg_prefix
)
12518 active_seg_prefix
= PREFIX_DS
;
12520 ptr_reg (code
, sizeflag
);
12524 OP_C (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
12532 else if (address_mode
!= mode_64bit
&& (prefixes
& PREFIX_LOCK
))
12534 all_prefixes
[last_lock_prefix
] = 0;
12535 used_prefixes
|= PREFIX_LOCK
;
12540 sprintf (scratchbuf
, "%%cr%d", modrm
.reg
+ add
);
12541 oappend_maybe_intel (scratchbuf
);
12545 OP_D (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
12554 sprintf (scratchbuf
, "dr%d", modrm
.reg
+ add
);
12556 sprintf (scratchbuf
, "%%db%d", modrm
.reg
+ add
);
12557 oappend (scratchbuf
);
12561 OP_T (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
12563 sprintf (scratchbuf
, "%%tr%d", modrm
.reg
);
12564 oappend_maybe_intel (scratchbuf
);
12568 OP_MMX (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
12570 int reg
= modrm
.reg
;
12571 const char **names
;
12573 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12574 if (prefixes
& PREFIX_DATA
)
12583 oappend (names
[reg
]);
12587 OP_XMM (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
12589 int reg
= modrm
.reg
;
12590 const char **names
;
12601 if (bytemode
== xmmq_mode
12602 || bytemode
== evex_half_bcst_xmmq_mode
)
12604 switch (vex
.length
)
12617 else if (bytemode
== ymm_mode
)
12619 else if (bytemode
== tmm_mode
)
12630 && bytemode
!= xmm_mode
12631 && bytemode
!= scalar_mode
)
12633 switch (vex
.length
)
12640 || bytemode
!= vex_vsib_q_w_dq_mode
)
12647 || bytemode
!= vex_vsib_q_w_dq_mode
)
12658 oappend (names
[reg
]);
12662 OP_EM (int bytemode
, int sizeflag
)
12665 const char **names
;
12667 if (modrm
.mod
!= 3)
12670 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
12672 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
12673 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12675 OP_E (bytemode
, sizeflag
);
12679 if ((sizeflag
& SUFFIX_ALWAYS
) && bytemode
== v_swap_mode
)
12682 /* Skip mod/rm byte. */
12685 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12687 if (prefixes
& PREFIX_DATA
)
12696 oappend (names
[reg
]);
12699 /* cvt* are the only instructions in sse2 which have
12700 both SSE and MMX operands and also have 0x66 prefix
12701 in their opcode. 0x66 was originally used to differentiate
12702 between SSE and MMX instruction(operands). So we have to handle the
12703 cvt* separately using OP_EMC and OP_MXC */
12705 OP_EMC (int bytemode
, int sizeflag
)
12707 if (modrm
.mod
!= 3)
12709 if (intel_syntax
&& bytemode
== v_mode
)
12711 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
12712 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12714 OP_E (bytemode
, sizeflag
);
12718 /* Skip mod/rm byte. */
12721 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12722 oappend (names_mm
[modrm
.rm
]);
12726 OP_MXC (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
12728 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12729 oappend (names_mm
[modrm
.reg
]);
12733 OP_EX (int bytemode
, int sizeflag
)
12736 const char **names
;
12738 /* Skip mod/rm byte. */
12742 if (modrm
.mod
!= 3)
12744 OP_E_memory (bytemode
, sizeflag
);
12759 if ((sizeflag
& SUFFIX_ALWAYS
)
12760 && (bytemode
== x_swap_mode
12761 || bytemode
== d_swap_mode
12762 || bytemode
== q_swap_mode
))
12766 && bytemode
!= xmm_mode
12767 && bytemode
!= xmmdw_mode
12768 && bytemode
!= xmmqd_mode
12769 && bytemode
!= xmm_mb_mode
12770 && bytemode
!= xmm_mw_mode
12771 && bytemode
!= xmm_md_mode
12772 && bytemode
!= xmm_mq_mode
12773 && bytemode
!= xmmq_mode
12774 && bytemode
!= evex_half_bcst_xmmq_mode
12775 && bytemode
!= ymm_mode
12776 && bytemode
!= tmm_mode
12777 && bytemode
!= vex_scalar_w_dq_mode
)
12779 switch (vex
.length
)
12794 else if (bytemode
== xmmq_mode
12795 || bytemode
== evex_half_bcst_xmmq_mode
)
12797 switch (vex
.length
)
12810 else if (bytemode
== tmm_mode
)
12820 else if (bytemode
== ymm_mode
)
12824 oappend (names
[reg
]);
12828 OP_MS (int bytemode
, int sizeflag
)
12830 if (modrm
.mod
== 3)
12831 OP_EM (bytemode
, sizeflag
);
12837 OP_XS (int bytemode
, int sizeflag
)
12839 if (modrm
.mod
== 3)
12840 OP_EX (bytemode
, sizeflag
);
12846 OP_M (int bytemode
, int sizeflag
)
12848 if (modrm
.mod
== 3)
12849 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
12852 OP_E (bytemode
, sizeflag
);
12856 OP_0f07 (int bytemode
, int sizeflag
)
12858 if (modrm
.mod
!= 3 || modrm
.rm
!= 0)
12861 OP_E (bytemode
, sizeflag
);
12864 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
12865 32bit mode and "xchg %rax,%rax" in 64bit mode. */
12868 NOP_Fixup1 (int bytemode
, int sizeflag
)
12870 if ((prefixes
& PREFIX_DATA
) != 0
12873 && address_mode
== mode_64bit
))
12874 OP_REG (bytemode
, sizeflag
);
12876 strcpy (obuf
, "nop");
12880 NOP_Fixup2 (int bytemode
, int sizeflag
)
12882 if ((prefixes
& PREFIX_DATA
) != 0
12885 && address_mode
== mode_64bit
))
12886 OP_IMREG (bytemode
, sizeflag
);
12889 static const char *const Suffix3DNow
[] = {
12890 /* 00 */ NULL
, NULL
, NULL
, NULL
,
12891 /* 04 */ NULL
, NULL
, NULL
, NULL
,
12892 /* 08 */ NULL
, NULL
, NULL
, NULL
,
12893 /* 0C */ "pi2fw", "pi2fd", NULL
, NULL
,
12894 /* 10 */ NULL
, NULL
, NULL
, NULL
,
12895 /* 14 */ NULL
, NULL
, NULL
, NULL
,
12896 /* 18 */ NULL
, NULL
, NULL
, NULL
,
12897 /* 1C */ "pf2iw", "pf2id", NULL
, NULL
,
12898 /* 20 */ NULL
, NULL
, NULL
, NULL
,
12899 /* 24 */ NULL
, NULL
, NULL
, NULL
,
12900 /* 28 */ NULL
, NULL
, NULL
, NULL
,
12901 /* 2C */ NULL
, NULL
, NULL
, NULL
,
12902 /* 30 */ NULL
, NULL
, NULL
, NULL
,
12903 /* 34 */ NULL
, NULL
, NULL
, NULL
,
12904 /* 38 */ NULL
, NULL
, NULL
, NULL
,
12905 /* 3C */ NULL
, NULL
, NULL
, NULL
,
12906 /* 40 */ NULL
, NULL
, NULL
, NULL
,
12907 /* 44 */ NULL
, NULL
, NULL
, NULL
,
12908 /* 48 */ NULL
, NULL
, NULL
, NULL
,
12909 /* 4C */ NULL
, NULL
, NULL
, NULL
,
12910 /* 50 */ NULL
, NULL
, NULL
, NULL
,
12911 /* 54 */ NULL
, NULL
, NULL
, NULL
,
12912 /* 58 */ NULL
, NULL
, NULL
, NULL
,
12913 /* 5C */ NULL
, NULL
, NULL
, NULL
,
12914 /* 60 */ NULL
, NULL
, NULL
, NULL
,
12915 /* 64 */ NULL
, NULL
, NULL
, NULL
,
12916 /* 68 */ NULL
, NULL
, NULL
, NULL
,
12917 /* 6C */ NULL
, NULL
, NULL
, NULL
,
12918 /* 70 */ NULL
, NULL
, NULL
, NULL
,
12919 /* 74 */ NULL
, NULL
, NULL
, NULL
,
12920 /* 78 */ NULL
, NULL
, NULL
, NULL
,
12921 /* 7C */ NULL
, NULL
, NULL
, NULL
,
12922 /* 80 */ NULL
, NULL
, NULL
, NULL
,
12923 /* 84 */ NULL
, NULL
, NULL
, NULL
,
12924 /* 88 */ NULL
, NULL
, "pfnacc", NULL
,
12925 /* 8C */ NULL
, NULL
, "pfpnacc", NULL
,
12926 /* 90 */ "pfcmpge", NULL
, NULL
, NULL
,
12927 /* 94 */ "pfmin", NULL
, "pfrcp", "pfrsqrt",
12928 /* 98 */ NULL
, NULL
, "pfsub", NULL
,
12929 /* 9C */ NULL
, NULL
, "pfadd", NULL
,
12930 /* A0 */ "pfcmpgt", NULL
, NULL
, NULL
,
12931 /* A4 */ "pfmax", NULL
, "pfrcpit1", "pfrsqit1",
12932 /* A8 */ NULL
, NULL
, "pfsubr", NULL
,
12933 /* AC */ NULL
, NULL
, "pfacc", NULL
,
12934 /* B0 */ "pfcmpeq", NULL
, NULL
, NULL
,
12935 /* B4 */ "pfmul", NULL
, "pfrcpit2", "pmulhrw",
12936 /* B8 */ NULL
, NULL
, NULL
, "pswapd",
12937 /* BC */ NULL
, NULL
, NULL
, "pavgusb",
12938 /* C0 */ NULL
, NULL
, NULL
, NULL
,
12939 /* C4 */ NULL
, NULL
, NULL
, NULL
,
12940 /* C8 */ NULL
, NULL
, NULL
, NULL
,
12941 /* CC */ NULL
, NULL
, NULL
, NULL
,
12942 /* D0 */ NULL
, NULL
, NULL
, NULL
,
12943 /* D4 */ NULL
, NULL
, NULL
, NULL
,
12944 /* D8 */ NULL
, NULL
, NULL
, NULL
,
12945 /* DC */ NULL
, NULL
, NULL
, NULL
,
12946 /* E0 */ NULL
, NULL
, NULL
, NULL
,
12947 /* E4 */ NULL
, NULL
, NULL
, NULL
,
12948 /* E8 */ NULL
, NULL
, NULL
, NULL
,
12949 /* EC */ NULL
, NULL
, NULL
, NULL
,
12950 /* F0 */ NULL
, NULL
, NULL
, NULL
,
12951 /* F4 */ NULL
, NULL
, NULL
, NULL
,
12952 /* F8 */ NULL
, NULL
, NULL
, NULL
,
12953 /* FC */ NULL
, NULL
, NULL
, NULL
,
12957 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
12959 const char *mnemonic
;
12961 FETCH_DATA (the_info
, codep
+ 1);
12962 /* AMD 3DNow! instructions are specified by an opcode suffix in the
12963 place where an 8-bit immediate would normally go. ie. the last
12964 byte of the instruction. */
12965 obufp
= mnemonicendp
;
12966 mnemonic
= Suffix3DNow
[*codep
++ & 0xff];
12968 oappend (mnemonic
);
12971 /* Since a variable sized modrm/sib chunk is between the start
12972 of the opcode (0x0f0f) and the opcode suffix, we need to do
12973 all the modrm processing first, and don't know until now that
12974 we have a bad opcode. This necessitates some cleaning up. */
12975 op_out
[0][0] = '\0';
12976 op_out
[1][0] = '\0';
12979 mnemonicendp
= obufp
;
12982 static const struct op simd_cmp_op
[] =
12984 { STRING_COMMA_LEN ("eq") },
12985 { STRING_COMMA_LEN ("lt") },
12986 { STRING_COMMA_LEN ("le") },
12987 { STRING_COMMA_LEN ("unord") },
12988 { STRING_COMMA_LEN ("neq") },
12989 { STRING_COMMA_LEN ("nlt") },
12990 { STRING_COMMA_LEN ("nle") },
12991 { STRING_COMMA_LEN ("ord") }
12994 static const struct op vex_cmp_op
[] =
12996 { STRING_COMMA_LEN ("eq_uq") },
12997 { STRING_COMMA_LEN ("nge") },
12998 { STRING_COMMA_LEN ("ngt") },
12999 { STRING_COMMA_LEN ("false") },
13000 { STRING_COMMA_LEN ("neq_oq") },
13001 { STRING_COMMA_LEN ("ge") },
13002 { STRING_COMMA_LEN ("gt") },
13003 { STRING_COMMA_LEN ("true") },
13004 { STRING_COMMA_LEN ("eq_os") },
13005 { STRING_COMMA_LEN ("lt_oq") },
13006 { STRING_COMMA_LEN ("le_oq") },
13007 { STRING_COMMA_LEN ("unord_s") },
13008 { STRING_COMMA_LEN ("neq_us") },
13009 { STRING_COMMA_LEN ("nlt_uq") },
13010 { STRING_COMMA_LEN ("nle_uq") },
13011 { STRING_COMMA_LEN ("ord_s") },
13012 { STRING_COMMA_LEN ("eq_us") },
13013 { STRING_COMMA_LEN ("nge_uq") },
13014 { STRING_COMMA_LEN ("ngt_uq") },
13015 { STRING_COMMA_LEN ("false_os") },
13016 { STRING_COMMA_LEN ("neq_os") },
13017 { STRING_COMMA_LEN ("ge_oq") },
13018 { STRING_COMMA_LEN ("gt_oq") },
13019 { STRING_COMMA_LEN ("true_us") },
13023 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
13025 unsigned int cmp_type
;
13027 FETCH_DATA (the_info
, codep
+ 1);
13028 cmp_type
= *codep
++ & 0xff;
13029 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
))
13032 char *p
= mnemonicendp
- 2;
13036 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
13037 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
13040 && cmp_type
< ARRAY_SIZE (simd_cmp_op
) + ARRAY_SIZE (vex_cmp_op
))
13043 char *p
= mnemonicendp
- 2;
13047 cmp_type
-= ARRAY_SIZE (simd_cmp_op
);
13048 sprintf (p
, "%s%s", vex_cmp_op
[cmp_type
].name
, suffix
);
13049 mnemonicendp
+= vex_cmp_op
[cmp_type
].len
;
13053 /* We have a reserved extension byte. Output it directly. */
13054 scratchbuf
[0] = '$';
13055 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
13056 oappend_maybe_intel (scratchbuf
);
13057 scratchbuf
[0] = '\0';
13062 OP_Mwait (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
13064 /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx */
13067 strcpy (op_out
[0], names32
[0]);
13068 strcpy (op_out
[1], names32
[1]);
13069 if (bytemode
== eBX_reg
)
13070 strcpy (op_out
[2], names32
[3]);
13071 two_source_ops
= 1;
13073 /* Skip mod/rm byte. */
13079 OP_Monitor (int bytemode ATTRIBUTE_UNUSED
,
13080 int sizeflag ATTRIBUTE_UNUSED
)
13082 /* monitor %{e,r,}ax,%ecx,%edx" */
13085 const char **names
= (address_mode
== mode_64bit
13086 ? names64
: names32
);
13088 if (prefixes
& PREFIX_ADDR
)
13090 /* Remove "addr16/addr32". */
13091 all_prefixes
[last_addr_prefix
] = 0;
13092 names
= (address_mode
!= mode_32bit
13093 ? names32
: names16
);
13094 used_prefixes
|= PREFIX_ADDR
;
13096 else if (address_mode
== mode_16bit
)
13098 strcpy (op_out
[0], names
[0]);
13099 strcpy (op_out
[1], names32
[1]);
13100 strcpy (op_out
[2], names32
[2]);
13101 two_source_ops
= 1;
13103 /* Skip mod/rm byte. */
13111 /* Throw away prefixes and 1st. opcode byte. */
13112 codep
= insn_codep
+ 1;
13117 REP_Fixup (int bytemode
, int sizeflag
)
13119 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
13121 if (prefixes
& PREFIX_REPZ
)
13122 all_prefixes
[last_repz_prefix
] = REP_PREFIX
;
13129 OP_IMREG (bytemode
, sizeflag
);
13132 OP_ESreg (bytemode
, sizeflag
);
13135 OP_DSreg (bytemode
, sizeflag
);
13144 SEP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
13146 if ( isa64
!= amd64
)
13151 mnemonicendp
= obufp
;
13155 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
13159 BND_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
13161 if (prefixes
& PREFIX_REPNZ
)
13162 all_prefixes
[last_repnz_prefix
] = BND_PREFIX
;
13165 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
13169 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED
,
13170 int sizeflag ATTRIBUTE_UNUSED
)
13173 /* Since active_seg_prefix is not set in 64-bit mode, check whether
13174 we've seen a PREFIX_DS. */
13175 if ((prefixes
& PREFIX_DS
) != 0
13176 && (address_mode
!= mode_64bit
|| last_data_prefix
< 0))
13178 /* NOTRACK prefix is only valid on indirect branch instructions.
13179 NB: DATA prefix is unsupported for Intel64. */
13180 active_seg_prefix
= 0;
13181 all_prefixes
[last_seg_prefix
] = NOTRACK_PREFIX
;
13185 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
13186 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
13190 HLE_Fixup1 (int bytemode
, int sizeflag
)
13193 && (prefixes
& PREFIX_LOCK
) != 0)
13195 if (prefixes
& PREFIX_REPZ
)
13196 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
13197 if (prefixes
& PREFIX_REPNZ
)
13198 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
13201 OP_E (bytemode
, sizeflag
);
13204 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
13205 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
13209 HLE_Fixup2 (int bytemode
, int sizeflag
)
13211 if (modrm
.mod
!= 3)
13213 if (prefixes
& PREFIX_REPZ
)
13214 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
13215 if (prefixes
& PREFIX_REPNZ
)
13216 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
13219 OP_E (bytemode
, sizeflag
);
13222 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
13223 "xrelease" for memory operand. No check for LOCK prefix. */
13226 HLE_Fixup3 (int bytemode
, int sizeflag
)
13229 && last_repz_prefix
> last_repnz_prefix
13230 && (prefixes
& PREFIX_REPZ
) != 0)
13231 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
13233 OP_E (bytemode
, sizeflag
);
13237 CMPXCHG8B_Fixup (int bytemode
, int sizeflag
)
13242 /* Change cmpxchg8b to cmpxchg16b. */
13243 char *p
= mnemonicendp
- 2;
13244 mnemonicendp
= stpcpy (p
, "16b");
13247 else if ((prefixes
& PREFIX_LOCK
) != 0)
13249 if (prefixes
& PREFIX_REPZ
)
13250 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
13251 if (prefixes
& PREFIX_REPNZ
)
13252 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
13255 OP_M (bytemode
, sizeflag
);
13259 XMM_Fixup (int reg
, int sizeflag ATTRIBUTE_UNUSED
)
13261 const char **names
;
13265 switch (vex
.length
)
13279 oappend (names
[reg
]);
13283 FXSAVE_Fixup (int bytemode
, int sizeflag
)
13285 /* Add proper suffix to "fxsave" and "fxrstor". */
13289 char *p
= mnemonicendp
;
13295 OP_M (bytemode
, sizeflag
);
13298 /* Display the destination register operand for instructions with
13302 OP_VEX (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
13305 const char **names
;
13310 reg
= vex
.register_specifier
;
13311 vex
.register_specifier
= 0;
13312 if (address_mode
!= mode_64bit
)
13314 else if (vex
.evex
&& !vex
.v
)
13317 if (bytemode
== vex_scalar_mode
)
13319 oappend (names_xmm
[reg
]);
13323 if (bytemode
== tmm_mode
)
13325 /* All 3 TMM registers must be distinct. */
13330 /* This must be the 3rd operand. */
13331 if (obufp
!= op_out
[2])
13333 oappend (names_tmm
[reg
]);
13334 if (reg
== modrm
.reg
|| reg
== modrm
.rm
)
13335 strcpy (obufp
, "/(bad)");
13338 if (modrm
.reg
== modrm
.rm
|| modrm
.reg
== reg
|| modrm
.rm
== reg
)
13341 && (modrm
.reg
== modrm
.rm
|| modrm
.reg
== reg
))
13342 strcat (op_out
[0], "/(bad)");
13344 && (modrm
.rm
== modrm
.reg
|| modrm
.rm
== reg
))
13345 strcat (op_out
[1], "/(bad)");
13351 switch (vex
.length
)
13357 case vex_vsib_q_w_dq_mode
:
13373 names
= names_mask
;
13386 case vex_vsib_q_w_dq_mode
:
13387 names
= vex
.w
? names_ymm
: names_xmm
;
13396 names
= names_mask
;
13399 /* See PR binutils/20893 for a reproducer. */
13411 oappend (names
[reg
]);
13415 OP_VexR (int bytemode
, int sizeflag
)
13417 if (modrm
.mod
== 3)
13418 OP_VEX (bytemode
, sizeflag
);
13422 OP_VexW (int bytemode
, int sizeflag
)
13424 OP_VEX (bytemode
, sizeflag
);
13428 /* Swap 2nd and 3rd operands. */
13429 strcpy (scratchbuf
, op_out
[2]);
13430 strcpy (op_out
[2], op_out
[1]);
13431 strcpy (op_out
[1], scratchbuf
);
13436 OP_REG_VexI4 (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
13439 const char **names
= names_xmm
;
13441 FETCH_DATA (the_info
, codep
+ 1);
13444 if (bytemode
!= x_mode
&& bytemode
!= scalar_mode
)
13448 if (address_mode
!= mode_64bit
)
13451 if (bytemode
== x_mode
&& vex
.length
== 256)
13454 oappend (names
[reg
]);
13458 /* Swap 3rd and 4th operands. */
13459 strcpy (scratchbuf
, op_out
[3]);
13460 strcpy (op_out
[3], op_out
[2]);
13461 strcpy (op_out
[2], scratchbuf
);
13466 OP_VexI4 (int bytemode ATTRIBUTE_UNUSED
,
13467 int sizeflag ATTRIBUTE_UNUSED
)
13469 scratchbuf
[0] = '$';
13470 print_operand_value (scratchbuf
+ 1, 1, codep
[-1] & 0xf);
13471 oappend_maybe_intel (scratchbuf
);
13475 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
,
13476 int sizeflag ATTRIBUTE_UNUSED
)
13478 unsigned int cmp_type
;
13483 FETCH_DATA (the_info
, codep
+ 1);
13484 cmp_type
= *codep
++ & 0xff;
13485 /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
13486 If it's the case, print suffix, otherwise - print the immediate. */
13487 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
)
13492 char *p
= mnemonicendp
- 2;
13494 /* vpcmp* can have both one- and two-lettered suffix. */
13508 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
13509 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
13513 /* We have a reserved extension byte. Output it directly. */
13514 scratchbuf
[0] = '$';
13515 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
13516 oappend_maybe_intel (scratchbuf
);
13517 scratchbuf
[0] = '\0';
13521 static const struct op xop_cmp_op
[] =
13523 { STRING_COMMA_LEN ("lt") },
13524 { STRING_COMMA_LEN ("le") },
13525 { STRING_COMMA_LEN ("gt") },
13526 { STRING_COMMA_LEN ("ge") },
13527 { STRING_COMMA_LEN ("eq") },
13528 { STRING_COMMA_LEN ("neq") },
13529 { STRING_COMMA_LEN ("false") },
13530 { STRING_COMMA_LEN ("true") }
13534 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED
,
13535 int sizeflag ATTRIBUTE_UNUSED
)
13537 unsigned int cmp_type
;
13539 FETCH_DATA (the_info
, codep
+ 1);
13540 cmp_type
= *codep
++ & 0xff;
13541 if (cmp_type
< ARRAY_SIZE (xop_cmp_op
))
13544 char *p
= mnemonicendp
- 2;
13546 /* vpcom* can have both one- and two-lettered suffix. */
13560 sprintf (p
, "%s%s", xop_cmp_op
[cmp_type
].name
, suffix
);
13561 mnemonicendp
+= xop_cmp_op
[cmp_type
].len
;
13565 /* We have a reserved extension byte. Output it directly. */
13566 scratchbuf
[0] = '$';
13567 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
13568 oappend_maybe_intel (scratchbuf
);
13569 scratchbuf
[0] = '\0';
13573 static const struct op pclmul_op
[] =
13575 { STRING_COMMA_LEN ("lql") },
13576 { STRING_COMMA_LEN ("hql") },
13577 { STRING_COMMA_LEN ("lqh") },
13578 { STRING_COMMA_LEN ("hqh") }
13582 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED
,
13583 int sizeflag ATTRIBUTE_UNUSED
)
13585 unsigned int pclmul_type
;
13587 FETCH_DATA (the_info
, codep
+ 1);
13588 pclmul_type
= *codep
++ & 0xff;
13589 switch (pclmul_type
)
13600 if (pclmul_type
< ARRAY_SIZE (pclmul_op
))
13603 char *p
= mnemonicendp
- 3;
13608 sprintf (p
, "%s%s", pclmul_op
[pclmul_type
].name
, suffix
);
13609 mnemonicendp
+= pclmul_op
[pclmul_type
].len
;
13613 /* We have a reserved extension byte. Output it directly. */
13614 scratchbuf
[0] = '$';
13615 print_operand_value (scratchbuf
+ 1, 1, pclmul_type
);
13616 oappend_maybe_intel (scratchbuf
);
13617 scratchbuf
[0] = '\0';
13622 MOVSXD_Fixup (int bytemode
, int sizeflag
)
13624 /* Add proper suffix to "movsxd". */
13625 char *p
= mnemonicendp
;
13650 oappend (INTERNAL_DISASSEMBLER_ERROR
);
13657 OP_E (bytemode
, sizeflag
);
13661 OP_Mask (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
13664 || (bytemode
!= mask_mode
&& bytemode
!= mask_bd_mode
))
13668 if ((rex
& REX_R
) != 0 || !vex
.r
)
13674 oappend (names_mask
[modrm
.reg
]);
13678 OP_Rounding (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
13680 if (modrm
.mod
== 3 && vex
.b
)
13683 case evex_rounding_64_mode
:
13684 if (address_mode
!= mode_64bit
)
13689 /* Fall through. */
13690 case evex_rounding_mode
:
13691 oappend (names_rounding
[vex
.ll
]);
13693 case evex_sae_mode
: