1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988-2020 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
24 modified by John Hassey (hassey@dg-rtp.dg.com)
25 x86-64 support added by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
28 /* The main tables describing the instructions is essentially a copy
29 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30 Programmers Manual. Usually, there is a capital letter, followed
31 by a small letter. The capital letter tell the addressing mode,
32 and the small letter tells about the operand size. Refer to
33 the Intel manual for details. */
36 #include "disassemble.h"
38 #include "opcode/i386.h"
39 #include "libiberty.h"
40 #include "safe-ctype.h"
44 static int print_insn (bfd_vma
, disassemble_info
*);
45 static void dofloat (int);
46 static void OP_ST (int, int);
47 static void OP_STi (int, int);
48 static int putop (const char *, int);
49 static void oappend (const char *);
50 static void append_seg (void);
51 static void OP_indirE (int, int);
52 static void print_operand_value (char *, int, bfd_vma
);
53 static void OP_E_register (int, int);
54 static void OP_E_memory (int, int);
55 static void print_displacement (char *, bfd_vma
);
56 static void OP_E (int, int);
57 static void OP_G (int, int);
58 static bfd_vma
get64 (void);
59 static bfd_signed_vma
get32 (void);
60 static bfd_signed_vma
get32s (void);
61 static int get16 (void);
62 static void set_op (bfd_vma
, int);
63 static void OP_Skip_MODRM (int, int);
64 static void OP_REG (int, int);
65 static void OP_IMREG (int, int);
66 static void OP_I (int, int);
67 static void OP_I64 (int, int);
68 static void OP_sI (int, int);
69 static void OP_J (int, int);
70 static void OP_SEG (int, int);
71 static void OP_DIR (int, int);
72 static void OP_OFF (int, int);
73 static void OP_OFF64 (int, int);
74 static void ptr_reg (int, int);
75 static void OP_ESreg (int, int);
76 static void OP_DSreg (int, int);
77 static void OP_C (int, int);
78 static void OP_D (int, int);
79 static void OP_T (int, int);
80 static void OP_R (int, int);
81 static void OP_MMX (int, int);
82 static void OP_XMM (int, int);
83 static void OP_EM (int, int);
84 static void OP_EX (int, int);
85 static void OP_EMC (int,int);
86 static void OP_MXC (int,int);
87 static void OP_MS (int, int);
88 static void OP_XS (int, int);
89 static void OP_M (int, int);
90 static void OP_VEX (int, int);
91 static void OP_EX_Vex (int, int);
92 static void OP_EX_VexW (int, int);
93 static void OP_EX_VexImmW (int, int);
94 static void OP_XMM_Vex (int, int);
95 static void OP_XMM_VexW (int, int);
96 static void OP_Rounding (int, int);
97 static void OP_REG_VexI4 (int, int);
98 static void PCLMUL_Fixup (int, int);
99 static void VCMP_Fixup (int, int);
100 static void VPCMP_Fixup (int, int);
101 static void VPCOM_Fixup (int, int);
102 static void OP_0f07 (int, int);
103 static void OP_Monitor (int, int);
104 static void OP_Mwait (int, int);
105 static void NOP_Fixup1 (int, int);
106 static void NOP_Fixup2 (int, int);
107 static void OP_3DNowSuffix (int, int);
108 static void CMP_Fixup (int, int);
109 static void BadOp (void);
110 static void REP_Fixup (int, int);
111 static void SEP_Fixup (int, int);
112 static void BND_Fixup (int, int);
113 static void NOTRACK_Fixup (int, int);
114 static void HLE_Fixup1 (int, int);
115 static void HLE_Fixup2 (int, int);
116 static void HLE_Fixup3 (int, int);
117 static void CMPXCHG8B_Fixup (int, int);
118 static void XMM_Fixup (int, int);
119 static void CRC32_Fixup (int, int);
120 static void FXSAVE_Fixup (int, int);
121 static void PCMPESTR_Fixup (int, int);
122 static void OP_LWPCB_E (int, int);
123 static void OP_LWP_E (int, int);
124 static void OP_Vex_2src_1 (int, int);
125 static void OP_Vex_2src_2 (int, int);
127 static void MOVBE_Fixup (int, int);
128 static void MOVSXD_Fixup (int, int);
130 static void OP_Mask (int, int);
133 /* Points to first byte not fetched. */
134 bfd_byte
*max_fetched
;
135 bfd_byte the_buffer
[MAX_MNEM_SIZE
];
138 OPCODES_SIGJMP_BUF bailout
;
148 enum address_mode address_mode
;
150 /* Flags for the prefixes for the current instruction. See below. */
153 /* REX prefix the current instruction. See below. */
155 /* Bits of REX we've already used. */
157 /* Mark parts used in the REX prefix. When we are testing for
158 empty prefix (for 8bit register REX extension), just mask it
159 out. Otherwise test for REX bit is excuse for existence of REX
160 only in case value is nonzero. */
161 #define USED_REX(value) \
166 rex_used |= (value) | REX_OPCODE; \
169 rex_used |= REX_OPCODE; \
172 /* Flags for prefixes which we somehow handled when printing the
173 current instruction. */
174 static int used_prefixes
;
176 /* Flags stored in PREFIXES. */
177 #define PREFIX_REPZ 1
178 #define PREFIX_REPNZ 2
179 #define PREFIX_LOCK 4
181 #define PREFIX_SS 0x10
182 #define PREFIX_DS 0x20
183 #define PREFIX_ES 0x40
184 #define PREFIX_FS 0x80
185 #define PREFIX_GS 0x100
186 #define PREFIX_DATA 0x200
187 #define PREFIX_ADDR 0x400
188 #define PREFIX_FWAIT 0x800
190 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
191 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
193 #define FETCH_DATA(info, addr) \
194 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
195 ? 1 : fetch_data ((info), (addr)))
198 fetch_data (struct disassemble_info
*info
, bfd_byte
*addr
)
201 struct dis_private
*priv
= (struct dis_private
*) info
->private_data
;
202 bfd_vma start
= priv
->insn_start
+ (priv
->max_fetched
- priv
->the_buffer
);
204 if (addr
<= priv
->the_buffer
+ MAX_MNEM_SIZE
)
205 status
= (*info
->read_memory_func
) (start
,
207 addr
- priv
->max_fetched
,
213 /* If we did manage to read at least one byte, then
214 print_insn_i386 will do something sensible. Otherwise, print
215 an error. We do that here because this is where we know
217 if (priv
->max_fetched
== priv
->the_buffer
)
218 (*info
->memory_error_func
) (status
, start
, info
);
219 OPCODES_SIGLONGJMP (priv
->bailout
, 1);
222 priv
->max_fetched
= addr
;
226 /* Possible values for prefix requirement. */
227 #define PREFIX_IGNORED_SHIFT 16
228 #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
229 #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
230 #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
231 #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
232 #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
234 /* Opcode prefixes. */
235 #define PREFIX_OPCODE (PREFIX_REPZ \
239 /* Prefixes ignored. */
240 #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \
241 | PREFIX_IGNORED_REPNZ \
242 | PREFIX_IGNORED_DATA)
244 #define XX { NULL, 0 }
245 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
247 #define Eb { OP_E, b_mode }
248 #define Ebnd { OP_E, bnd_mode }
249 #define EbS { OP_E, b_swap_mode }
250 #define EbndS { OP_E, bnd_swap_mode }
251 #define Ev { OP_E, v_mode }
252 #define Eva { OP_E, va_mode }
253 #define Ev_bnd { OP_E, v_bnd_mode }
254 #define EvS { OP_E, v_swap_mode }
255 #define Ed { OP_E, d_mode }
256 #define Edq { OP_E, dq_mode }
257 #define Edqw { OP_E, dqw_mode }
258 #define Edqb { OP_E, dqb_mode }
259 #define Edb { OP_E, db_mode }
260 #define Edw { OP_E, dw_mode }
261 #define Edqd { OP_E, dqd_mode }
262 #define Eq { OP_E, q_mode }
263 #define indirEv { OP_indirE, indir_v_mode }
264 #define indirEp { OP_indirE, f_mode }
265 #define stackEv { OP_E, stack_v_mode }
266 #define Em { OP_E, m_mode }
267 #define Ew { OP_E, w_mode }
268 #define M { OP_M, 0 } /* lea, lgdt, etc. */
269 #define Ma { OP_M, a_mode }
270 #define Mb { OP_M, b_mode }
271 #define Md { OP_M, d_mode }
272 #define Mo { OP_M, o_mode }
273 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
274 #define Mq { OP_M, q_mode }
275 #define Mv_bnd { OP_M, v_bndmk_mode }
276 #define Mx { OP_M, x_mode }
277 #define Mxmm { OP_M, xmm_mode }
278 #define Gb { OP_G, b_mode }
279 #define Gbnd { OP_G, bnd_mode }
280 #define Gv { OP_G, v_mode }
281 #define Gd { OP_G, d_mode }
282 #define Gdq { OP_G, dq_mode }
283 #define Gm { OP_G, m_mode }
284 #define Gva { OP_G, va_mode }
285 #define Gw { OP_G, w_mode }
286 #define Rd { OP_R, d_mode }
287 #define Rdq { OP_R, dq_mode }
288 #define Rm { OP_R, m_mode }
289 #define Ib { OP_I, b_mode }
290 #define sIb { OP_sI, b_mode } /* sign extened byte */
291 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
292 #define Iv { OP_I, v_mode }
293 #define sIv { OP_sI, v_mode }
294 #define Iv64 { OP_I64, v_mode }
295 #define Id { OP_I, d_mode }
296 #define Iw { OP_I, w_mode }
297 #define I1 { OP_I, const_1_mode }
298 #define Jb { OP_J, b_mode }
299 #define Jv { OP_J, v_mode }
300 #define Jdqw { OP_J, dqw_mode }
301 #define Cm { OP_C, m_mode }
302 #define Dm { OP_D, m_mode }
303 #define Td { OP_T, d_mode }
304 #define Skip_MODRM { OP_Skip_MODRM, 0 }
306 #define RMeAX { OP_REG, eAX_reg }
307 #define RMeBX { OP_REG, eBX_reg }
308 #define RMeCX { OP_REG, eCX_reg }
309 #define RMeDX { OP_REG, eDX_reg }
310 #define RMeSP { OP_REG, eSP_reg }
311 #define RMeBP { OP_REG, eBP_reg }
312 #define RMeSI { OP_REG, eSI_reg }
313 #define RMeDI { OP_REG, eDI_reg }
314 #define RMrAX { OP_REG, rAX_reg }
315 #define RMrBX { OP_REG, rBX_reg }
316 #define RMrCX { OP_REG, rCX_reg }
317 #define RMrDX { OP_REG, rDX_reg }
318 #define RMrSP { OP_REG, rSP_reg }
319 #define RMrBP { OP_REG, rBP_reg }
320 #define RMrSI { OP_REG, rSI_reg }
321 #define RMrDI { OP_REG, rDI_reg }
322 #define RMAL { OP_REG, al_reg }
323 #define RMCL { OP_REG, cl_reg }
324 #define RMDL { OP_REG, dl_reg }
325 #define RMBL { OP_REG, bl_reg }
326 #define RMAH { OP_REG, ah_reg }
327 #define RMCH { OP_REG, ch_reg }
328 #define RMDH { OP_REG, dh_reg }
329 #define RMBH { OP_REG, bh_reg }
330 #define RMAX { OP_REG, ax_reg }
331 #define RMDX { OP_REG, dx_reg }
333 #define eAX { OP_IMREG, eAX_reg }
334 #define eBX { OP_IMREG, eBX_reg }
335 #define eCX { OP_IMREG, eCX_reg }
336 #define eDX { OP_IMREG, eDX_reg }
337 #define eSP { OP_IMREG, eSP_reg }
338 #define eBP { OP_IMREG, eBP_reg }
339 #define eSI { OP_IMREG, eSI_reg }
340 #define eDI { OP_IMREG, eDI_reg }
341 #define AL { OP_IMREG, al_reg }
342 #define CL { OP_IMREG, cl_reg }
343 #define DL { OP_IMREG, dl_reg }
344 #define BL { OP_IMREG, bl_reg }
345 #define AH { OP_IMREG, ah_reg }
346 #define CH { OP_IMREG, ch_reg }
347 #define DH { OP_IMREG, dh_reg }
348 #define BH { OP_IMREG, bh_reg }
349 #define AX { OP_IMREG, ax_reg }
350 #define DX { OP_IMREG, dx_reg }
351 #define zAX { OP_IMREG, z_mode_ax_reg }
352 #define indirDX { OP_IMREG, indir_dx_reg }
354 #define Sw { OP_SEG, w_mode }
355 #define Sv { OP_SEG, v_mode }
356 #define Ap { OP_DIR, 0 }
357 #define Ob { OP_OFF64, b_mode }
358 #define Ov { OP_OFF64, v_mode }
359 #define Xb { OP_DSreg, eSI_reg }
360 #define Xv { OP_DSreg, eSI_reg }
361 #define Xz { OP_DSreg, eSI_reg }
362 #define Yb { OP_ESreg, eDI_reg }
363 #define Yv { OP_ESreg, eDI_reg }
364 #define DSBX { OP_DSreg, eBX_reg }
366 #define es { OP_REG, es_reg }
367 #define ss { OP_REG, ss_reg }
368 #define cs { OP_REG, cs_reg }
369 #define ds { OP_REG, ds_reg }
370 #define fs { OP_REG, fs_reg }
371 #define gs { OP_REG, gs_reg }
373 #define MX { OP_MMX, 0 }
374 #define XM { OP_XMM, 0 }
375 #define XMScalar { OP_XMM, scalar_mode }
376 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
377 #define XMM { OP_XMM, xmm_mode }
378 #define XMxmmq { OP_XMM, xmmq_mode }
379 #define EM { OP_EM, v_mode }
380 #define EMS { OP_EM, v_swap_mode }
381 #define EMd { OP_EM, d_mode }
382 #define EMx { OP_EM, x_mode }
383 #define EXbScalar { OP_EX, b_scalar_mode }
384 #define EXw { OP_EX, w_mode }
385 #define EXwScalar { OP_EX, w_scalar_mode }
386 #define EXd { OP_EX, d_mode }
387 #define EXdS { OP_EX, d_swap_mode }
388 #define EXq { OP_EX, q_mode }
389 #define EXqS { OP_EX, q_swap_mode }
390 #define EXx { OP_EX, x_mode }
391 #define EXxS { OP_EX, x_swap_mode }
392 #define EXxmm { OP_EX, xmm_mode }
393 #define EXymm { OP_EX, ymm_mode }
394 #define EXxmmq { OP_EX, xmmq_mode }
395 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
396 #define EXxmm_mb { OP_EX, xmm_mb_mode }
397 #define EXxmm_mw { OP_EX, xmm_mw_mode }
398 #define EXxmm_md { OP_EX, xmm_md_mode }
399 #define EXxmm_mq { OP_EX, xmm_mq_mode }
400 #define EXxmmdw { OP_EX, xmmdw_mode }
401 #define EXxmmqd { OP_EX, xmmqd_mode }
402 #define EXymmq { OP_EX, ymmq_mode }
403 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
404 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
405 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
406 #define MS { OP_MS, v_mode }
407 #define XS { OP_XS, v_mode }
408 #define EMCq { OP_EMC, q_mode }
409 #define MXC { OP_MXC, 0 }
410 #define OPSUF { OP_3DNowSuffix, 0 }
411 #define SEP { SEP_Fixup, 0 }
412 #define CMP { CMP_Fixup, 0 }
413 #define XMM0 { XMM_Fixup, 0 }
414 #define FXSAVE { FXSAVE_Fixup, 0 }
415 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
416 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
418 #define Vex { OP_VEX, vex_mode }
419 #define VexScalar { OP_VEX, vex_scalar_mode }
420 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
421 #define Vex128 { OP_VEX, vex128_mode }
422 #define Vex256 { OP_VEX, vex256_mode }
423 #define VexGdq { OP_VEX, dq_mode }
424 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
425 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
426 #define EXVexW { OP_EX_VexW, x_mode }
427 #define EXdVexW { OP_EX_VexW, d_mode }
428 #define EXqVexW { OP_EX_VexW, q_mode }
429 #define EXVexImmW { OP_EX_VexImmW, x_mode }
430 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
431 #define XMVexW { OP_XMM_VexW, 0 }
432 #define XMVexI4 { OP_REG_VexI4, x_mode }
433 #define PCLMUL { PCLMUL_Fixup, 0 }
434 #define VCMP { VCMP_Fixup, 0 }
435 #define VPCMP { VPCMP_Fixup, 0 }
436 #define VPCOM { VPCOM_Fixup, 0 }
438 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
439 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
440 #define EXxEVexS { OP_Rounding, evex_sae_mode }
442 #define XMask { OP_Mask, mask_mode }
443 #define MaskG { OP_G, mask_mode }
444 #define MaskE { OP_E, mask_mode }
445 #define MaskBDE { OP_E, mask_bd_mode }
446 #define MaskR { OP_R, mask_mode }
447 #define MaskVex { OP_VEX, mask_mode }
449 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
450 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
451 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
452 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
454 /* Used handle "rep" prefix for string instructions. */
455 #define Xbr { REP_Fixup, eSI_reg }
456 #define Xvr { REP_Fixup, eSI_reg }
457 #define Ybr { REP_Fixup, eDI_reg }
458 #define Yvr { REP_Fixup, eDI_reg }
459 #define Yzr { REP_Fixup, eDI_reg }
460 #define indirDXr { REP_Fixup, indir_dx_reg }
461 #define ALr { REP_Fixup, al_reg }
462 #define eAXr { REP_Fixup, eAX_reg }
464 /* Used handle HLE prefix for lockable instructions. */
465 #define Ebh1 { HLE_Fixup1, b_mode }
466 #define Evh1 { HLE_Fixup1, v_mode }
467 #define Ebh2 { HLE_Fixup2, b_mode }
468 #define Evh2 { HLE_Fixup2, v_mode }
469 #define Ebh3 { HLE_Fixup3, b_mode }
470 #define Evh3 { HLE_Fixup3, v_mode }
472 #define BND { BND_Fixup, 0 }
473 #define NOTRACK { NOTRACK_Fixup, 0 }
475 #define cond_jump_flag { NULL, cond_jump_mode }
476 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
478 /* bits in sizeflag */
479 #define SUFFIX_ALWAYS 4
487 /* byte operand with operand swapped */
489 /* byte operand, sign extend like 'T' suffix */
491 /* operand size depends on prefixes */
493 /* operand size depends on prefixes with operand swapped */
495 /* operand size depends on address prefix */
499 /* double word operand */
501 /* double word operand with operand swapped */
503 /* quad word operand */
505 /* quad word operand with operand swapped */
507 /* ten-byte operand */
509 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
510 broadcast enabled. */
512 /* Similar to x_mode, but with different EVEX mem shifts. */
514 /* Similar to x_mode, but with disabled broadcast. */
516 /* Similar to x_mode, but with operands swapped and disabled broadcast
519 /* 16-byte XMM operand */
521 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
522 memory operand (depending on vector length). Broadcast isn't
525 /* Same as xmmq_mode, but broadcast is allowed. */
526 evex_half_bcst_xmmq_mode
,
527 /* XMM register or byte memory operand */
529 /* XMM register or word memory operand */
531 /* XMM register or double word memory operand */
533 /* XMM register or quad word memory operand */
535 /* 16-byte XMM, word, double word or quad word operand. */
537 /* 16-byte XMM, double word, quad word operand or xmm word operand. */
539 /* 32-byte YMM operand */
541 /* quad word, ymmword or zmmword memory operand. */
543 /* 32-byte YMM or 16-byte word operand */
545 /* d_mode in 32bit, q_mode in 64bit mode. */
547 /* pair of v_mode operands */
553 /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode. */
555 /* operand size depends on REX prefixes. */
557 /* registers like dq_mode, memory like w_mode, displacements like
558 v_mode without considering Intel64 ISA. */
562 /* bounds operand with operand swapped */
564 /* 4- or 6-byte pointer operand */
567 /* v_mode for indirect branch opcodes. */
569 /* v_mode for stack-related opcodes. */
571 /* non-quad operand size depends on prefixes */
573 /* 16-byte operand */
575 /* registers like dq_mode, memory like b_mode. */
577 /* registers like d_mode, memory like b_mode. */
579 /* registers like d_mode, memory like w_mode. */
581 /* registers like dq_mode, memory like d_mode. */
583 /* normal vex mode */
585 /* 128bit vex mode */
587 /* 256bit vex mode */
590 /* Operand size depends on the VEX.W bit, with VSIB dword indices. */
591 vex_vsib_d_w_dq_mode
,
592 /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */
594 /* Operand size depends on the VEX.W bit, with VSIB qword indices. */
595 vex_vsib_q_w_dq_mode
,
596 /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */
599 /* scalar, ignore vector length. */
601 /* like b_mode, ignore vector length. */
603 /* like w_mode, ignore vector length. */
605 /* like d_swap_mode, ignore vector length. */
607 /* like q_swap_mode, ignore vector length. */
609 /* like vex_mode, ignore vector length. */
611 /* Operand size depends on the VEX.W bit, ignore vector length. */
612 vex_scalar_w_dq_mode
,
614 /* Static rounding. */
616 /* Static rounding, 64-bit mode only. */
617 evex_rounding_64_mode
,
618 /* Supress all exceptions. */
621 /* Mask register operand. */
623 /* Mask register operand. */
691 #define FLOAT NULL, { { NULL, FLOATCODE } }, 0
693 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0
694 #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P
695 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
696 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
697 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
698 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
699 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
700 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
701 #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
702 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
703 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
704 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
705 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
706 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
707 #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I))
708 #define EVEX_LEN_TABLE(I) DIS386 (USE_EVEX_LEN_TABLE, (I))
838 MOD_VEX_0F12_PREFIX_0
,
839 MOD_VEX_0F12_PREFIX_2
,
841 MOD_VEX_0F16_PREFIX_0
,
842 MOD_VEX_0F16_PREFIX_2
,
845 MOD_VEX_W_0_0F41_P_0_LEN_1
,
846 MOD_VEX_W_1_0F41_P_0_LEN_1
,
847 MOD_VEX_W_0_0F41_P_2_LEN_1
,
848 MOD_VEX_W_1_0F41_P_2_LEN_1
,
849 MOD_VEX_W_0_0F42_P_0_LEN_1
,
850 MOD_VEX_W_1_0F42_P_0_LEN_1
,
851 MOD_VEX_W_0_0F42_P_2_LEN_1
,
852 MOD_VEX_W_1_0F42_P_2_LEN_1
,
853 MOD_VEX_W_0_0F44_P_0_LEN_1
,
854 MOD_VEX_W_1_0F44_P_0_LEN_1
,
855 MOD_VEX_W_0_0F44_P_2_LEN_1
,
856 MOD_VEX_W_1_0F44_P_2_LEN_1
,
857 MOD_VEX_W_0_0F45_P_0_LEN_1
,
858 MOD_VEX_W_1_0F45_P_0_LEN_1
,
859 MOD_VEX_W_0_0F45_P_2_LEN_1
,
860 MOD_VEX_W_1_0F45_P_2_LEN_1
,
861 MOD_VEX_W_0_0F46_P_0_LEN_1
,
862 MOD_VEX_W_1_0F46_P_0_LEN_1
,
863 MOD_VEX_W_0_0F46_P_2_LEN_1
,
864 MOD_VEX_W_1_0F46_P_2_LEN_1
,
865 MOD_VEX_W_0_0F47_P_0_LEN_1
,
866 MOD_VEX_W_1_0F47_P_0_LEN_1
,
867 MOD_VEX_W_0_0F47_P_2_LEN_1
,
868 MOD_VEX_W_1_0F47_P_2_LEN_1
,
869 MOD_VEX_W_0_0F4A_P_0_LEN_1
,
870 MOD_VEX_W_1_0F4A_P_0_LEN_1
,
871 MOD_VEX_W_0_0F4A_P_2_LEN_1
,
872 MOD_VEX_W_1_0F4A_P_2_LEN_1
,
873 MOD_VEX_W_0_0F4B_P_0_LEN_1
,
874 MOD_VEX_W_1_0F4B_P_0_LEN_1
,
875 MOD_VEX_W_0_0F4B_P_2_LEN_1
,
887 MOD_VEX_W_0_0F91_P_0_LEN_0
,
888 MOD_VEX_W_1_0F91_P_0_LEN_0
,
889 MOD_VEX_W_0_0F91_P_2_LEN_0
,
890 MOD_VEX_W_1_0F91_P_2_LEN_0
,
891 MOD_VEX_W_0_0F92_P_0_LEN_0
,
892 MOD_VEX_W_0_0F92_P_2_LEN_0
,
893 MOD_VEX_0F92_P_3_LEN_0
,
894 MOD_VEX_W_0_0F93_P_0_LEN_0
,
895 MOD_VEX_W_0_0F93_P_2_LEN_0
,
896 MOD_VEX_0F93_P_3_LEN_0
,
897 MOD_VEX_W_0_0F98_P_0_LEN_0
,
898 MOD_VEX_W_1_0F98_P_0_LEN_0
,
899 MOD_VEX_W_0_0F98_P_2_LEN_0
,
900 MOD_VEX_W_1_0F98_P_2_LEN_0
,
901 MOD_VEX_W_0_0F99_P_0_LEN_0
,
902 MOD_VEX_W_1_0F99_P_0_LEN_0
,
903 MOD_VEX_W_0_0F99_P_2_LEN_0
,
904 MOD_VEX_W_1_0F99_P_2_LEN_0
,
907 MOD_VEX_0FD7_PREFIX_2
,
908 MOD_VEX_0FE7_PREFIX_2
,
909 MOD_VEX_0FF0_PREFIX_3
,
910 MOD_VEX_0F381A_PREFIX_2
,
911 MOD_VEX_0F382A_PREFIX_2
,
912 MOD_VEX_0F382C_PREFIX_2
,
913 MOD_VEX_0F382D_PREFIX_2
,
914 MOD_VEX_0F382E_PREFIX_2
,
915 MOD_VEX_0F382F_PREFIX_2
,
916 MOD_VEX_0F385A_PREFIX_2
,
917 MOD_VEX_0F388C_PREFIX_2
,
918 MOD_VEX_0F388E_PREFIX_2
,
919 MOD_VEX_W_0_0F3A30_P_2_LEN_0
,
920 MOD_VEX_W_1_0F3A30_P_2_LEN_0
,
921 MOD_VEX_W_0_0F3A31_P_2_LEN_0
,
922 MOD_VEX_W_1_0F3A31_P_2_LEN_0
,
923 MOD_VEX_W_0_0F3A32_P_2_LEN_0
,
924 MOD_VEX_W_1_0F3A32_P_2_LEN_0
,
925 MOD_VEX_W_0_0F3A33_P_2_LEN_0
,
926 MOD_VEX_W_1_0F3A33_P_2_LEN_0
,
928 MOD_EVEX_0F12_PREFIX_0
,
929 MOD_EVEX_0F12_PREFIX_2
,
931 MOD_EVEX_0F16_PREFIX_0
,
932 MOD_EVEX_0F16_PREFIX_2
,
935 MOD_EVEX_0F38C6_REG_1
,
936 MOD_EVEX_0F38C6_REG_2
,
937 MOD_EVEX_0F38C6_REG_5
,
938 MOD_EVEX_0F38C6_REG_6
,
939 MOD_EVEX_0F38C7_REG_1
,
940 MOD_EVEX_0F38C7_REG_2
,
941 MOD_EVEX_0F38C7_REG_5
,
942 MOD_EVEX_0F38C7_REG_6
955 RM_0F1E_P_1_MOD_3_REG_7
,
956 RM_0FAE_REG_6_MOD_3_P_0
,
963 PREFIX_0F01_REG_3_RM_1
,
964 PREFIX_0F01_REG_5_MOD_0
,
965 PREFIX_0F01_REG_5_MOD_3_RM_0
,
966 PREFIX_0F01_REG_5_MOD_3_RM_1
,
967 PREFIX_0F01_REG_5_MOD_3_RM_2
,
968 PREFIX_0F01_REG_7_MOD_3_RM_2
,
969 PREFIX_0F01_REG_7_MOD_3_RM_3
,
1011 PREFIX_0FAE_REG_0_MOD_3
,
1012 PREFIX_0FAE_REG_1_MOD_3
,
1013 PREFIX_0FAE_REG_2_MOD_3
,
1014 PREFIX_0FAE_REG_3_MOD_3
,
1015 PREFIX_0FAE_REG_4_MOD_0
,
1016 PREFIX_0FAE_REG_4_MOD_3
,
1017 PREFIX_0FAE_REG_5_MOD_0
,
1018 PREFIX_0FAE_REG_5_MOD_3
,
1019 PREFIX_0FAE_REG_6_MOD_0
,
1020 PREFIX_0FAE_REG_6_MOD_3
,
1021 PREFIX_0FAE_REG_7_MOD_0
,
1027 PREFIX_0FC7_REG_6_MOD_0
,
1028 PREFIX_0FC7_REG_6_MOD_3
,
1029 PREFIX_0FC7_REG_7_MOD_3
,
1159 PREFIX_VEX_0F71_REG_2
,
1160 PREFIX_VEX_0F71_REG_4
,
1161 PREFIX_VEX_0F71_REG_6
,
1162 PREFIX_VEX_0F72_REG_2
,
1163 PREFIX_VEX_0F72_REG_4
,
1164 PREFIX_VEX_0F72_REG_6
,
1165 PREFIX_VEX_0F73_REG_2
,
1166 PREFIX_VEX_0F73_REG_3
,
1167 PREFIX_VEX_0F73_REG_6
,
1168 PREFIX_VEX_0F73_REG_7
,
1341 PREFIX_VEX_0F38F3_REG_1
,
1342 PREFIX_VEX_0F38F3_REG_2
,
1343 PREFIX_VEX_0F38F3_REG_3
,
1440 PREFIX_EVEX_0F71_REG_2
,
1441 PREFIX_EVEX_0F71_REG_4
,
1442 PREFIX_EVEX_0F71_REG_6
,
1443 PREFIX_EVEX_0F72_REG_0
,
1444 PREFIX_EVEX_0F72_REG_1
,
1445 PREFIX_EVEX_0F72_REG_2
,
1446 PREFIX_EVEX_0F72_REG_4
,
1447 PREFIX_EVEX_0F72_REG_6
,
1448 PREFIX_EVEX_0F73_REG_2
,
1449 PREFIX_EVEX_0F73_REG_3
,
1450 PREFIX_EVEX_0F73_REG_6
,
1451 PREFIX_EVEX_0F73_REG_7
,
1573 PREFIX_EVEX_0F38C6_REG_1
,
1574 PREFIX_EVEX_0F38C6_REG_2
,
1575 PREFIX_EVEX_0F38C6_REG_5
,
1576 PREFIX_EVEX_0F38C6_REG_6
,
1577 PREFIX_EVEX_0F38C7_REG_1
,
1578 PREFIX_EVEX_0F38C7_REG_2
,
1579 PREFIX_EVEX_0F38C7_REG_5
,
1580 PREFIX_EVEX_0F38C7_REG_6
,
1673 THREE_BYTE_0F38
= 0,
1700 VEX_LEN_0F12_P_0_M_0
= 0,
1701 VEX_LEN_0F12_P_0_M_1
,
1702 #define VEX_LEN_0F12_P_2_M_0 VEX_LEN_0F12_P_0_M_0
1704 VEX_LEN_0F16_P_0_M_0
,
1705 VEX_LEN_0F16_P_0_M_1
,
1706 #define VEX_LEN_0F16_P_2_M_0 VEX_LEN_0F16_P_0_M_0
1742 VEX_LEN_0FAE_R_2_M_0
,
1743 VEX_LEN_0FAE_R_3_M_0
,
1750 VEX_LEN_0F381A_P_2_M_0
,
1753 VEX_LEN_0F385A_P_2_M_0
,
1756 VEX_LEN_0F38F3_R_1_P_0
,
1757 VEX_LEN_0F38F3_R_2_P_0
,
1758 VEX_LEN_0F38F3_R_3_P_0
,
1801 VEX_LEN_0FXOP_08_CC
,
1802 VEX_LEN_0FXOP_08_CD
,
1803 VEX_LEN_0FXOP_08_CE
,
1804 VEX_LEN_0FXOP_08_CF
,
1805 VEX_LEN_0FXOP_08_EC
,
1806 VEX_LEN_0FXOP_08_ED
,
1807 VEX_LEN_0FXOP_08_EE
,
1808 VEX_LEN_0FXOP_08_EF
,
1809 VEX_LEN_0FXOP_09_80
,
1815 EVEX_LEN_0F6E_P_2
= 0,
1821 EVEX_LEN_0F3816_P_2
,
1822 EVEX_LEN_0F3819_P_2_W_0
,
1823 EVEX_LEN_0F3819_P_2_W_1
,
1824 EVEX_LEN_0F381A_P_2_W_0
,
1825 EVEX_LEN_0F381A_P_2_W_1
,
1826 EVEX_LEN_0F381B_P_2_W_0
,
1827 EVEX_LEN_0F381B_P_2_W_1
,
1828 EVEX_LEN_0F3836_P_2
,
1829 EVEX_LEN_0F385A_P_2_W_0
,
1830 EVEX_LEN_0F385A_P_2_W_1
,
1831 EVEX_LEN_0F385B_P_2_W_0
,
1832 EVEX_LEN_0F385B_P_2_W_1
,
1833 EVEX_LEN_0F38C6_REG_1_PREFIX_2
,
1834 EVEX_LEN_0F38C6_REG_2_PREFIX_2
,
1835 EVEX_LEN_0F38C6_REG_5_PREFIX_2
,
1836 EVEX_LEN_0F38C6_REG_6_PREFIX_2
,
1837 EVEX_LEN_0F38C7_R_1_P_2_W_0
,
1838 EVEX_LEN_0F38C7_R_1_P_2_W_1
,
1839 EVEX_LEN_0F38C7_R_2_P_2_W_0
,
1840 EVEX_LEN_0F38C7_R_2_P_2_W_1
,
1841 EVEX_LEN_0F38C7_R_5_P_2_W_0
,
1842 EVEX_LEN_0F38C7_R_5_P_2_W_1
,
1843 EVEX_LEN_0F38C7_R_6_P_2_W_0
,
1844 EVEX_LEN_0F38C7_R_6_P_2_W_1
,
1845 EVEX_LEN_0F3A00_P_2_W_1
,
1846 EVEX_LEN_0F3A01_P_2_W_1
,
1847 EVEX_LEN_0F3A14_P_2
,
1848 EVEX_LEN_0F3A15_P_2
,
1849 EVEX_LEN_0F3A16_P_2
,
1850 EVEX_LEN_0F3A17_P_2
,
1851 EVEX_LEN_0F3A18_P_2_W_0
,
1852 EVEX_LEN_0F3A18_P_2_W_1
,
1853 EVEX_LEN_0F3A19_P_2_W_0
,
1854 EVEX_LEN_0F3A19_P_2_W_1
,
1855 EVEX_LEN_0F3A1A_P_2_W_0
,
1856 EVEX_LEN_0F3A1A_P_2_W_1
,
1857 EVEX_LEN_0F3A1B_P_2_W_0
,
1858 EVEX_LEN_0F3A1B_P_2_W_1
,
1859 EVEX_LEN_0F3A20_P_2
,
1860 EVEX_LEN_0F3A21_P_2_W_0
,
1861 EVEX_LEN_0F3A22_P_2
,
1862 EVEX_LEN_0F3A23_P_2_W_0
,
1863 EVEX_LEN_0F3A23_P_2_W_1
,
1864 EVEX_LEN_0F3A38_P_2_W_0
,
1865 EVEX_LEN_0F3A38_P_2_W_1
,
1866 EVEX_LEN_0F3A39_P_2_W_0
,
1867 EVEX_LEN_0F3A39_P_2_W_1
,
1868 EVEX_LEN_0F3A3A_P_2_W_0
,
1869 EVEX_LEN_0F3A3A_P_2_W_1
,
1870 EVEX_LEN_0F3A3B_P_2_W_0
,
1871 EVEX_LEN_0F3A3B_P_2_W_1
,
1872 EVEX_LEN_0F3A43_P_2_W_0
,
1873 EVEX_LEN_0F3A43_P_2_W_1
1878 VEX_W_0F41_P_0_LEN_1
= 0,
1879 VEX_W_0F41_P_2_LEN_1
,
1880 VEX_W_0F42_P_0_LEN_1
,
1881 VEX_W_0F42_P_2_LEN_1
,
1882 VEX_W_0F44_P_0_LEN_0
,
1883 VEX_W_0F44_P_2_LEN_0
,
1884 VEX_W_0F45_P_0_LEN_1
,
1885 VEX_W_0F45_P_2_LEN_1
,
1886 VEX_W_0F46_P_0_LEN_1
,
1887 VEX_W_0F46_P_2_LEN_1
,
1888 VEX_W_0F47_P_0_LEN_1
,
1889 VEX_W_0F47_P_2_LEN_1
,
1890 VEX_W_0F4A_P_0_LEN_1
,
1891 VEX_W_0F4A_P_2_LEN_1
,
1892 VEX_W_0F4B_P_0_LEN_1
,
1893 VEX_W_0F4B_P_2_LEN_1
,
1894 VEX_W_0F90_P_0_LEN_0
,
1895 VEX_W_0F90_P_2_LEN_0
,
1896 VEX_W_0F91_P_0_LEN_0
,
1897 VEX_W_0F91_P_2_LEN_0
,
1898 VEX_W_0F92_P_0_LEN_0
,
1899 VEX_W_0F92_P_2_LEN_0
,
1900 VEX_W_0F93_P_0_LEN_0
,
1901 VEX_W_0F93_P_2_LEN_0
,
1902 VEX_W_0F98_P_0_LEN_0
,
1903 VEX_W_0F98_P_2_LEN_0
,
1904 VEX_W_0F99_P_0_LEN_0
,
1905 VEX_W_0F99_P_2_LEN_0
,
1914 VEX_W_0F381A_P_2_M_0
,
1915 VEX_W_0F382C_P_2_M_0
,
1916 VEX_W_0F382D_P_2_M_0
,
1917 VEX_W_0F382E_P_2_M_0
,
1918 VEX_W_0F382F_P_2_M_0
,
1923 VEX_W_0F385A_P_2_M_0
,
1936 VEX_W_0F3A30_P_2_LEN_0
,
1937 VEX_W_0F3A31_P_2_LEN_0
,
1938 VEX_W_0F3A32_P_2_LEN_0
,
1939 VEX_W_0F3A33_P_2_LEN_0
,
1955 EVEX_W_0F12_P_0_M_1
,
1958 EVEX_W_0F16_P_0_M_1
,
1992 EVEX_W_0F72_R_2_P_2
,
1993 EVEX_W_0F72_R_6_P_2
,
1994 EVEX_W_0F73_R_2_P_2
,
1995 EVEX_W_0F73_R_6_P_2
,
2096 EVEX_W_0F38C7_R_1_P_2
,
2097 EVEX_W_0F38C7_R_2_P_2
,
2098 EVEX_W_0F38C7_R_5_P_2
,
2099 EVEX_W_0F38C7_R_6_P_2
,
2134 typedef void (*op_rtn
) (int bytemode
, int sizeflag
);
2143 unsigned int prefix_requirement
;
2146 /* Upper case letters in the instruction names here are macros.
2147 'A' => print 'b' if no register operands or suffix_always is true
2148 'B' => print 'b' if suffix_always is true
2149 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2151 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2152 suffix_always is true
2153 'E' => print 'e' if 32-bit form of jcxz
2154 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2155 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2156 'H' => print ",pt" or ",pn" branch hint
2159 'K' => print 'd' or 'q' if rex prefix is present.
2160 'L' => print 'l' if suffix_always is true
2161 'M' => print 'r' if intel_mnemonic is false.
2162 'N' => print 'n' if instruction has no wait "prefix"
2163 'O' => print 'd' or 'o' (or 'q' in Intel mode)
2164 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2165 or suffix_always is true. print 'q' if rex prefix is present.
2166 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2168 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2169 'S' => print 'w', 'l' or 'q' if suffix_always is true
2170 'T' => print 'q' in 64bit mode if instruction has no operand size
2171 prefix and behave as 'P' otherwise
2172 'U' => print 'q' in 64bit mode if instruction has no operand size
2173 prefix and behave as 'Q' otherwise
2174 'V' => print 'q' in 64bit mode if instruction has no operand size
2175 prefix and behave as 'S' otherwise
2176 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2177 'X' => print 's', 'd' depending on data16 prefix (for XMM)
2179 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2180 '!' => change condition from true to false or from false to true.
2181 '%' => add 1 upper case letter to the macro.
2182 '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size
2183 prefix or suffix_always is true (lcall/ljmp).
2184 '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2185 on operand size prefix.
2186 '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2187 has no operand size prefix for AMD64 ISA, behave as 'P'
2190 2 upper case letter macros:
2191 "XY" => print 'x' or 'y' if suffix_always is true or no register
2192 operands and no broadcast.
2193 "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2194 register operands and no broadcast.
2195 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2196 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory
2197 operand or no operand at all in 64bit mode, or if suffix_always
2199 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2200 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2201 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2202 "LW" => print 'd', 'q' depending on the VEX.W bit
2203 "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2204 an operand size prefix, or suffix_always is true. print
2205 'q' if rex prefix is present.
2207 Many of the above letters print nothing in Intel mode. See "putop"
2210 Braces '{' and '}', and vertical bars '|', indicate alternative
2211 mnemonic strings for AT&T and Intel. */
2213 static const struct dis386 dis386
[] = {
2215 { "addB", { Ebh1
, Gb
}, 0 },
2216 { "addS", { Evh1
, Gv
}, 0 },
2217 { "addB", { Gb
, EbS
}, 0 },
2218 { "addS", { Gv
, EvS
}, 0 },
2219 { "addB", { AL
, Ib
}, 0 },
2220 { "addS", { eAX
, Iv
}, 0 },
2221 { X86_64_TABLE (X86_64_06
) },
2222 { X86_64_TABLE (X86_64_07
) },
2224 { "orB", { Ebh1
, Gb
}, 0 },
2225 { "orS", { Evh1
, Gv
}, 0 },
2226 { "orB", { Gb
, EbS
}, 0 },
2227 { "orS", { Gv
, EvS
}, 0 },
2228 { "orB", { AL
, Ib
}, 0 },
2229 { "orS", { eAX
, Iv
}, 0 },
2230 { X86_64_TABLE (X86_64_0E
) },
2231 { Bad_Opcode
}, /* 0x0f extended opcode escape */
2233 { "adcB", { Ebh1
, Gb
}, 0 },
2234 { "adcS", { Evh1
, Gv
}, 0 },
2235 { "adcB", { Gb
, EbS
}, 0 },
2236 { "adcS", { Gv
, EvS
}, 0 },
2237 { "adcB", { AL
, Ib
}, 0 },
2238 { "adcS", { eAX
, Iv
}, 0 },
2239 { X86_64_TABLE (X86_64_16
) },
2240 { X86_64_TABLE (X86_64_17
) },
2242 { "sbbB", { Ebh1
, Gb
}, 0 },
2243 { "sbbS", { Evh1
, Gv
}, 0 },
2244 { "sbbB", { Gb
, EbS
}, 0 },
2245 { "sbbS", { Gv
, EvS
}, 0 },
2246 { "sbbB", { AL
, Ib
}, 0 },
2247 { "sbbS", { eAX
, Iv
}, 0 },
2248 { X86_64_TABLE (X86_64_1E
) },
2249 { X86_64_TABLE (X86_64_1F
) },
2251 { "andB", { Ebh1
, Gb
}, 0 },
2252 { "andS", { Evh1
, Gv
}, 0 },
2253 { "andB", { Gb
, EbS
}, 0 },
2254 { "andS", { Gv
, EvS
}, 0 },
2255 { "andB", { AL
, Ib
}, 0 },
2256 { "andS", { eAX
, Iv
}, 0 },
2257 { Bad_Opcode
}, /* SEG ES prefix */
2258 { X86_64_TABLE (X86_64_27
) },
2260 { "subB", { Ebh1
, Gb
}, 0 },
2261 { "subS", { Evh1
, Gv
}, 0 },
2262 { "subB", { Gb
, EbS
}, 0 },
2263 { "subS", { Gv
, EvS
}, 0 },
2264 { "subB", { AL
, Ib
}, 0 },
2265 { "subS", { eAX
, Iv
}, 0 },
2266 { Bad_Opcode
}, /* SEG CS prefix */
2267 { X86_64_TABLE (X86_64_2F
) },
2269 { "xorB", { Ebh1
, Gb
}, 0 },
2270 { "xorS", { Evh1
, Gv
}, 0 },
2271 { "xorB", { Gb
, EbS
}, 0 },
2272 { "xorS", { Gv
, EvS
}, 0 },
2273 { "xorB", { AL
, Ib
}, 0 },
2274 { "xorS", { eAX
, Iv
}, 0 },
2275 { Bad_Opcode
}, /* SEG SS prefix */
2276 { X86_64_TABLE (X86_64_37
) },
2278 { "cmpB", { Eb
, Gb
}, 0 },
2279 { "cmpS", { Ev
, Gv
}, 0 },
2280 { "cmpB", { Gb
, EbS
}, 0 },
2281 { "cmpS", { Gv
, EvS
}, 0 },
2282 { "cmpB", { AL
, Ib
}, 0 },
2283 { "cmpS", { eAX
, Iv
}, 0 },
2284 { Bad_Opcode
}, /* SEG DS prefix */
2285 { X86_64_TABLE (X86_64_3F
) },
2287 { "inc{S|}", { RMeAX
}, 0 },
2288 { "inc{S|}", { RMeCX
}, 0 },
2289 { "inc{S|}", { RMeDX
}, 0 },
2290 { "inc{S|}", { RMeBX
}, 0 },
2291 { "inc{S|}", { RMeSP
}, 0 },
2292 { "inc{S|}", { RMeBP
}, 0 },
2293 { "inc{S|}", { RMeSI
}, 0 },
2294 { "inc{S|}", { RMeDI
}, 0 },
2296 { "dec{S|}", { RMeAX
}, 0 },
2297 { "dec{S|}", { RMeCX
}, 0 },
2298 { "dec{S|}", { RMeDX
}, 0 },
2299 { "dec{S|}", { RMeBX
}, 0 },
2300 { "dec{S|}", { RMeSP
}, 0 },
2301 { "dec{S|}", { RMeBP
}, 0 },
2302 { "dec{S|}", { RMeSI
}, 0 },
2303 { "dec{S|}", { RMeDI
}, 0 },
2305 { "pushV", { RMrAX
}, 0 },
2306 { "pushV", { RMrCX
}, 0 },
2307 { "pushV", { RMrDX
}, 0 },
2308 { "pushV", { RMrBX
}, 0 },
2309 { "pushV", { RMrSP
}, 0 },
2310 { "pushV", { RMrBP
}, 0 },
2311 { "pushV", { RMrSI
}, 0 },
2312 { "pushV", { RMrDI
}, 0 },
2314 { "popV", { RMrAX
}, 0 },
2315 { "popV", { RMrCX
}, 0 },
2316 { "popV", { RMrDX
}, 0 },
2317 { "popV", { RMrBX
}, 0 },
2318 { "popV", { RMrSP
}, 0 },
2319 { "popV", { RMrBP
}, 0 },
2320 { "popV", { RMrSI
}, 0 },
2321 { "popV", { RMrDI
}, 0 },
2323 { X86_64_TABLE (X86_64_60
) },
2324 { X86_64_TABLE (X86_64_61
) },
2325 { X86_64_TABLE (X86_64_62
) },
2326 { X86_64_TABLE (X86_64_63
) },
2327 { Bad_Opcode
}, /* seg fs */
2328 { Bad_Opcode
}, /* seg gs */
2329 { Bad_Opcode
}, /* op size prefix */
2330 { Bad_Opcode
}, /* adr size prefix */
2332 { "pushT", { sIv
}, 0 },
2333 { "imulS", { Gv
, Ev
, Iv
}, 0 },
2334 { "pushT", { sIbT
}, 0 },
2335 { "imulS", { Gv
, Ev
, sIb
}, 0 },
2336 { "ins{b|}", { Ybr
, indirDX
}, 0 },
2337 { X86_64_TABLE (X86_64_6D
) },
2338 { "outs{b|}", { indirDXr
, Xb
}, 0 },
2339 { X86_64_TABLE (X86_64_6F
) },
2341 { "joH", { Jb
, BND
, cond_jump_flag
}, 0 },
2342 { "jnoH", { Jb
, BND
, cond_jump_flag
}, 0 },
2343 { "jbH", { Jb
, BND
, cond_jump_flag
}, 0 },
2344 { "jaeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2345 { "jeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2346 { "jneH", { Jb
, BND
, cond_jump_flag
}, 0 },
2347 { "jbeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2348 { "jaH", { Jb
, BND
, cond_jump_flag
}, 0 },
2350 { "jsH", { Jb
, BND
, cond_jump_flag
}, 0 },
2351 { "jnsH", { Jb
, BND
, cond_jump_flag
}, 0 },
2352 { "jpH", { Jb
, BND
, cond_jump_flag
}, 0 },
2353 { "jnpH", { Jb
, BND
, cond_jump_flag
}, 0 },
2354 { "jlH", { Jb
, BND
, cond_jump_flag
}, 0 },
2355 { "jgeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2356 { "jleH", { Jb
, BND
, cond_jump_flag
}, 0 },
2357 { "jgH", { Jb
, BND
, cond_jump_flag
}, 0 },
2359 { REG_TABLE (REG_80
) },
2360 { REG_TABLE (REG_81
) },
2361 { X86_64_TABLE (X86_64_82
) },
2362 { REG_TABLE (REG_83
) },
2363 { "testB", { Eb
, Gb
}, 0 },
2364 { "testS", { Ev
, Gv
}, 0 },
2365 { "xchgB", { Ebh2
, Gb
}, 0 },
2366 { "xchgS", { Evh2
, Gv
}, 0 },
2368 { "movB", { Ebh3
, Gb
}, 0 },
2369 { "movS", { Evh3
, Gv
}, 0 },
2370 { "movB", { Gb
, EbS
}, 0 },
2371 { "movS", { Gv
, EvS
}, 0 },
2372 { "movD", { Sv
, Sw
}, 0 },
2373 { MOD_TABLE (MOD_8D
) },
2374 { "movD", { Sw
, Sv
}, 0 },
2375 { REG_TABLE (REG_8F
) },
2377 { PREFIX_TABLE (PREFIX_90
) },
2378 { "xchgS", { RMeCX
, eAX
}, 0 },
2379 { "xchgS", { RMeDX
, eAX
}, 0 },
2380 { "xchgS", { RMeBX
, eAX
}, 0 },
2381 { "xchgS", { RMeSP
, eAX
}, 0 },
2382 { "xchgS", { RMeBP
, eAX
}, 0 },
2383 { "xchgS", { RMeSI
, eAX
}, 0 },
2384 { "xchgS", { RMeDI
, eAX
}, 0 },
2386 { "cW{t|}R", { XX
}, 0 },
2387 { "cR{t|}O", { XX
}, 0 },
2388 { X86_64_TABLE (X86_64_9A
) },
2389 { Bad_Opcode
}, /* fwait */
2390 { "pushfT", { XX
}, 0 },
2391 { "popfT", { XX
}, 0 },
2392 { "sahf", { XX
}, 0 },
2393 { "lahf", { XX
}, 0 },
2395 { "mov%LB", { AL
, Ob
}, 0 },
2396 { "mov%LS", { eAX
, Ov
}, 0 },
2397 { "mov%LB", { Ob
, AL
}, 0 },
2398 { "mov%LS", { Ov
, eAX
}, 0 },
2399 { "movs{b|}", { Ybr
, Xb
}, 0 },
2400 { "movs{R|}", { Yvr
, Xv
}, 0 },
2401 { "cmps{b|}", { Xb
, Yb
}, 0 },
2402 { "cmps{R|}", { Xv
, Yv
}, 0 },
2404 { "testB", { AL
, Ib
}, 0 },
2405 { "testS", { eAX
, Iv
}, 0 },
2406 { "stosB", { Ybr
, AL
}, 0 },
2407 { "stosS", { Yvr
, eAX
}, 0 },
2408 { "lodsB", { ALr
, Xb
}, 0 },
2409 { "lodsS", { eAXr
, Xv
}, 0 },
2410 { "scasB", { AL
, Yb
}, 0 },
2411 { "scasS", { eAX
, Yv
}, 0 },
2413 { "movB", { RMAL
, Ib
}, 0 },
2414 { "movB", { RMCL
, Ib
}, 0 },
2415 { "movB", { RMDL
, Ib
}, 0 },
2416 { "movB", { RMBL
, Ib
}, 0 },
2417 { "movB", { RMAH
, Ib
}, 0 },
2418 { "movB", { RMCH
, Ib
}, 0 },
2419 { "movB", { RMDH
, Ib
}, 0 },
2420 { "movB", { RMBH
, Ib
}, 0 },
2422 { "mov%LV", { RMeAX
, Iv64
}, 0 },
2423 { "mov%LV", { RMeCX
, Iv64
}, 0 },
2424 { "mov%LV", { RMeDX
, Iv64
}, 0 },
2425 { "mov%LV", { RMeBX
, Iv64
}, 0 },
2426 { "mov%LV", { RMeSP
, Iv64
}, 0 },
2427 { "mov%LV", { RMeBP
, Iv64
}, 0 },
2428 { "mov%LV", { RMeSI
, Iv64
}, 0 },
2429 { "mov%LV", { RMeDI
, Iv64
}, 0 },
2431 { REG_TABLE (REG_C0
) },
2432 { REG_TABLE (REG_C1
) },
2433 { X86_64_TABLE (X86_64_C2
) },
2434 { X86_64_TABLE (X86_64_C3
) },
2435 { X86_64_TABLE (X86_64_C4
) },
2436 { X86_64_TABLE (X86_64_C5
) },
2437 { REG_TABLE (REG_C6
) },
2438 { REG_TABLE (REG_C7
) },
2440 { "enterT", { Iw
, Ib
}, 0 },
2441 { "leaveT", { XX
}, 0 },
2442 { "{l|}ret{|f}P", { Iw
}, 0 },
2443 { "{l|}ret{|f}P", { XX
}, 0 },
2444 { "int3", { XX
}, 0 },
2445 { "int", { Ib
}, 0 },
2446 { X86_64_TABLE (X86_64_CE
) },
2447 { "iret%LP", { XX
}, 0 },
2449 { REG_TABLE (REG_D0
) },
2450 { REG_TABLE (REG_D1
) },
2451 { REG_TABLE (REG_D2
) },
2452 { REG_TABLE (REG_D3
) },
2453 { X86_64_TABLE (X86_64_D4
) },
2454 { X86_64_TABLE (X86_64_D5
) },
2456 { "xlat", { DSBX
}, 0 },
2467 { "loopneFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2468 { "loopeFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2469 { "loopFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2470 { "jEcxzH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2471 { "inB", { AL
, Ib
}, 0 },
2472 { "inG", { zAX
, Ib
}, 0 },
2473 { "outB", { Ib
, AL
}, 0 },
2474 { "outG", { Ib
, zAX
}, 0 },
2476 { X86_64_TABLE (X86_64_E8
) },
2477 { X86_64_TABLE (X86_64_E9
) },
2478 { X86_64_TABLE (X86_64_EA
) },
2479 { "jmp", { Jb
, BND
}, 0 },
2480 { "inB", { AL
, indirDX
}, 0 },
2481 { "inG", { zAX
, indirDX
}, 0 },
2482 { "outB", { indirDX
, AL
}, 0 },
2483 { "outG", { indirDX
, zAX
}, 0 },
2485 { Bad_Opcode
}, /* lock prefix */
2486 { "icebp", { XX
}, 0 },
2487 { Bad_Opcode
}, /* repne */
2488 { Bad_Opcode
}, /* repz */
2489 { "hlt", { XX
}, 0 },
2490 { "cmc", { XX
}, 0 },
2491 { REG_TABLE (REG_F6
) },
2492 { REG_TABLE (REG_F7
) },
2494 { "clc", { XX
}, 0 },
2495 { "stc", { XX
}, 0 },
2496 { "cli", { XX
}, 0 },
2497 { "sti", { XX
}, 0 },
2498 { "cld", { XX
}, 0 },
2499 { "std", { XX
}, 0 },
2500 { REG_TABLE (REG_FE
) },
2501 { REG_TABLE (REG_FF
) },
2504 static const struct dis386 dis386_twobyte
[] = {
2506 { REG_TABLE (REG_0F00
) },
2507 { REG_TABLE (REG_0F01
) },
2508 { "larS", { Gv
, Ew
}, 0 },
2509 { "lslS", { Gv
, Ew
}, 0 },
2511 { "syscall", { XX
}, 0 },
2512 { "clts", { XX
}, 0 },
2513 { "sysret%LQ", { XX
}, 0 },
2515 { "invd", { XX
}, 0 },
2516 { PREFIX_TABLE (PREFIX_0F09
) },
2518 { "ud2", { XX
}, 0 },
2520 { REG_TABLE (REG_0F0D
) },
2521 { "femms", { XX
}, 0 },
2522 { "", { MX
, EM
, OPSUF
}, 0 }, /* See OP_3DNowSuffix. */
2524 { PREFIX_TABLE (PREFIX_0F10
) },
2525 { PREFIX_TABLE (PREFIX_0F11
) },
2526 { PREFIX_TABLE (PREFIX_0F12
) },
2527 { MOD_TABLE (MOD_0F13
) },
2528 { "unpcklpX", { XM
, EXx
}, PREFIX_OPCODE
},
2529 { "unpckhpX", { XM
, EXx
}, PREFIX_OPCODE
},
2530 { PREFIX_TABLE (PREFIX_0F16
) },
2531 { MOD_TABLE (MOD_0F17
) },
2533 { REG_TABLE (REG_0F18
) },
2534 { "nopQ", { Ev
}, 0 },
2535 { PREFIX_TABLE (PREFIX_0F1A
) },
2536 { PREFIX_TABLE (PREFIX_0F1B
) },
2537 { PREFIX_TABLE (PREFIX_0F1C
) },
2538 { "nopQ", { Ev
}, 0 },
2539 { PREFIX_TABLE (PREFIX_0F1E
) },
2540 { "nopQ", { Ev
}, 0 },
2542 { "movZ", { Rm
, Cm
}, 0 },
2543 { "movZ", { Rm
, Dm
}, 0 },
2544 { "movZ", { Cm
, Rm
}, 0 },
2545 { "movZ", { Dm
, Rm
}, 0 },
2546 { MOD_TABLE (MOD_0F24
) },
2548 { MOD_TABLE (MOD_0F26
) },
2551 { "movapX", { XM
, EXx
}, PREFIX_OPCODE
},
2552 { "movapX", { EXxS
, XM
}, PREFIX_OPCODE
},
2553 { PREFIX_TABLE (PREFIX_0F2A
) },
2554 { PREFIX_TABLE (PREFIX_0F2B
) },
2555 { PREFIX_TABLE (PREFIX_0F2C
) },
2556 { PREFIX_TABLE (PREFIX_0F2D
) },
2557 { PREFIX_TABLE (PREFIX_0F2E
) },
2558 { PREFIX_TABLE (PREFIX_0F2F
) },
2560 { "wrmsr", { XX
}, 0 },
2561 { "rdtsc", { XX
}, 0 },
2562 { "rdmsr", { XX
}, 0 },
2563 { "rdpmc", { XX
}, 0 },
2564 { "sysenter", { SEP
}, 0 },
2565 { "sysexit", { SEP
}, 0 },
2567 { "getsec", { XX
}, 0 },
2569 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38
, PREFIX_OPCODE
) },
2571 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A
, PREFIX_OPCODE
) },
2578 { "cmovoS", { Gv
, Ev
}, 0 },
2579 { "cmovnoS", { Gv
, Ev
}, 0 },
2580 { "cmovbS", { Gv
, Ev
}, 0 },
2581 { "cmovaeS", { Gv
, Ev
}, 0 },
2582 { "cmoveS", { Gv
, Ev
}, 0 },
2583 { "cmovneS", { Gv
, Ev
}, 0 },
2584 { "cmovbeS", { Gv
, Ev
}, 0 },
2585 { "cmovaS", { Gv
, Ev
}, 0 },
2587 { "cmovsS", { Gv
, Ev
}, 0 },
2588 { "cmovnsS", { Gv
, Ev
}, 0 },
2589 { "cmovpS", { Gv
, Ev
}, 0 },
2590 { "cmovnpS", { Gv
, Ev
}, 0 },
2591 { "cmovlS", { Gv
, Ev
}, 0 },
2592 { "cmovgeS", { Gv
, Ev
}, 0 },
2593 { "cmovleS", { Gv
, Ev
}, 0 },
2594 { "cmovgS", { Gv
, Ev
}, 0 },
2596 { MOD_TABLE (MOD_0F50
) },
2597 { PREFIX_TABLE (PREFIX_0F51
) },
2598 { PREFIX_TABLE (PREFIX_0F52
) },
2599 { PREFIX_TABLE (PREFIX_0F53
) },
2600 { "andpX", { XM
, EXx
}, PREFIX_OPCODE
},
2601 { "andnpX", { XM
, EXx
}, PREFIX_OPCODE
},
2602 { "orpX", { XM
, EXx
}, PREFIX_OPCODE
},
2603 { "xorpX", { XM
, EXx
}, PREFIX_OPCODE
},
2605 { PREFIX_TABLE (PREFIX_0F58
) },
2606 { PREFIX_TABLE (PREFIX_0F59
) },
2607 { PREFIX_TABLE (PREFIX_0F5A
) },
2608 { PREFIX_TABLE (PREFIX_0F5B
) },
2609 { PREFIX_TABLE (PREFIX_0F5C
) },
2610 { PREFIX_TABLE (PREFIX_0F5D
) },
2611 { PREFIX_TABLE (PREFIX_0F5E
) },
2612 { PREFIX_TABLE (PREFIX_0F5F
) },
2614 { PREFIX_TABLE (PREFIX_0F60
) },
2615 { PREFIX_TABLE (PREFIX_0F61
) },
2616 { PREFIX_TABLE (PREFIX_0F62
) },
2617 { "packsswb", { MX
, EM
}, PREFIX_OPCODE
},
2618 { "pcmpgtb", { MX
, EM
}, PREFIX_OPCODE
},
2619 { "pcmpgtw", { MX
, EM
}, PREFIX_OPCODE
},
2620 { "pcmpgtd", { MX
, EM
}, PREFIX_OPCODE
},
2621 { "packuswb", { MX
, EM
}, PREFIX_OPCODE
},
2623 { "punpckhbw", { MX
, EM
}, PREFIX_OPCODE
},
2624 { "punpckhwd", { MX
, EM
}, PREFIX_OPCODE
},
2625 { "punpckhdq", { MX
, EM
}, PREFIX_OPCODE
},
2626 { "packssdw", { MX
, EM
}, PREFIX_OPCODE
},
2627 { PREFIX_TABLE (PREFIX_0F6C
) },
2628 { PREFIX_TABLE (PREFIX_0F6D
) },
2629 { "movK", { MX
, Edq
}, PREFIX_OPCODE
},
2630 { PREFIX_TABLE (PREFIX_0F6F
) },
2632 { PREFIX_TABLE (PREFIX_0F70
) },
2633 { REG_TABLE (REG_0F71
) },
2634 { REG_TABLE (REG_0F72
) },
2635 { REG_TABLE (REG_0F73
) },
2636 { "pcmpeqb", { MX
, EM
}, PREFIX_OPCODE
},
2637 { "pcmpeqw", { MX
, EM
}, PREFIX_OPCODE
},
2638 { "pcmpeqd", { MX
, EM
}, PREFIX_OPCODE
},
2639 { "emms", { XX
}, PREFIX_OPCODE
},
2641 { PREFIX_TABLE (PREFIX_0F78
) },
2642 { PREFIX_TABLE (PREFIX_0F79
) },
2645 { PREFIX_TABLE (PREFIX_0F7C
) },
2646 { PREFIX_TABLE (PREFIX_0F7D
) },
2647 { PREFIX_TABLE (PREFIX_0F7E
) },
2648 { PREFIX_TABLE (PREFIX_0F7F
) },
2650 { "joH", { Jv
, BND
, cond_jump_flag
}, 0 },
2651 { "jnoH", { Jv
, BND
, cond_jump_flag
}, 0 },
2652 { "jbH", { Jv
, BND
, cond_jump_flag
}, 0 },
2653 { "jaeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2654 { "jeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2655 { "jneH", { Jv
, BND
, cond_jump_flag
}, 0 },
2656 { "jbeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2657 { "jaH", { Jv
, BND
, cond_jump_flag
}, 0 },
2659 { "jsH", { Jv
, BND
, cond_jump_flag
}, 0 },
2660 { "jnsH", { Jv
, BND
, cond_jump_flag
}, 0 },
2661 { "jpH", { Jv
, BND
, cond_jump_flag
}, 0 },
2662 { "jnpH", { Jv
, BND
, cond_jump_flag
}, 0 },
2663 { "jlH", { Jv
, BND
, cond_jump_flag
}, 0 },
2664 { "jgeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2665 { "jleH", { Jv
, BND
, cond_jump_flag
}, 0 },
2666 { "jgH", { Jv
, BND
, cond_jump_flag
}, 0 },
2668 { "seto", { Eb
}, 0 },
2669 { "setno", { Eb
}, 0 },
2670 { "setb", { Eb
}, 0 },
2671 { "setae", { Eb
}, 0 },
2672 { "sete", { Eb
}, 0 },
2673 { "setne", { Eb
}, 0 },
2674 { "setbe", { Eb
}, 0 },
2675 { "seta", { Eb
}, 0 },
2677 { "sets", { Eb
}, 0 },
2678 { "setns", { Eb
}, 0 },
2679 { "setp", { Eb
}, 0 },
2680 { "setnp", { Eb
}, 0 },
2681 { "setl", { Eb
}, 0 },
2682 { "setge", { Eb
}, 0 },
2683 { "setle", { Eb
}, 0 },
2684 { "setg", { Eb
}, 0 },
2686 { "pushT", { fs
}, 0 },
2687 { "popT", { fs
}, 0 },
2688 { "cpuid", { XX
}, 0 },
2689 { "btS", { Ev
, Gv
}, 0 },
2690 { "shldS", { Ev
, Gv
, Ib
}, 0 },
2691 { "shldS", { Ev
, Gv
, CL
}, 0 },
2692 { REG_TABLE (REG_0FA6
) },
2693 { REG_TABLE (REG_0FA7
) },
2695 { "pushT", { gs
}, 0 },
2696 { "popT", { gs
}, 0 },
2697 { "rsm", { XX
}, 0 },
2698 { "btsS", { Evh1
, Gv
}, 0 },
2699 { "shrdS", { Ev
, Gv
, Ib
}, 0 },
2700 { "shrdS", { Ev
, Gv
, CL
}, 0 },
2701 { REG_TABLE (REG_0FAE
) },
2702 { "imulS", { Gv
, Ev
}, 0 },
2704 { "cmpxchgB", { Ebh1
, Gb
}, 0 },
2705 { "cmpxchgS", { Evh1
, Gv
}, 0 },
2706 { MOD_TABLE (MOD_0FB2
) },
2707 { "btrS", { Evh1
, Gv
}, 0 },
2708 { MOD_TABLE (MOD_0FB4
) },
2709 { MOD_TABLE (MOD_0FB5
) },
2710 { "movz{bR|x}", { Gv
, Eb
}, 0 },
2711 { "movz{wR|x}", { Gv
, Ew
}, 0 }, /* yes, there really is movzww ! */
2713 { PREFIX_TABLE (PREFIX_0FB8
) },
2714 { "ud1S", { Gv
, Ev
}, 0 },
2715 { REG_TABLE (REG_0FBA
) },
2716 { "btcS", { Evh1
, Gv
}, 0 },
2717 { PREFIX_TABLE (PREFIX_0FBC
) },
2718 { PREFIX_TABLE (PREFIX_0FBD
) },
2719 { "movs{bR|x}", { Gv
, Eb
}, 0 },
2720 { "movs{wR|x}", { Gv
, Ew
}, 0 }, /* yes, there really is movsww ! */
2722 { "xaddB", { Ebh1
, Gb
}, 0 },
2723 { "xaddS", { Evh1
, Gv
}, 0 },
2724 { PREFIX_TABLE (PREFIX_0FC2
) },
2725 { MOD_TABLE (MOD_0FC3
) },
2726 { "pinsrw", { MX
, Edqw
, Ib
}, PREFIX_OPCODE
},
2727 { "pextrw", { Gdq
, MS
, Ib
}, PREFIX_OPCODE
},
2728 { "shufpX", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
2729 { REG_TABLE (REG_0FC7
) },
2731 { "bswap", { RMeAX
}, 0 },
2732 { "bswap", { RMeCX
}, 0 },
2733 { "bswap", { RMeDX
}, 0 },
2734 { "bswap", { RMeBX
}, 0 },
2735 { "bswap", { RMeSP
}, 0 },
2736 { "bswap", { RMeBP
}, 0 },
2737 { "bswap", { RMeSI
}, 0 },
2738 { "bswap", { RMeDI
}, 0 },
2740 { PREFIX_TABLE (PREFIX_0FD0
) },
2741 { "psrlw", { MX
, EM
}, PREFIX_OPCODE
},
2742 { "psrld", { MX
, EM
}, PREFIX_OPCODE
},
2743 { "psrlq", { MX
, EM
}, PREFIX_OPCODE
},
2744 { "paddq", { MX
, EM
}, PREFIX_OPCODE
},
2745 { "pmullw", { MX
, EM
}, PREFIX_OPCODE
},
2746 { PREFIX_TABLE (PREFIX_0FD6
) },
2747 { MOD_TABLE (MOD_0FD7
) },
2749 { "psubusb", { MX
, EM
}, PREFIX_OPCODE
},
2750 { "psubusw", { MX
, EM
}, PREFIX_OPCODE
},
2751 { "pminub", { MX
, EM
}, PREFIX_OPCODE
},
2752 { "pand", { MX
, EM
}, PREFIX_OPCODE
},
2753 { "paddusb", { MX
, EM
}, PREFIX_OPCODE
},
2754 { "paddusw", { MX
, EM
}, PREFIX_OPCODE
},
2755 { "pmaxub", { MX
, EM
}, PREFIX_OPCODE
},
2756 { "pandn", { MX
, EM
}, PREFIX_OPCODE
},
2758 { "pavgb", { MX
, EM
}, PREFIX_OPCODE
},
2759 { "psraw", { MX
, EM
}, PREFIX_OPCODE
},
2760 { "psrad", { MX
, EM
}, PREFIX_OPCODE
},
2761 { "pavgw", { MX
, EM
}, PREFIX_OPCODE
},
2762 { "pmulhuw", { MX
, EM
}, PREFIX_OPCODE
},
2763 { "pmulhw", { MX
, EM
}, PREFIX_OPCODE
},
2764 { PREFIX_TABLE (PREFIX_0FE6
) },
2765 { PREFIX_TABLE (PREFIX_0FE7
) },
2767 { "psubsb", { MX
, EM
}, PREFIX_OPCODE
},
2768 { "psubsw", { MX
, EM
}, PREFIX_OPCODE
},
2769 { "pminsw", { MX
, EM
}, PREFIX_OPCODE
},
2770 { "por", { MX
, EM
}, PREFIX_OPCODE
},
2771 { "paddsb", { MX
, EM
}, PREFIX_OPCODE
},
2772 { "paddsw", { MX
, EM
}, PREFIX_OPCODE
},
2773 { "pmaxsw", { MX
, EM
}, PREFIX_OPCODE
},
2774 { "pxor", { MX
, EM
}, PREFIX_OPCODE
},
2776 { PREFIX_TABLE (PREFIX_0FF0
) },
2777 { "psllw", { MX
, EM
}, PREFIX_OPCODE
},
2778 { "pslld", { MX
, EM
}, PREFIX_OPCODE
},
2779 { "psllq", { MX
, EM
}, PREFIX_OPCODE
},
2780 { "pmuludq", { MX
, EM
}, PREFIX_OPCODE
},
2781 { "pmaddwd", { MX
, EM
}, PREFIX_OPCODE
},
2782 { "psadbw", { MX
, EM
}, PREFIX_OPCODE
},
2783 { PREFIX_TABLE (PREFIX_0FF7
) },
2785 { "psubb", { MX
, EM
}, PREFIX_OPCODE
},
2786 { "psubw", { MX
, EM
}, PREFIX_OPCODE
},
2787 { "psubd", { MX
, EM
}, PREFIX_OPCODE
},
2788 { "psubq", { MX
, EM
}, PREFIX_OPCODE
},
2789 { "paddb", { MX
, EM
}, PREFIX_OPCODE
},
2790 { "paddw", { MX
, EM
}, PREFIX_OPCODE
},
2791 { "paddd", { MX
, EM
}, PREFIX_OPCODE
},
2792 { "ud0S", { Gv
, Ev
}, 0 },
2795 static const unsigned char onebyte_has_modrm
[256] = {
2796 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2797 /* ------------------------------- */
2798 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2799 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2800 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2801 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2802 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2803 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2804 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2805 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2806 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2807 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2808 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2809 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2810 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2811 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2812 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2813 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
2814 /* ------------------------------- */
2815 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2818 static const unsigned char twobyte_has_modrm
[256] = {
2819 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2820 /* ------------------------------- */
2821 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2822 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2823 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2824 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2825 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2826 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2827 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2828 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2829 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2830 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2831 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2832 /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2833 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2834 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2835 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2836 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 /* ff */
2837 /* ------------------------------- */
2838 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2841 static char obuf
[100];
2843 static char *mnemonicendp
;
2844 static char scratchbuf
[100];
2845 static unsigned char *start_codep
;
2846 static unsigned char *insn_codep
;
2847 static unsigned char *codep
;
2848 static unsigned char *end_codep
;
2849 static int last_lock_prefix
;
2850 static int last_repz_prefix
;
2851 static int last_repnz_prefix
;
2852 static int last_data_prefix
;
2853 static int last_addr_prefix
;
2854 static int last_rex_prefix
;
2855 static int last_seg_prefix
;
2856 static int fwait_prefix
;
2857 /* The active segment register prefix. */
2858 static int active_seg_prefix
;
2859 #define MAX_CODE_LENGTH 15
2860 /* We can up to 14 prefixes since the maximum instruction length is
2862 static int all_prefixes
[MAX_CODE_LENGTH
- 1];
2863 static disassemble_info
*the_info
;
2871 static unsigned char need_modrm
;
2881 int register_specifier
;
2888 int mask_register_specifier
;
2894 static unsigned char need_vex
;
2895 static unsigned char need_vex_reg
;
2896 static unsigned char vex_w_done
;
2904 /* If we are accessing mod/rm/reg without need_modrm set, then the
2905 values are stale. Hitting this abort likely indicates that you
2906 need to update onebyte_has_modrm or twobyte_has_modrm. */
2907 #define MODRM_CHECK if (!need_modrm) abort ()
2909 static const char **names64
;
2910 static const char **names32
;
2911 static const char **names16
;
2912 static const char **names8
;
2913 static const char **names8rex
;
2914 static const char **names_seg
;
2915 static const char *index64
;
2916 static const char *index32
;
2917 static const char **index16
;
2918 static const char **names_bnd
;
2920 static const char *intel_names64
[] = {
2921 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2922 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2924 static const char *intel_names32
[] = {
2925 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2926 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2928 static const char *intel_names16
[] = {
2929 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2930 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2932 static const char *intel_names8
[] = {
2933 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2935 static const char *intel_names8rex
[] = {
2936 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2937 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2939 static const char *intel_names_seg
[] = {
2940 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2942 static const char *intel_index64
= "riz";
2943 static const char *intel_index32
= "eiz";
2944 static const char *intel_index16
[] = {
2945 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2948 static const char *att_names64
[] = {
2949 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2950 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2952 static const char *att_names32
[] = {
2953 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2954 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2956 static const char *att_names16
[] = {
2957 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2958 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2960 static const char *att_names8
[] = {
2961 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2963 static const char *att_names8rex
[] = {
2964 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2965 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2967 static const char *att_names_seg
[] = {
2968 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2970 static const char *att_index64
= "%riz";
2971 static const char *att_index32
= "%eiz";
2972 static const char *att_index16
[] = {
2973 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2976 static const char **names_mm
;
2977 static const char *intel_names_mm
[] = {
2978 "mm0", "mm1", "mm2", "mm3",
2979 "mm4", "mm5", "mm6", "mm7"
2981 static const char *att_names_mm
[] = {
2982 "%mm0", "%mm1", "%mm2", "%mm3",
2983 "%mm4", "%mm5", "%mm6", "%mm7"
2986 static const char *intel_names_bnd
[] = {
2987 "bnd0", "bnd1", "bnd2", "bnd3"
2990 static const char *att_names_bnd
[] = {
2991 "%bnd0", "%bnd1", "%bnd2", "%bnd3"
2994 static const char **names_xmm
;
2995 static const char *intel_names_xmm
[] = {
2996 "xmm0", "xmm1", "xmm2", "xmm3",
2997 "xmm4", "xmm5", "xmm6", "xmm7",
2998 "xmm8", "xmm9", "xmm10", "xmm11",
2999 "xmm12", "xmm13", "xmm14", "xmm15",
3000 "xmm16", "xmm17", "xmm18", "xmm19",
3001 "xmm20", "xmm21", "xmm22", "xmm23",
3002 "xmm24", "xmm25", "xmm26", "xmm27",
3003 "xmm28", "xmm29", "xmm30", "xmm31"
3005 static const char *att_names_xmm
[] = {
3006 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3007 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3008 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3009 "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3010 "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3011 "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3012 "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3013 "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3016 static const char **names_ymm
;
3017 static const char *intel_names_ymm
[] = {
3018 "ymm0", "ymm1", "ymm2", "ymm3",
3019 "ymm4", "ymm5", "ymm6", "ymm7",
3020 "ymm8", "ymm9", "ymm10", "ymm11",
3021 "ymm12", "ymm13", "ymm14", "ymm15",
3022 "ymm16", "ymm17", "ymm18", "ymm19",
3023 "ymm20", "ymm21", "ymm22", "ymm23",
3024 "ymm24", "ymm25", "ymm26", "ymm27",
3025 "ymm28", "ymm29", "ymm30", "ymm31"
3027 static const char *att_names_ymm
[] = {
3028 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3029 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3030 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3031 "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3032 "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3033 "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3034 "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3035 "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3038 static const char **names_zmm
;
3039 static const char *intel_names_zmm
[] = {
3040 "zmm0", "zmm1", "zmm2", "zmm3",
3041 "zmm4", "zmm5", "zmm6", "zmm7",
3042 "zmm8", "zmm9", "zmm10", "zmm11",
3043 "zmm12", "zmm13", "zmm14", "zmm15",
3044 "zmm16", "zmm17", "zmm18", "zmm19",
3045 "zmm20", "zmm21", "zmm22", "zmm23",
3046 "zmm24", "zmm25", "zmm26", "zmm27",
3047 "zmm28", "zmm29", "zmm30", "zmm31"
3049 static const char *att_names_zmm
[] = {
3050 "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3051 "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3052 "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3053 "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3054 "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3055 "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3056 "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3057 "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3060 static const char **names_mask
;
3061 static const char *intel_names_mask
[] = {
3062 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3064 static const char *att_names_mask
[] = {
3065 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3068 static const char *names_rounding
[] =
3076 static const struct dis386 reg_table
[][8] = {
3079 { "addA", { Ebh1
, Ib
}, 0 },
3080 { "orA", { Ebh1
, Ib
}, 0 },
3081 { "adcA", { Ebh1
, Ib
}, 0 },
3082 { "sbbA", { Ebh1
, Ib
}, 0 },
3083 { "andA", { Ebh1
, Ib
}, 0 },
3084 { "subA", { Ebh1
, Ib
}, 0 },
3085 { "xorA", { Ebh1
, Ib
}, 0 },
3086 { "cmpA", { Eb
, Ib
}, 0 },
3090 { "addQ", { Evh1
, Iv
}, 0 },
3091 { "orQ", { Evh1
, Iv
}, 0 },
3092 { "adcQ", { Evh1
, Iv
}, 0 },
3093 { "sbbQ", { Evh1
, Iv
}, 0 },
3094 { "andQ", { Evh1
, Iv
}, 0 },
3095 { "subQ", { Evh1
, Iv
}, 0 },
3096 { "xorQ", { Evh1
, Iv
}, 0 },
3097 { "cmpQ", { Ev
, Iv
}, 0 },
3101 { "addQ", { Evh1
, sIb
}, 0 },
3102 { "orQ", { Evh1
, sIb
}, 0 },
3103 { "adcQ", { Evh1
, sIb
}, 0 },
3104 { "sbbQ", { Evh1
, sIb
}, 0 },
3105 { "andQ", { Evh1
, sIb
}, 0 },
3106 { "subQ", { Evh1
, sIb
}, 0 },
3107 { "xorQ", { Evh1
, sIb
}, 0 },
3108 { "cmpQ", { Ev
, sIb
}, 0 },
3112 { "popU", { stackEv
}, 0 },
3113 { XOP_8F_TABLE (XOP_09
) },
3117 { XOP_8F_TABLE (XOP_09
) },
3121 { "rolA", { Eb
, Ib
}, 0 },
3122 { "rorA", { Eb
, Ib
}, 0 },
3123 { "rclA", { Eb
, Ib
}, 0 },
3124 { "rcrA", { Eb
, Ib
}, 0 },
3125 { "shlA", { Eb
, Ib
}, 0 },
3126 { "shrA", { Eb
, Ib
}, 0 },
3127 { "shlA", { Eb
, Ib
}, 0 },
3128 { "sarA", { Eb
, Ib
}, 0 },
3132 { "rolQ", { Ev
, Ib
}, 0 },
3133 { "rorQ", { Ev
, Ib
}, 0 },
3134 { "rclQ", { Ev
, Ib
}, 0 },
3135 { "rcrQ", { Ev
, Ib
}, 0 },
3136 { "shlQ", { Ev
, Ib
}, 0 },
3137 { "shrQ", { Ev
, Ib
}, 0 },
3138 { "shlQ", { Ev
, Ib
}, 0 },
3139 { "sarQ", { Ev
, Ib
}, 0 },
3143 { "movA", { Ebh3
, Ib
}, 0 },
3150 { MOD_TABLE (MOD_C6_REG_7
) },
3154 { "movQ", { Evh3
, Iv
}, 0 },
3161 { MOD_TABLE (MOD_C7_REG_7
) },
3165 { "rolA", { Eb
, I1
}, 0 },
3166 { "rorA", { Eb
, I1
}, 0 },
3167 { "rclA", { Eb
, I1
}, 0 },
3168 { "rcrA", { Eb
, I1
}, 0 },
3169 { "shlA", { Eb
, I1
}, 0 },
3170 { "shrA", { Eb
, I1
}, 0 },
3171 { "shlA", { Eb
, I1
}, 0 },
3172 { "sarA", { Eb
, I1
}, 0 },
3176 { "rolQ", { Ev
, I1
}, 0 },
3177 { "rorQ", { Ev
, I1
}, 0 },
3178 { "rclQ", { Ev
, I1
}, 0 },
3179 { "rcrQ", { Ev
, I1
}, 0 },
3180 { "shlQ", { Ev
, I1
}, 0 },
3181 { "shrQ", { Ev
, I1
}, 0 },
3182 { "shlQ", { Ev
, I1
}, 0 },
3183 { "sarQ", { Ev
, I1
}, 0 },
3187 { "rolA", { Eb
, CL
}, 0 },
3188 { "rorA", { Eb
, CL
}, 0 },
3189 { "rclA", { Eb
, CL
}, 0 },
3190 { "rcrA", { Eb
, CL
}, 0 },
3191 { "shlA", { Eb
, CL
}, 0 },
3192 { "shrA", { Eb
, CL
}, 0 },
3193 { "shlA", { Eb
, CL
}, 0 },
3194 { "sarA", { Eb
, CL
}, 0 },
3198 { "rolQ", { Ev
, CL
}, 0 },
3199 { "rorQ", { Ev
, CL
}, 0 },
3200 { "rclQ", { Ev
, CL
}, 0 },
3201 { "rcrQ", { Ev
, CL
}, 0 },
3202 { "shlQ", { Ev
, CL
}, 0 },
3203 { "shrQ", { Ev
, CL
}, 0 },
3204 { "shlQ", { Ev
, CL
}, 0 },
3205 { "sarQ", { Ev
, CL
}, 0 },
3209 { "testA", { Eb
, Ib
}, 0 },
3210 { "testA", { Eb
, Ib
}, 0 },
3211 { "notA", { Ebh1
}, 0 },
3212 { "negA", { Ebh1
}, 0 },
3213 { "mulA", { Eb
}, 0 }, /* Don't print the implicit %al register, */
3214 { "imulA", { Eb
}, 0 }, /* to distinguish these opcodes from other */
3215 { "divA", { Eb
}, 0 }, /* mul/imul opcodes. Do the same for div */
3216 { "idivA", { Eb
}, 0 }, /* and idiv for consistency. */
3220 { "testQ", { Ev
, Iv
}, 0 },
3221 { "testQ", { Ev
, Iv
}, 0 },
3222 { "notQ", { Evh1
}, 0 },
3223 { "negQ", { Evh1
}, 0 },
3224 { "mulQ", { Ev
}, 0 }, /* Don't print the implicit register. */
3225 { "imulQ", { Ev
}, 0 },
3226 { "divQ", { Ev
}, 0 },
3227 { "idivQ", { Ev
}, 0 },
3231 { "incA", { Ebh1
}, 0 },
3232 { "decA", { Ebh1
}, 0 },
3236 { "incQ", { Evh1
}, 0 },
3237 { "decQ", { Evh1
}, 0 },
3238 { "call{&|}", { NOTRACK
, indirEv
, BND
}, 0 },
3239 { MOD_TABLE (MOD_FF_REG_3
) },
3240 { "jmp{&|}", { NOTRACK
, indirEv
, BND
}, 0 },
3241 { MOD_TABLE (MOD_FF_REG_5
) },
3242 { "pushU", { stackEv
}, 0 },
3247 { "sldtD", { Sv
}, 0 },
3248 { "strD", { Sv
}, 0 },
3249 { "lldt", { Ew
}, 0 },
3250 { "ltr", { Ew
}, 0 },
3251 { "verr", { Ew
}, 0 },
3252 { "verw", { Ew
}, 0 },
3258 { MOD_TABLE (MOD_0F01_REG_0
) },
3259 { MOD_TABLE (MOD_0F01_REG_1
) },
3260 { MOD_TABLE (MOD_0F01_REG_2
) },
3261 { MOD_TABLE (MOD_0F01_REG_3
) },
3262 { "smswD", { Sv
}, 0 },
3263 { MOD_TABLE (MOD_0F01_REG_5
) },
3264 { "lmsw", { Ew
}, 0 },
3265 { MOD_TABLE (MOD_0F01_REG_7
) },
3269 { "prefetch", { Mb
}, 0 },
3270 { "prefetchw", { Mb
}, 0 },
3271 { "prefetchwt1", { Mb
}, 0 },
3272 { "prefetch", { Mb
}, 0 },
3273 { "prefetch", { Mb
}, 0 },
3274 { "prefetch", { Mb
}, 0 },
3275 { "prefetch", { Mb
}, 0 },
3276 { "prefetch", { Mb
}, 0 },
3280 { MOD_TABLE (MOD_0F18_REG_0
) },
3281 { MOD_TABLE (MOD_0F18_REG_1
) },
3282 { MOD_TABLE (MOD_0F18_REG_2
) },
3283 { MOD_TABLE (MOD_0F18_REG_3
) },
3284 { MOD_TABLE (MOD_0F18_REG_4
) },
3285 { MOD_TABLE (MOD_0F18_REG_5
) },
3286 { MOD_TABLE (MOD_0F18_REG_6
) },
3287 { MOD_TABLE (MOD_0F18_REG_7
) },
3289 /* REG_0F1C_P_0_MOD_0 */
3291 { "cldemote", { Mb
}, 0 },
3292 { "nopQ", { Ev
}, 0 },
3293 { "nopQ", { Ev
}, 0 },
3294 { "nopQ", { Ev
}, 0 },
3295 { "nopQ", { Ev
}, 0 },
3296 { "nopQ", { Ev
}, 0 },
3297 { "nopQ", { Ev
}, 0 },
3298 { "nopQ", { Ev
}, 0 },
3300 /* REG_0F1E_P_1_MOD_3 */
3302 { "nopQ", { Ev
}, 0 },
3303 { "rdsspK", { Rdq
}, PREFIX_OPCODE
},
3304 { "nopQ", { Ev
}, 0 },
3305 { "nopQ", { Ev
}, 0 },
3306 { "nopQ", { Ev
}, 0 },
3307 { "nopQ", { Ev
}, 0 },
3308 { "nopQ", { Ev
}, 0 },
3309 { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7
) },
3315 { MOD_TABLE (MOD_0F71_REG_2
) },
3317 { MOD_TABLE (MOD_0F71_REG_4
) },
3319 { MOD_TABLE (MOD_0F71_REG_6
) },
3325 { MOD_TABLE (MOD_0F72_REG_2
) },
3327 { MOD_TABLE (MOD_0F72_REG_4
) },
3329 { MOD_TABLE (MOD_0F72_REG_6
) },
3335 { MOD_TABLE (MOD_0F73_REG_2
) },
3336 { MOD_TABLE (MOD_0F73_REG_3
) },
3339 { MOD_TABLE (MOD_0F73_REG_6
) },
3340 { MOD_TABLE (MOD_0F73_REG_7
) },
3344 { "montmul", { { OP_0f07
, 0 } }, 0 },
3345 { "xsha1", { { OP_0f07
, 0 } }, 0 },
3346 { "xsha256", { { OP_0f07
, 0 } }, 0 },
3350 { "xstore-rng", { { OP_0f07
, 0 } }, 0 },
3351 { "xcrypt-ecb", { { OP_0f07
, 0 } }, 0 },
3352 { "xcrypt-cbc", { { OP_0f07
, 0 } }, 0 },
3353 { "xcrypt-ctr", { { OP_0f07
, 0 } }, 0 },
3354 { "xcrypt-cfb", { { OP_0f07
, 0 } }, 0 },
3355 { "xcrypt-ofb", { { OP_0f07
, 0 } }, 0 },
3359 { MOD_TABLE (MOD_0FAE_REG_0
) },
3360 { MOD_TABLE (MOD_0FAE_REG_1
) },
3361 { MOD_TABLE (MOD_0FAE_REG_2
) },
3362 { MOD_TABLE (MOD_0FAE_REG_3
) },
3363 { MOD_TABLE (MOD_0FAE_REG_4
) },
3364 { MOD_TABLE (MOD_0FAE_REG_5
) },
3365 { MOD_TABLE (MOD_0FAE_REG_6
) },
3366 { MOD_TABLE (MOD_0FAE_REG_7
) },
3374 { "btQ", { Ev
, Ib
}, 0 },
3375 { "btsQ", { Evh1
, Ib
}, 0 },
3376 { "btrQ", { Evh1
, Ib
}, 0 },
3377 { "btcQ", { Evh1
, Ib
}, 0 },
3382 { "cmpxchg8b", { { CMPXCHG8B_Fixup
, q_mode
} }, 0 },
3384 { MOD_TABLE (MOD_0FC7_REG_3
) },
3385 { MOD_TABLE (MOD_0FC7_REG_4
) },
3386 { MOD_TABLE (MOD_0FC7_REG_5
) },
3387 { MOD_TABLE (MOD_0FC7_REG_6
) },
3388 { MOD_TABLE (MOD_0FC7_REG_7
) },
3394 { MOD_TABLE (MOD_VEX_0F71_REG_2
) },
3396 { MOD_TABLE (MOD_VEX_0F71_REG_4
) },
3398 { MOD_TABLE (MOD_VEX_0F71_REG_6
) },
3404 { MOD_TABLE (MOD_VEX_0F72_REG_2
) },
3406 { MOD_TABLE (MOD_VEX_0F72_REG_4
) },
3408 { MOD_TABLE (MOD_VEX_0F72_REG_6
) },
3414 { MOD_TABLE (MOD_VEX_0F73_REG_2
) },
3415 { MOD_TABLE (MOD_VEX_0F73_REG_3
) },
3418 { MOD_TABLE (MOD_VEX_0F73_REG_6
) },
3419 { MOD_TABLE (MOD_VEX_0F73_REG_7
) },
3425 { MOD_TABLE (MOD_VEX_0FAE_REG_2
) },
3426 { MOD_TABLE (MOD_VEX_0FAE_REG_3
) },
3428 /* REG_VEX_0F38F3 */
3431 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1
) },
3432 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2
) },
3433 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3
) },
3437 { "llwpcb", { { OP_LWPCB_E
, 0 } }, 0 },
3438 { "slwpcb", { { OP_LWPCB_E
, 0 } }, 0 },
3442 { "lwpins", { { OP_LWP_E
, 0 }, Ed
, Id
}, 0 },
3443 { "lwpval", { { OP_LWP_E
, 0 }, Ed
, Id
}, 0 },
3445 /* REG_XOP_TBM_01 */
3448 { "blcfill", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3449 { "blsfill", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3450 { "blcs", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3451 { "tzmsk", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3452 { "blcic", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3453 { "blsic", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3454 { "t1mskc", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3456 /* REG_XOP_TBM_02 */
3459 { "blcmsk", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3464 { "blci", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3467 #include "i386-dis-evex-reg.h"
3470 static const struct dis386 prefix_table
[][4] = {
3473 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} }, 0 },
3474 { "pause", { XX
}, 0 },
3475 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} }, 0 },
3476 { NULL
, { { NULL
, 0 } }, PREFIX_IGNORED
}
3479 /* PREFIX_0F01_REG_3_RM_1 */
3481 { "vmmcall", { Skip_MODRM
}, 0 },
3482 { "vmgexit", { Skip_MODRM
}, 0 },
3484 { "vmgexit", { Skip_MODRM
}, 0 },
3487 /* PREFIX_0F01_REG_5_MOD_0 */
3490 { "rstorssp", { Mq
}, PREFIX_OPCODE
},
3493 /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
3495 { "serialize", { Skip_MODRM
}, PREFIX_OPCODE
},
3496 { "setssbsy", { Skip_MODRM
}, PREFIX_OPCODE
},
3498 { "xsusldtrk", { Skip_MODRM
}, PREFIX_OPCODE
},
3501 /* PREFIX_0F01_REG_5_MOD_3_RM_1 */
3506 { "xresldtrk", { Skip_MODRM
}, PREFIX_OPCODE
},
3509 /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
3512 { "saveprevssp", { Skip_MODRM
}, PREFIX_OPCODE
},
3515 /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
3517 { "monitorx", { { OP_Monitor
, 0 } }, 0 },
3518 { "mcommit", { Skip_MODRM
}, 0 },
3521 /* PREFIX_0F01_REG_7_MOD_3_RM_3 */
3523 { "mwaitx", { { OP_Mwait
, eBX_reg
} }, 0 },
3528 { "wbinvd", { XX
}, 0 },
3529 { "wbnoinvd", { XX
}, 0 },
3534 { "movups", { XM
, EXx
}, PREFIX_OPCODE
},
3535 { "movss", { XM
, EXd
}, PREFIX_OPCODE
},
3536 { "movupd", { XM
, EXx
}, PREFIX_OPCODE
},
3537 { "movsd", { XM
, EXq
}, PREFIX_OPCODE
},
3542 { "movups", { EXxS
, XM
}, PREFIX_OPCODE
},
3543 { "movss", { EXdS
, XM
}, PREFIX_OPCODE
},
3544 { "movupd", { EXxS
, XM
}, PREFIX_OPCODE
},
3545 { "movsd", { EXqS
, XM
}, PREFIX_OPCODE
},
3550 { MOD_TABLE (MOD_0F12_PREFIX_0
) },
3551 { "movsldup", { XM
, EXx
}, PREFIX_OPCODE
},
3552 { MOD_TABLE (MOD_0F12_PREFIX_2
) },
3553 { "movddup", { XM
, EXq
}, PREFIX_OPCODE
},
3558 { MOD_TABLE (MOD_0F16_PREFIX_0
) },
3559 { "movshdup", { XM
, EXx
}, PREFIX_OPCODE
},
3560 { MOD_TABLE (MOD_0F16_PREFIX_2
) },
3565 { MOD_TABLE (MOD_0F1A_PREFIX_0
) },
3566 { "bndcl", { Gbnd
, Ev_bnd
}, 0 },
3567 { "bndmov", { Gbnd
, Ebnd
}, 0 },
3568 { "bndcu", { Gbnd
, Ev_bnd
}, 0 },
3573 { MOD_TABLE (MOD_0F1B_PREFIX_0
) },
3574 { MOD_TABLE (MOD_0F1B_PREFIX_1
) },
3575 { "bndmov", { EbndS
, Gbnd
}, 0 },
3576 { "bndcn", { Gbnd
, Ev_bnd
}, 0 },
3581 { MOD_TABLE (MOD_0F1C_PREFIX_0
) },
3582 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3583 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3584 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3589 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3590 { MOD_TABLE (MOD_0F1E_PREFIX_1
) },
3591 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3592 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3597 { "cvtpi2ps", { XM
, EMCq
}, PREFIX_OPCODE
},
3598 { "cvtsi2ss%LQ", { XM
, Edq
}, PREFIX_OPCODE
},
3599 { "cvtpi2pd", { XM
, EMCq
}, PREFIX_OPCODE
},
3600 { "cvtsi2sd%LQ", { XM
, Edq
}, 0 },
3605 { MOD_TABLE (MOD_0F2B_PREFIX_0
) },
3606 { MOD_TABLE (MOD_0F2B_PREFIX_1
) },
3607 { MOD_TABLE (MOD_0F2B_PREFIX_2
) },
3608 { MOD_TABLE (MOD_0F2B_PREFIX_3
) },
3613 { "cvttps2pi", { MXC
, EXq
}, PREFIX_OPCODE
},
3614 { "cvttss2si", { Gdq
, EXd
}, PREFIX_OPCODE
},
3615 { "cvttpd2pi", { MXC
, EXx
}, PREFIX_OPCODE
},
3616 { "cvttsd2si", { Gdq
, EXq
}, PREFIX_OPCODE
},
3621 { "cvtps2pi", { MXC
, EXq
}, PREFIX_OPCODE
},
3622 { "cvtss2si", { Gdq
, EXd
}, PREFIX_OPCODE
},
3623 { "cvtpd2pi", { MXC
, EXx
}, PREFIX_OPCODE
},
3624 { "cvtsd2si", { Gdq
, EXq
}, PREFIX_OPCODE
},
3629 { "ucomiss",{ XM
, EXd
}, 0 },
3631 { "ucomisd",{ XM
, EXq
}, 0 },
3636 { "comiss", { XM
, EXd
}, 0 },
3638 { "comisd", { XM
, EXq
}, 0 },
3643 { "sqrtps", { XM
, EXx
}, PREFIX_OPCODE
},
3644 { "sqrtss", { XM
, EXd
}, PREFIX_OPCODE
},
3645 { "sqrtpd", { XM
, EXx
}, PREFIX_OPCODE
},
3646 { "sqrtsd", { XM
, EXq
}, PREFIX_OPCODE
},
3651 { "rsqrtps",{ XM
, EXx
}, PREFIX_OPCODE
},
3652 { "rsqrtss",{ XM
, EXd
}, PREFIX_OPCODE
},
3657 { "rcpps", { XM
, EXx
}, PREFIX_OPCODE
},
3658 { "rcpss", { XM
, EXd
}, PREFIX_OPCODE
},
3663 { "addps", { XM
, EXx
}, PREFIX_OPCODE
},
3664 { "addss", { XM
, EXd
}, PREFIX_OPCODE
},
3665 { "addpd", { XM
, EXx
}, PREFIX_OPCODE
},
3666 { "addsd", { XM
, EXq
}, PREFIX_OPCODE
},
3671 { "mulps", { XM
, EXx
}, PREFIX_OPCODE
},
3672 { "mulss", { XM
, EXd
}, PREFIX_OPCODE
},
3673 { "mulpd", { XM
, EXx
}, PREFIX_OPCODE
},
3674 { "mulsd", { XM
, EXq
}, PREFIX_OPCODE
},
3679 { "cvtps2pd", { XM
, EXq
}, PREFIX_OPCODE
},
3680 { "cvtss2sd", { XM
, EXd
}, PREFIX_OPCODE
},
3681 { "cvtpd2ps", { XM
, EXx
}, PREFIX_OPCODE
},
3682 { "cvtsd2ss", { XM
, EXq
}, PREFIX_OPCODE
},
3687 { "cvtdq2ps", { XM
, EXx
}, PREFIX_OPCODE
},
3688 { "cvttps2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3689 { "cvtps2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3694 { "subps", { XM
, EXx
}, PREFIX_OPCODE
},
3695 { "subss", { XM
, EXd
}, PREFIX_OPCODE
},
3696 { "subpd", { XM
, EXx
}, PREFIX_OPCODE
},
3697 { "subsd", { XM
, EXq
}, PREFIX_OPCODE
},
3702 { "minps", { XM
, EXx
}, PREFIX_OPCODE
},
3703 { "minss", { XM
, EXd
}, PREFIX_OPCODE
},
3704 { "minpd", { XM
, EXx
}, PREFIX_OPCODE
},
3705 { "minsd", { XM
, EXq
}, PREFIX_OPCODE
},
3710 { "divps", { XM
, EXx
}, PREFIX_OPCODE
},
3711 { "divss", { XM
, EXd
}, PREFIX_OPCODE
},
3712 { "divpd", { XM
, EXx
}, PREFIX_OPCODE
},
3713 { "divsd", { XM
, EXq
}, PREFIX_OPCODE
},
3718 { "maxps", { XM
, EXx
}, PREFIX_OPCODE
},
3719 { "maxss", { XM
, EXd
}, PREFIX_OPCODE
},
3720 { "maxpd", { XM
, EXx
}, PREFIX_OPCODE
},
3721 { "maxsd", { XM
, EXq
}, PREFIX_OPCODE
},
3726 { "punpcklbw",{ MX
, EMd
}, PREFIX_OPCODE
},
3728 { "punpcklbw",{ MX
, EMx
}, PREFIX_OPCODE
},
3733 { "punpcklwd",{ MX
, EMd
}, PREFIX_OPCODE
},
3735 { "punpcklwd",{ MX
, EMx
}, PREFIX_OPCODE
},
3740 { "punpckldq",{ MX
, EMd
}, PREFIX_OPCODE
},
3742 { "punpckldq",{ MX
, EMx
}, PREFIX_OPCODE
},
3749 { "punpcklqdq", { XM
, EXx
}, PREFIX_OPCODE
},
3756 { "punpckhqdq", { XM
, EXx
}, PREFIX_OPCODE
},
3761 { "movq", { MX
, EM
}, PREFIX_OPCODE
},
3762 { "movdqu", { XM
, EXx
}, PREFIX_OPCODE
},
3763 { "movdqa", { XM
, EXx
}, PREFIX_OPCODE
},
3768 { "pshufw", { MX
, EM
, Ib
}, PREFIX_OPCODE
},
3769 { "pshufhw",{ XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3770 { "pshufd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3771 { "pshuflw",{ XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3774 /* PREFIX_0F73_REG_3 */
3778 { "psrldq", { XS
, Ib
}, 0 },
3781 /* PREFIX_0F73_REG_7 */
3785 { "pslldq", { XS
, Ib
}, 0 },
3790 {"vmread", { Em
, Gm
}, 0 },
3792 {"extrq", { XS
, Ib
, Ib
}, 0 },
3793 {"insertq", { XM
, XS
, Ib
, Ib
}, 0 },
3798 {"vmwrite", { Gm
, Em
}, 0 },
3800 {"extrq", { XM
, XS
}, 0 },
3801 {"insertq", { XM
, XS
}, 0 },
3808 { "haddpd", { XM
, EXx
}, PREFIX_OPCODE
},
3809 { "haddps", { XM
, EXx
}, PREFIX_OPCODE
},
3816 { "hsubpd", { XM
, EXx
}, PREFIX_OPCODE
},
3817 { "hsubps", { XM
, EXx
}, PREFIX_OPCODE
},
3822 { "movK", { Edq
, MX
}, PREFIX_OPCODE
},
3823 { "movq", { XM
, EXq
}, PREFIX_OPCODE
},
3824 { "movK", { Edq
, XM
}, PREFIX_OPCODE
},
3829 { "movq", { EMS
, MX
}, PREFIX_OPCODE
},
3830 { "movdqu", { EXxS
, XM
}, PREFIX_OPCODE
},
3831 { "movdqa", { EXxS
, XM
}, PREFIX_OPCODE
},
3834 /* PREFIX_0FAE_REG_0_MOD_3 */
3837 { "rdfsbase", { Ev
}, 0 },
3840 /* PREFIX_0FAE_REG_1_MOD_3 */
3843 { "rdgsbase", { Ev
}, 0 },
3846 /* PREFIX_0FAE_REG_2_MOD_3 */
3849 { "wrfsbase", { Ev
}, 0 },
3852 /* PREFIX_0FAE_REG_3_MOD_3 */
3855 { "wrgsbase", { Ev
}, 0 },
3858 /* PREFIX_0FAE_REG_4_MOD_0 */
3860 { "xsave", { FXSAVE
}, 0 },
3861 { "ptwrite%LQ", { Edq
}, 0 },
3864 /* PREFIX_0FAE_REG_4_MOD_3 */
3867 { "ptwrite%LQ", { Edq
}, 0 },
3870 /* PREFIX_0FAE_REG_5_MOD_0 */
3872 { "xrstor", { FXSAVE
}, PREFIX_OPCODE
},
3875 /* PREFIX_0FAE_REG_5_MOD_3 */
3877 { "lfence", { Skip_MODRM
}, 0 },
3878 { "incsspK", { Rdq
}, PREFIX_OPCODE
},
3881 /* PREFIX_0FAE_REG_6_MOD_0 */
3883 { "xsaveopt", { FXSAVE
}, PREFIX_OPCODE
},
3884 { "clrssbsy", { Mq
}, PREFIX_OPCODE
},
3885 { "clwb", { Mb
}, PREFIX_OPCODE
},
3888 /* PREFIX_0FAE_REG_6_MOD_3 */
3890 { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0
) },
3891 { "umonitor", { Eva
}, PREFIX_OPCODE
},
3892 { "tpause", { Edq
}, PREFIX_OPCODE
},
3893 { "umwait", { Edq
}, PREFIX_OPCODE
},
3896 /* PREFIX_0FAE_REG_7_MOD_0 */
3898 { "clflush", { Mb
}, 0 },
3900 { "clflushopt", { Mb
}, 0 },
3906 { "popcntS", { Gv
, Ev
}, 0 },
3911 { "bsfS", { Gv
, Ev
}, 0 },
3912 { "tzcntS", { Gv
, Ev
}, 0 },
3913 { "bsfS", { Gv
, Ev
}, 0 },
3918 { "bsrS", { Gv
, Ev
}, 0 },
3919 { "lzcntS", { Gv
, Ev
}, 0 },
3920 { "bsrS", { Gv
, Ev
}, 0 },
3925 { "cmpps", { XM
, EXx
, CMP
}, PREFIX_OPCODE
},
3926 { "cmpss", { XM
, EXd
, CMP
}, PREFIX_OPCODE
},
3927 { "cmppd", { XM
, EXx
, CMP
}, PREFIX_OPCODE
},
3928 { "cmpsd", { XM
, EXq
, CMP
}, PREFIX_OPCODE
},
3931 /* PREFIX_0FC3_MOD_0 */
3933 { "movntiS", { Edq
, Gdq
}, PREFIX_OPCODE
},
3936 /* PREFIX_0FC7_REG_6_MOD_0 */
3938 { "vmptrld",{ Mq
}, 0 },
3939 { "vmxon", { Mq
}, 0 },
3940 { "vmclear",{ Mq
}, 0 },
3943 /* PREFIX_0FC7_REG_6_MOD_3 */
3945 { "rdrand", { Ev
}, 0 },
3947 { "rdrand", { Ev
}, 0 }
3950 /* PREFIX_0FC7_REG_7_MOD_3 */
3952 { "rdseed", { Ev
}, 0 },
3953 { "rdpid", { Em
}, 0 },
3954 { "rdseed", { Ev
}, 0 },
3961 { "addsubpd", { XM
, EXx
}, 0 },
3962 { "addsubps", { XM
, EXx
}, 0 },
3968 { "movq2dq",{ XM
, MS
}, 0 },
3969 { "movq", { EXqS
, XM
}, 0 },
3970 { "movdq2q",{ MX
, XS
}, 0 },
3976 { "cvtdq2pd", { XM
, EXq
}, PREFIX_OPCODE
},
3977 { "cvttpd2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3978 { "cvtpd2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3983 { "movntq", { Mq
, MX
}, PREFIX_OPCODE
},
3985 { MOD_TABLE (MOD_0FE7_PREFIX_2
) },
3993 { MOD_TABLE (MOD_0FF0_PREFIX_3
) },
3998 { "maskmovq", { MX
, MS
}, PREFIX_OPCODE
},
4000 { "maskmovdqu", { XM
, XS
}, PREFIX_OPCODE
},
4007 { "pblendvb", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4014 { "blendvps", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4021 { "blendvpd", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4028 { "ptest", { XM
, EXx
}, PREFIX_OPCODE
},
4035 { "pmovsxbw", { XM
, EXq
}, PREFIX_OPCODE
},
4042 { "pmovsxbd", { XM
, EXd
}, PREFIX_OPCODE
},
4049 { "pmovsxbq", { XM
, EXw
}, PREFIX_OPCODE
},
4056 { "pmovsxwd", { XM
, EXq
}, PREFIX_OPCODE
},
4063 { "pmovsxwq", { XM
, EXd
}, PREFIX_OPCODE
},
4070 { "pmovsxdq", { XM
, EXq
}, PREFIX_OPCODE
},
4077 { "pmuldq", { XM
, EXx
}, PREFIX_OPCODE
},
4084 { "pcmpeqq", { XM
, EXx
}, PREFIX_OPCODE
},
4091 { MOD_TABLE (MOD_0F382A_PREFIX_2
) },
4098 { "packusdw", { XM
, EXx
}, PREFIX_OPCODE
},
4105 { "pmovzxbw", { XM
, EXq
}, PREFIX_OPCODE
},
4112 { "pmovzxbd", { XM
, EXd
}, PREFIX_OPCODE
},
4119 { "pmovzxbq", { XM
, EXw
}, PREFIX_OPCODE
},
4126 { "pmovzxwd", { XM
, EXq
}, PREFIX_OPCODE
},
4133 { "pmovzxwq", { XM
, EXd
}, PREFIX_OPCODE
},
4140 { "pmovzxdq", { XM
, EXq
}, PREFIX_OPCODE
},
4147 { "pcmpgtq", { XM
, EXx
}, PREFIX_OPCODE
},
4154 { "pminsb", { XM
, EXx
}, PREFIX_OPCODE
},
4161 { "pminsd", { XM
, EXx
}, PREFIX_OPCODE
},
4168 { "pminuw", { XM
, EXx
}, PREFIX_OPCODE
},
4175 { "pminud", { XM
, EXx
}, PREFIX_OPCODE
},
4182 { "pmaxsb", { XM
, EXx
}, PREFIX_OPCODE
},
4189 { "pmaxsd", { XM
, EXx
}, PREFIX_OPCODE
},
4196 { "pmaxuw", { XM
, EXx
}, PREFIX_OPCODE
},
4203 { "pmaxud", { XM
, EXx
}, PREFIX_OPCODE
},
4210 { "pmulld", { XM
, EXx
}, PREFIX_OPCODE
},
4217 { "phminposuw", { XM
, EXx
}, PREFIX_OPCODE
},
4224 { "invept", { Gm
, Mo
}, PREFIX_OPCODE
},
4231 { "invvpid", { Gm
, Mo
}, PREFIX_OPCODE
},
4238 { "invpcid", { Gm
, M
}, PREFIX_OPCODE
},
4243 { "sha1nexte", { XM
, EXxmm
}, PREFIX_OPCODE
},
4248 { "sha1msg1", { XM
, EXxmm
}, PREFIX_OPCODE
},
4253 { "sha1msg2", { XM
, EXxmm
}, PREFIX_OPCODE
},
4258 { "sha256rnds2", { XM
, EXxmm
, XMM0
}, PREFIX_OPCODE
},
4263 { "sha256msg1", { XM
, EXxmm
}, PREFIX_OPCODE
},
4268 { "sha256msg2", { XM
, EXxmm
}, PREFIX_OPCODE
},
4275 { "gf2p8mulb", { XM
, EXxmm
}, PREFIX_OPCODE
},
4282 { "aesimc", { XM
, EXx
}, PREFIX_OPCODE
},
4289 { "aesenc", { XM
, EXx
}, PREFIX_OPCODE
},
4296 { "aesenclast", { XM
, EXx
}, PREFIX_OPCODE
},
4303 { "aesdec", { XM
, EXx
}, PREFIX_OPCODE
},
4310 { "aesdeclast", { XM
, EXx
}, PREFIX_OPCODE
},
4315 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4317 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4318 { "crc32", { Gdq
, { CRC32_Fixup
, b_mode
} }, PREFIX_OPCODE
},
4323 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
}, PREFIX_OPCODE
},
4325 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
}, PREFIX_OPCODE
},
4326 { "crc32", { Gdq
, { CRC32_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4333 { MOD_TABLE (MOD_0F38F5_PREFIX_2
) },
4338 { MOD_TABLE (MOD_0F38F6_PREFIX_0
) },
4339 { "adoxS", { Gdq
, Edq
}, PREFIX_OPCODE
},
4340 { "adcxS", { Gdq
, Edq
}, PREFIX_OPCODE
},
4347 { MOD_TABLE (MOD_0F38F8_PREFIX_1
) },
4348 { MOD_TABLE (MOD_0F38F8_PREFIX_2
) },
4349 { MOD_TABLE (MOD_0F38F8_PREFIX_3
) },
4354 { MOD_TABLE (MOD_0F38F9_PREFIX_0
) },
4361 { "roundps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4368 { "roundpd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4375 { "roundss", { XM
, EXd
, Ib
}, PREFIX_OPCODE
},
4382 { "roundsd", { XM
, EXq
, Ib
}, PREFIX_OPCODE
},
4389 { "blendps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4396 { "blendpd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4403 { "pblendw", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4410 { "pextrb", { Edqb
, XM
, Ib
}, PREFIX_OPCODE
},
4417 { "pextrw", { Edqw
, XM
, Ib
}, PREFIX_OPCODE
},
4424 { "pextrK", { Edq
, XM
, Ib
}, PREFIX_OPCODE
},
4431 { "extractps", { Edqd
, XM
, Ib
}, PREFIX_OPCODE
},
4438 { "pinsrb", { XM
, Edqb
, Ib
}, PREFIX_OPCODE
},
4445 { "insertps", { XM
, EXd
, Ib
}, PREFIX_OPCODE
},
4452 { "pinsrK", { XM
, Edq
, Ib
}, PREFIX_OPCODE
},
4459 { "dpps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4466 { "dppd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4473 { "mpsadbw", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4480 { "pclmulqdq", { XM
, EXx
, PCLMUL
}, PREFIX_OPCODE
},
4487 { "pcmpestrm", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, PREFIX_OPCODE
},
4494 { "pcmpestri", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, PREFIX_OPCODE
},
4501 { "pcmpistrm", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4508 { "pcmpistri", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4513 { "sha1rnds4", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4520 { "gf2p8affineqb", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4527 { "gf2p8affineinvqb", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4534 { "aeskeygenassist", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4537 /* PREFIX_VEX_0F10 */
4539 { "vmovups", { XM
, EXx
}, 0 },
4540 { "vmovss", { XMVexScalar
, VexScalar
, EXxmm_md
}, 0 },
4541 { "vmovupd", { XM
, EXx
}, 0 },
4542 { "vmovsd", { XMVexScalar
, VexScalar
, EXxmm_mq
}, 0 },
4545 /* PREFIX_VEX_0F11 */
4547 { "vmovups", { EXxS
, XM
}, 0 },
4548 { "vmovss", { EXdVexScalarS
, VexScalar
, XMScalar
}, 0 },
4549 { "vmovupd", { EXxS
, XM
}, 0 },
4550 { "vmovsd", { EXqVexScalarS
, VexScalar
, XMScalar
}, 0 },
4553 /* PREFIX_VEX_0F12 */
4555 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0
) },
4556 { "vmovsldup", { XM
, EXx
}, 0 },
4557 { MOD_TABLE (MOD_VEX_0F12_PREFIX_2
) },
4558 { "vmovddup", { XM
, EXymmq
}, 0 },
4561 /* PREFIX_VEX_0F16 */
4563 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0
) },
4564 { "vmovshdup", { XM
, EXx
}, 0 },
4565 { MOD_TABLE (MOD_VEX_0F16_PREFIX_2
) },
4568 /* PREFIX_VEX_0F2A */
4571 { "vcvtsi2ss%LQ", { XMScalar
, VexScalar
, Edq
}, 0 },
4573 { "vcvtsi2sd%LQ", { XMScalar
, VexScalar
, Edq
}, 0 },
4576 /* PREFIX_VEX_0F2C */
4579 { "vcvttss2si", { Gdq
, EXxmm_md
}, 0 },
4581 { "vcvttsd2si", { Gdq
, EXxmm_mq
}, 0 },
4584 /* PREFIX_VEX_0F2D */
4587 { "vcvtss2si", { Gdq
, EXxmm_md
}, 0 },
4589 { "vcvtsd2si", { Gdq
, EXxmm_mq
}, 0 },
4592 /* PREFIX_VEX_0F2E */
4594 { "vucomiss", { XMScalar
, EXxmm_md
}, 0 },
4596 { "vucomisd", { XMScalar
, EXxmm_mq
}, 0 },
4599 /* PREFIX_VEX_0F2F */
4601 { "vcomiss", { XMScalar
, EXxmm_md
}, 0 },
4603 { "vcomisd", { XMScalar
, EXxmm_mq
}, 0 },
4606 /* PREFIX_VEX_0F41 */
4608 { VEX_LEN_TABLE (VEX_LEN_0F41_P_0
) },
4610 { VEX_LEN_TABLE (VEX_LEN_0F41_P_2
) },
4613 /* PREFIX_VEX_0F42 */
4615 { VEX_LEN_TABLE (VEX_LEN_0F42_P_0
) },
4617 { VEX_LEN_TABLE (VEX_LEN_0F42_P_2
) },
4620 /* PREFIX_VEX_0F44 */
4622 { VEX_LEN_TABLE (VEX_LEN_0F44_P_0
) },
4624 { VEX_LEN_TABLE (VEX_LEN_0F44_P_2
) },
4627 /* PREFIX_VEX_0F45 */
4629 { VEX_LEN_TABLE (VEX_LEN_0F45_P_0
) },
4631 { VEX_LEN_TABLE (VEX_LEN_0F45_P_2
) },
4634 /* PREFIX_VEX_0F46 */
4636 { VEX_LEN_TABLE (VEX_LEN_0F46_P_0
) },
4638 { VEX_LEN_TABLE (VEX_LEN_0F46_P_2
) },
4641 /* PREFIX_VEX_0F47 */
4643 { VEX_LEN_TABLE (VEX_LEN_0F47_P_0
) },
4645 { VEX_LEN_TABLE (VEX_LEN_0F47_P_2
) },
4648 /* PREFIX_VEX_0F4A */
4650 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0
) },
4652 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2
) },
4655 /* PREFIX_VEX_0F4B */
4657 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0
) },
4659 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2
) },
4662 /* PREFIX_VEX_0F51 */
4664 { "vsqrtps", { XM
, EXx
}, 0 },
4665 { "vsqrtss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
4666 { "vsqrtpd", { XM
, EXx
}, 0 },
4667 { "vsqrtsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
4670 /* PREFIX_VEX_0F52 */
4672 { "vrsqrtps", { XM
, EXx
}, 0 },
4673 { "vrsqrtss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
4676 /* PREFIX_VEX_0F53 */
4678 { "vrcpps", { XM
, EXx
}, 0 },
4679 { "vrcpss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
4682 /* PREFIX_VEX_0F58 */
4684 { "vaddps", { XM
, Vex
, EXx
}, 0 },
4685 { "vaddss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
4686 { "vaddpd", { XM
, Vex
, EXx
}, 0 },
4687 { "vaddsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
4690 /* PREFIX_VEX_0F59 */
4692 { "vmulps", { XM
, Vex
, EXx
}, 0 },
4693 { "vmulss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
4694 { "vmulpd", { XM
, Vex
, EXx
}, 0 },
4695 { "vmulsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
4698 /* PREFIX_VEX_0F5A */
4700 { "vcvtps2pd", { XM
, EXxmmq
}, 0 },
4701 { "vcvtss2sd", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
4702 { "vcvtpd2ps%XY",{ XMM
, EXx
}, 0 },
4703 { "vcvtsd2ss", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
4706 /* PREFIX_VEX_0F5B */
4708 { "vcvtdq2ps", { XM
, EXx
}, 0 },
4709 { "vcvttps2dq", { XM
, EXx
}, 0 },
4710 { "vcvtps2dq", { XM
, EXx
}, 0 },
4713 /* PREFIX_VEX_0F5C */
4715 { "vsubps", { XM
, Vex
, EXx
}, 0 },
4716 { "vsubss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
4717 { "vsubpd", { XM
, Vex
, EXx
}, 0 },
4718 { "vsubsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
4721 /* PREFIX_VEX_0F5D */
4723 { "vminps", { XM
, Vex
, EXx
}, 0 },
4724 { "vminss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
4725 { "vminpd", { XM
, Vex
, EXx
}, 0 },
4726 { "vminsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
4729 /* PREFIX_VEX_0F5E */
4731 { "vdivps", { XM
, Vex
, EXx
}, 0 },
4732 { "vdivss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
4733 { "vdivpd", { XM
, Vex
, EXx
}, 0 },
4734 { "vdivsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
4737 /* PREFIX_VEX_0F5F */
4739 { "vmaxps", { XM
, Vex
, EXx
}, 0 },
4740 { "vmaxss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
4741 { "vmaxpd", { XM
, Vex
, EXx
}, 0 },
4742 { "vmaxsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
4745 /* PREFIX_VEX_0F60 */
4749 { "vpunpcklbw", { XM
, Vex
, EXx
}, 0 },
4752 /* PREFIX_VEX_0F61 */
4756 { "vpunpcklwd", { XM
, Vex
, EXx
}, 0 },
4759 /* PREFIX_VEX_0F62 */
4763 { "vpunpckldq", { XM
, Vex
, EXx
}, 0 },
4766 /* PREFIX_VEX_0F63 */
4770 { "vpacksswb", { XM
, Vex
, EXx
}, 0 },
4773 /* PREFIX_VEX_0F64 */
4777 { "vpcmpgtb", { XM
, Vex
, EXx
}, 0 },
4780 /* PREFIX_VEX_0F65 */
4784 { "vpcmpgtw", { XM
, Vex
, EXx
}, 0 },
4787 /* PREFIX_VEX_0F66 */
4791 { "vpcmpgtd", { XM
, Vex
, EXx
}, 0 },
4794 /* PREFIX_VEX_0F67 */
4798 { "vpackuswb", { XM
, Vex
, EXx
}, 0 },
4801 /* PREFIX_VEX_0F68 */
4805 { "vpunpckhbw", { XM
, Vex
, EXx
}, 0 },
4808 /* PREFIX_VEX_0F69 */
4812 { "vpunpckhwd", { XM
, Vex
, EXx
}, 0 },
4815 /* PREFIX_VEX_0F6A */
4819 { "vpunpckhdq", { XM
, Vex
, EXx
}, 0 },
4822 /* PREFIX_VEX_0F6B */
4826 { "vpackssdw", { XM
, Vex
, EXx
}, 0 },
4829 /* PREFIX_VEX_0F6C */
4833 { "vpunpcklqdq", { XM
, Vex
, EXx
}, 0 },
4836 /* PREFIX_VEX_0F6D */
4840 { "vpunpckhqdq", { XM
, Vex
, EXx
}, 0 },
4843 /* PREFIX_VEX_0F6E */
4847 { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2
) },
4850 /* PREFIX_VEX_0F6F */
4853 { "vmovdqu", { XM
, EXx
}, 0 },
4854 { "vmovdqa", { XM
, EXx
}, 0 },
4857 /* PREFIX_VEX_0F70 */
4860 { "vpshufhw", { XM
, EXx
, Ib
}, 0 },
4861 { "vpshufd", { XM
, EXx
, Ib
}, 0 },
4862 { "vpshuflw", { XM
, EXx
, Ib
}, 0 },
4865 /* PREFIX_VEX_0F71_REG_2 */
4869 { "vpsrlw", { Vex
, XS
, Ib
}, 0 },
4872 /* PREFIX_VEX_0F71_REG_4 */
4876 { "vpsraw", { Vex
, XS
, Ib
}, 0 },
4879 /* PREFIX_VEX_0F71_REG_6 */
4883 { "vpsllw", { Vex
, XS
, Ib
}, 0 },
4886 /* PREFIX_VEX_0F72_REG_2 */
4890 { "vpsrld", { Vex
, XS
, Ib
}, 0 },
4893 /* PREFIX_VEX_0F72_REG_4 */
4897 { "vpsrad", { Vex
, XS
, Ib
}, 0 },
4900 /* PREFIX_VEX_0F72_REG_6 */
4904 { "vpslld", { Vex
, XS
, Ib
}, 0 },
4907 /* PREFIX_VEX_0F73_REG_2 */
4911 { "vpsrlq", { Vex
, XS
, Ib
}, 0 },
4914 /* PREFIX_VEX_0F73_REG_3 */
4918 { "vpsrldq", { Vex
, XS
, Ib
}, 0 },
4921 /* PREFIX_VEX_0F73_REG_6 */
4925 { "vpsllq", { Vex
, XS
, Ib
}, 0 },
4928 /* PREFIX_VEX_0F73_REG_7 */
4932 { "vpslldq", { Vex
, XS
, Ib
}, 0 },
4935 /* PREFIX_VEX_0F74 */
4939 { "vpcmpeqb", { XM
, Vex
, EXx
}, 0 },
4942 /* PREFIX_VEX_0F75 */
4946 { "vpcmpeqw", { XM
, Vex
, EXx
}, 0 },
4949 /* PREFIX_VEX_0F76 */
4953 { "vpcmpeqd", { XM
, Vex
, EXx
}, 0 },
4956 /* PREFIX_VEX_0F77 */
4958 { VEX_LEN_TABLE (VEX_LEN_0F77_P_0
) },
4961 /* PREFIX_VEX_0F7C */
4965 { "vhaddpd", { XM
, Vex
, EXx
}, 0 },
4966 { "vhaddps", { XM
, Vex
, EXx
}, 0 },
4969 /* PREFIX_VEX_0F7D */
4973 { "vhsubpd", { XM
, Vex
, EXx
}, 0 },
4974 { "vhsubps", { XM
, Vex
, EXx
}, 0 },
4977 /* PREFIX_VEX_0F7E */
4980 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1
) },
4981 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2
) },
4984 /* PREFIX_VEX_0F7F */
4987 { "vmovdqu", { EXxS
, XM
}, 0 },
4988 { "vmovdqa", { EXxS
, XM
}, 0 },
4991 /* PREFIX_VEX_0F90 */
4993 { VEX_LEN_TABLE (VEX_LEN_0F90_P_0
) },
4995 { VEX_LEN_TABLE (VEX_LEN_0F90_P_2
) },
4998 /* PREFIX_VEX_0F91 */
5000 { VEX_LEN_TABLE (VEX_LEN_0F91_P_0
) },
5002 { VEX_LEN_TABLE (VEX_LEN_0F91_P_2
) },
5005 /* PREFIX_VEX_0F92 */
5007 { VEX_LEN_TABLE (VEX_LEN_0F92_P_0
) },
5009 { VEX_LEN_TABLE (VEX_LEN_0F92_P_2
) },
5010 { VEX_LEN_TABLE (VEX_LEN_0F92_P_3
) },
5013 /* PREFIX_VEX_0F93 */
5015 { VEX_LEN_TABLE (VEX_LEN_0F93_P_0
) },
5017 { VEX_LEN_TABLE (VEX_LEN_0F93_P_2
) },
5018 { VEX_LEN_TABLE (VEX_LEN_0F93_P_3
) },
5021 /* PREFIX_VEX_0F98 */
5023 { VEX_LEN_TABLE (VEX_LEN_0F98_P_0
) },
5025 { VEX_LEN_TABLE (VEX_LEN_0F98_P_2
) },
5028 /* PREFIX_VEX_0F99 */
5030 { VEX_LEN_TABLE (VEX_LEN_0F99_P_0
) },
5032 { VEX_LEN_TABLE (VEX_LEN_0F99_P_2
) },
5035 /* PREFIX_VEX_0FC2 */
5037 { "vcmpps", { XM
, Vex
, EXx
, VCMP
}, 0 },
5038 { "vcmpss", { XMScalar
, VexScalar
, EXxmm_md
, VCMP
}, 0 },
5039 { "vcmppd", { XM
, Vex
, EXx
, VCMP
}, 0 },
5040 { "vcmpsd", { XMScalar
, VexScalar
, EXxmm_mq
, VCMP
}, 0 },
5043 /* PREFIX_VEX_0FC4 */
5047 { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2
) },
5050 /* PREFIX_VEX_0FC5 */
5054 { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2
) },
5057 /* PREFIX_VEX_0FD0 */
5061 { "vaddsubpd", { XM
, Vex
, EXx
}, 0 },
5062 { "vaddsubps", { XM
, Vex
, EXx
}, 0 },
5065 /* PREFIX_VEX_0FD1 */
5069 { "vpsrlw", { XM
, Vex
, EXxmm
}, 0 },
5072 /* PREFIX_VEX_0FD2 */
5076 { "vpsrld", { XM
, Vex
, EXxmm
}, 0 },
5079 /* PREFIX_VEX_0FD3 */
5083 { "vpsrlq", { XM
, Vex
, EXxmm
}, 0 },
5086 /* PREFIX_VEX_0FD4 */
5090 { "vpaddq", { XM
, Vex
, EXx
}, 0 },
5093 /* PREFIX_VEX_0FD5 */
5097 { "vpmullw", { XM
, Vex
, EXx
}, 0 },
5100 /* PREFIX_VEX_0FD6 */
5104 { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2
) },
5107 /* PREFIX_VEX_0FD7 */
5111 { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2
) },
5114 /* PREFIX_VEX_0FD8 */
5118 { "vpsubusb", { XM
, Vex
, EXx
}, 0 },
5121 /* PREFIX_VEX_0FD9 */
5125 { "vpsubusw", { XM
, Vex
, EXx
}, 0 },
5128 /* PREFIX_VEX_0FDA */
5132 { "vpminub", { XM
, Vex
, EXx
}, 0 },
5135 /* PREFIX_VEX_0FDB */
5139 { "vpand", { XM
, Vex
, EXx
}, 0 },
5142 /* PREFIX_VEX_0FDC */
5146 { "vpaddusb", { XM
, Vex
, EXx
}, 0 },
5149 /* PREFIX_VEX_0FDD */
5153 { "vpaddusw", { XM
, Vex
, EXx
}, 0 },
5156 /* PREFIX_VEX_0FDE */
5160 { "vpmaxub", { XM
, Vex
, EXx
}, 0 },
5163 /* PREFIX_VEX_0FDF */
5167 { "vpandn", { XM
, Vex
, EXx
}, 0 },
5170 /* PREFIX_VEX_0FE0 */
5174 { "vpavgb", { XM
, Vex
, EXx
}, 0 },
5177 /* PREFIX_VEX_0FE1 */
5181 { "vpsraw", { XM
, Vex
, EXxmm
}, 0 },
5184 /* PREFIX_VEX_0FE2 */
5188 { "vpsrad", { XM
, Vex
, EXxmm
}, 0 },
5191 /* PREFIX_VEX_0FE3 */
5195 { "vpavgw", { XM
, Vex
, EXx
}, 0 },
5198 /* PREFIX_VEX_0FE4 */
5202 { "vpmulhuw", { XM
, Vex
, EXx
}, 0 },
5205 /* PREFIX_VEX_0FE5 */
5209 { "vpmulhw", { XM
, Vex
, EXx
}, 0 },
5212 /* PREFIX_VEX_0FE6 */
5215 { "vcvtdq2pd", { XM
, EXxmmq
}, 0 },
5216 { "vcvttpd2dq%XY", { XMM
, EXx
}, 0 },
5217 { "vcvtpd2dq%XY", { XMM
, EXx
}, 0 },
5220 /* PREFIX_VEX_0FE7 */
5224 { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2
) },
5227 /* PREFIX_VEX_0FE8 */
5231 { "vpsubsb", { XM
, Vex
, EXx
}, 0 },
5234 /* PREFIX_VEX_0FE9 */
5238 { "vpsubsw", { XM
, Vex
, EXx
}, 0 },
5241 /* PREFIX_VEX_0FEA */
5245 { "vpminsw", { XM
, Vex
, EXx
}, 0 },
5248 /* PREFIX_VEX_0FEB */
5252 { "vpor", { XM
, Vex
, EXx
}, 0 },
5255 /* PREFIX_VEX_0FEC */
5259 { "vpaddsb", { XM
, Vex
, EXx
}, 0 },
5262 /* PREFIX_VEX_0FED */
5266 { "vpaddsw", { XM
, Vex
, EXx
}, 0 },
5269 /* PREFIX_VEX_0FEE */
5273 { "vpmaxsw", { XM
, Vex
, EXx
}, 0 },
5276 /* PREFIX_VEX_0FEF */
5280 { "vpxor", { XM
, Vex
, EXx
}, 0 },
5283 /* PREFIX_VEX_0FF0 */
5288 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3
) },
5291 /* PREFIX_VEX_0FF1 */
5295 { "vpsllw", { XM
, Vex
, EXxmm
}, 0 },
5298 /* PREFIX_VEX_0FF2 */
5302 { "vpslld", { XM
, Vex
, EXxmm
}, 0 },
5305 /* PREFIX_VEX_0FF3 */
5309 { "vpsllq", { XM
, Vex
, EXxmm
}, 0 },
5312 /* PREFIX_VEX_0FF4 */
5316 { "vpmuludq", { XM
, Vex
, EXx
}, 0 },
5319 /* PREFIX_VEX_0FF5 */
5323 { "vpmaddwd", { XM
, Vex
, EXx
}, 0 },
5326 /* PREFIX_VEX_0FF6 */
5330 { "vpsadbw", { XM
, Vex
, EXx
}, 0 },
5333 /* PREFIX_VEX_0FF7 */
5337 { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2
) },
5340 /* PREFIX_VEX_0FF8 */
5344 { "vpsubb", { XM
, Vex
, EXx
}, 0 },
5347 /* PREFIX_VEX_0FF9 */
5351 { "vpsubw", { XM
, Vex
, EXx
}, 0 },
5354 /* PREFIX_VEX_0FFA */
5358 { "vpsubd", { XM
, Vex
, EXx
}, 0 },
5361 /* PREFIX_VEX_0FFB */
5365 { "vpsubq", { XM
, Vex
, EXx
}, 0 },
5368 /* PREFIX_VEX_0FFC */
5372 { "vpaddb", { XM
, Vex
, EXx
}, 0 },
5375 /* PREFIX_VEX_0FFD */
5379 { "vpaddw", { XM
, Vex
, EXx
}, 0 },
5382 /* PREFIX_VEX_0FFE */
5386 { "vpaddd", { XM
, Vex
, EXx
}, 0 },
5389 /* PREFIX_VEX_0F3800 */
5393 { "vpshufb", { XM
, Vex
, EXx
}, 0 },
5396 /* PREFIX_VEX_0F3801 */
5400 { "vphaddw", { XM
, Vex
, EXx
}, 0 },
5403 /* PREFIX_VEX_0F3802 */
5407 { "vphaddd", { XM
, Vex
, EXx
}, 0 },
5410 /* PREFIX_VEX_0F3803 */
5414 { "vphaddsw", { XM
, Vex
, EXx
}, 0 },
5417 /* PREFIX_VEX_0F3804 */
5421 { "vpmaddubsw", { XM
, Vex
, EXx
}, 0 },
5424 /* PREFIX_VEX_0F3805 */
5428 { "vphsubw", { XM
, Vex
, EXx
}, 0 },
5431 /* PREFIX_VEX_0F3806 */
5435 { "vphsubd", { XM
, Vex
, EXx
}, 0 },
5438 /* PREFIX_VEX_0F3807 */
5442 { "vphsubsw", { XM
, Vex
, EXx
}, 0 },
5445 /* PREFIX_VEX_0F3808 */
5449 { "vpsignb", { XM
, Vex
, EXx
}, 0 },
5452 /* PREFIX_VEX_0F3809 */
5456 { "vpsignw", { XM
, Vex
, EXx
}, 0 },
5459 /* PREFIX_VEX_0F380A */
5463 { "vpsignd", { XM
, Vex
, EXx
}, 0 },
5466 /* PREFIX_VEX_0F380B */
5470 { "vpmulhrsw", { XM
, Vex
, EXx
}, 0 },
5473 /* PREFIX_VEX_0F380C */
5477 { VEX_W_TABLE (VEX_W_0F380C_P_2
) },
5480 /* PREFIX_VEX_0F380D */
5484 { VEX_W_TABLE (VEX_W_0F380D_P_2
) },
5487 /* PREFIX_VEX_0F380E */
5491 { VEX_W_TABLE (VEX_W_0F380E_P_2
) },
5494 /* PREFIX_VEX_0F380F */
5498 { VEX_W_TABLE (VEX_W_0F380F_P_2
) },
5501 /* PREFIX_VEX_0F3813 */
5505 { VEX_W_TABLE (VEX_W_0F3813_P_2
) },
5508 /* PREFIX_VEX_0F3816 */
5512 { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2
) },
5515 /* PREFIX_VEX_0F3817 */
5519 { "vptest", { XM
, EXx
}, 0 },
5522 /* PREFIX_VEX_0F3818 */
5526 { VEX_W_TABLE (VEX_W_0F3818_P_2
) },
5529 /* PREFIX_VEX_0F3819 */
5533 { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2
) },
5536 /* PREFIX_VEX_0F381A */
5540 { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2
) },
5543 /* PREFIX_VEX_0F381C */
5547 { "vpabsb", { XM
, EXx
}, 0 },
5550 /* PREFIX_VEX_0F381D */
5554 { "vpabsw", { XM
, EXx
}, 0 },
5557 /* PREFIX_VEX_0F381E */
5561 { "vpabsd", { XM
, EXx
}, 0 },
5564 /* PREFIX_VEX_0F3820 */
5568 { "vpmovsxbw", { XM
, EXxmmq
}, 0 },
5571 /* PREFIX_VEX_0F3821 */
5575 { "vpmovsxbd", { XM
, EXxmmqd
}, 0 },
5578 /* PREFIX_VEX_0F3822 */
5582 { "vpmovsxbq", { XM
, EXxmmdw
}, 0 },
5585 /* PREFIX_VEX_0F3823 */
5589 { "vpmovsxwd", { XM
, EXxmmq
}, 0 },
5592 /* PREFIX_VEX_0F3824 */
5596 { "vpmovsxwq", { XM
, EXxmmqd
}, 0 },
5599 /* PREFIX_VEX_0F3825 */
5603 { "vpmovsxdq", { XM
, EXxmmq
}, 0 },
5606 /* PREFIX_VEX_0F3828 */
5610 { "vpmuldq", { XM
, Vex
, EXx
}, 0 },
5613 /* PREFIX_VEX_0F3829 */
5617 { "vpcmpeqq", { XM
, Vex
, EXx
}, 0 },
5620 /* PREFIX_VEX_0F382A */
5624 { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2
) },
5627 /* PREFIX_VEX_0F382B */
5631 { "vpackusdw", { XM
, Vex
, EXx
}, 0 },
5634 /* PREFIX_VEX_0F382C */
5638 { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2
) },
5641 /* PREFIX_VEX_0F382D */
5645 { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2
) },
5648 /* PREFIX_VEX_0F382E */
5652 { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2
) },
5655 /* PREFIX_VEX_0F382F */
5659 { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2
) },
5662 /* PREFIX_VEX_0F3830 */
5666 { "vpmovzxbw", { XM
, EXxmmq
}, 0 },
5669 /* PREFIX_VEX_0F3831 */
5673 { "vpmovzxbd", { XM
, EXxmmqd
}, 0 },
5676 /* PREFIX_VEX_0F3832 */
5680 { "vpmovzxbq", { XM
, EXxmmdw
}, 0 },
5683 /* PREFIX_VEX_0F3833 */
5687 { "vpmovzxwd", { XM
, EXxmmq
}, 0 },
5690 /* PREFIX_VEX_0F3834 */
5694 { "vpmovzxwq", { XM
, EXxmmqd
}, 0 },
5697 /* PREFIX_VEX_0F3835 */
5701 { "vpmovzxdq", { XM
, EXxmmq
}, 0 },
5704 /* PREFIX_VEX_0F3836 */
5708 { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2
) },
5711 /* PREFIX_VEX_0F3837 */
5715 { "vpcmpgtq", { XM
, Vex
, EXx
}, 0 },
5718 /* PREFIX_VEX_0F3838 */
5722 { "vpminsb", { XM
, Vex
, EXx
}, 0 },
5725 /* PREFIX_VEX_0F3839 */
5729 { "vpminsd", { XM
, Vex
, EXx
}, 0 },
5732 /* PREFIX_VEX_0F383A */
5736 { "vpminuw", { XM
, Vex
, EXx
}, 0 },
5739 /* PREFIX_VEX_0F383B */
5743 { "vpminud", { XM
, Vex
, EXx
}, 0 },
5746 /* PREFIX_VEX_0F383C */
5750 { "vpmaxsb", { XM
, Vex
, EXx
}, 0 },
5753 /* PREFIX_VEX_0F383D */
5757 { "vpmaxsd", { XM
, Vex
, EXx
}, 0 },
5760 /* PREFIX_VEX_0F383E */
5764 { "vpmaxuw", { XM
, Vex
, EXx
}, 0 },
5767 /* PREFIX_VEX_0F383F */
5771 { "vpmaxud", { XM
, Vex
, EXx
}, 0 },
5774 /* PREFIX_VEX_0F3840 */
5778 { "vpmulld", { XM
, Vex
, EXx
}, 0 },
5781 /* PREFIX_VEX_0F3841 */
5785 { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2
) },
5788 /* PREFIX_VEX_0F3845 */
5792 { "vpsrlv%LW", { XM
, Vex
, EXx
}, 0 },
5795 /* PREFIX_VEX_0F3846 */
5799 { VEX_W_TABLE (VEX_W_0F3846_P_2
) },
5802 /* PREFIX_VEX_0F3847 */
5806 { "vpsllv%LW", { XM
, Vex
, EXx
}, 0 },
5809 /* PREFIX_VEX_0F3858 */
5813 { VEX_W_TABLE (VEX_W_0F3858_P_2
) },
5816 /* PREFIX_VEX_0F3859 */
5820 { VEX_W_TABLE (VEX_W_0F3859_P_2
) },
5823 /* PREFIX_VEX_0F385A */
5827 { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2
) },
5830 /* PREFIX_VEX_0F3878 */
5834 { VEX_W_TABLE (VEX_W_0F3878_P_2
) },
5837 /* PREFIX_VEX_0F3879 */
5841 { VEX_W_TABLE (VEX_W_0F3879_P_2
) },
5844 /* PREFIX_VEX_0F388C */
5848 { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2
) },
5851 /* PREFIX_VEX_0F388E */
5855 { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2
) },
5858 /* PREFIX_VEX_0F3890 */
5862 { "vpgatherd%LW", { XM
, MVexVSIBDWpX
, Vex
}, 0 },
5865 /* PREFIX_VEX_0F3891 */
5869 { "vpgatherq%LW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
}, 0 },
5872 /* PREFIX_VEX_0F3892 */
5876 { "vgatherdp%XW", { XM
, MVexVSIBDWpX
, Vex
}, 0 },
5879 /* PREFIX_VEX_0F3893 */
5883 { "vgatherqp%XW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
}, 0 },
5886 /* PREFIX_VEX_0F3896 */
5890 { "vfmaddsub132p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
5893 /* PREFIX_VEX_0F3897 */
5897 { "vfmsubadd132p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
5900 /* PREFIX_VEX_0F3898 */
5904 { "vfmadd132p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
5907 /* PREFIX_VEX_0F3899 */
5911 { "vfmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexR
}, 0 },
5914 /* PREFIX_VEX_0F389A */
5918 { "vfmsub132p%XW", { XM
, Vex
, EXx
}, 0 },
5921 /* PREFIX_VEX_0F389B */
5925 { "vfmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
5928 /* PREFIX_VEX_0F389C */
5932 { "vfnmadd132p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
5935 /* PREFIX_VEX_0F389D */
5939 { "vfnmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexR
}, 0 },
5942 /* PREFIX_VEX_0F389E */
5946 { "vfnmsub132p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
5949 /* PREFIX_VEX_0F389F */
5953 { "vfnmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexR
}, 0 },
5956 /* PREFIX_VEX_0F38A6 */
5960 { "vfmaddsub213p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
5964 /* PREFIX_VEX_0F38A7 */
5968 { "vfmsubadd213p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
5971 /* PREFIX_VEX_0F38A8 */
5975 { "vfmadd213p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
5978 /* PREFIX_VEX_0F38A9 */
5982 { "vfmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexR
}, 0 },
5985 /* PREFIX_VEX_0F38AA */
5989 { "vfmsub213p%XW", { XM
, Vex
, EXx
}, 0 },
5992 /* PREFIX_VEX_0F38AB */
5996 { "vfmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
5999 /* PREFIX_VEX_0F38AC */
6003 { "vfnmadd213p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
6006 /* PREFIX_VEX_0F38AD */
6010 { "vfnmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexR
}, 0 },
6013 /* PREFIX_VEX_0F38AE */
6017 { "vfnmsub213p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
6020 /* PREFIX_VEX_0F38AF */
6024 { "vfnmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexR
}, 0 },
6027 /* PREFIX_VEX_0F38B6 */
6031 { "vfmaddsub231p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
6034 /* PREFIX_VEX_0F38B7 */
6038 { "vfmsubadd231p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
6041 /* PREFIX_VEX_0F38B8 */
6045 { "vfmadd231p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
6048 /* PREFIX_VEX_0F38B9 */
6052 { "vfmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexR
}, 0 },
6055 /* PREFIX_VEX_0F38BA */
6059 { "vfmsub231p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
6062 /* PREFIX_VEX_0F38BB */
6066 { "vfmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexR
}, 0 },
6069 /* PREFIX_VEX_0F38BC */
6073 { "vfnmadd231p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
6076 /* PREFIX_VEX_0F38BD */
6080 { "vfnmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexR
}, 0 },
6083 /* PREFIX_VEX_0F38BE */
6087 { "vfnmsub231p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
6090 /* PREFIX_VEX_0F38BF */
6094 { "vfnmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexR
}, 0 },
6097 /* PREFIX_VEX_0F38CF */
6101 { VEX_W_TABLE (VEX_W_0F38CF_P_2
) },
6104 /* PREFIX_VEX_0F38DB */
6108 { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2
) },
6111 /* PREFIX_VEX_0F38DC */
6115 { "vaesenc", { XM
, Vex
, EXx
}, 0 },
6118 /* PREFIX_VEX_0F38DD */
6122 { "vaesenclast", { XM
, Vex
, EXx
}, 0 },
6125 /* PREFIX_VEX_0F38DE */
6129 { "vaesdec", { XM
, Vex
, EXx
}, 0 },
6132 /* PREFIX_VEX_0F38DF */
6136 { "vaesdeclast", { XM
, Vex
, EXx
}, 0 },
6139 /* PREFIX_VEX_0F38F2 */
6141 { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0
) },
6144 /* PREFIX_VEX_0F38F3_REG_1 */
6146 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0
) },
6149 /* PREFIX_VEX_0F38F3_REG_2 */
6151 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0
) },
6154 /* PREFIX_VEX_0F38F3_REG_3 */
6156 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0
) },
6159 /* PREFIX_VEX_0F38F5 */
6161 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0
) },
6162 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1
) },
6164 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3
) },
6167 /* PREFIX_VEX_0F38F6 */
6172 { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3
) },
6175 /* PREFIX_VEX_0F38F7 */
6177 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0
) },
6178 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1
) },
6179 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2
) },
6180 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3
) },
6183 /* PREFIX_VEX_0F3A00 */
6187 { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2
) },
6190 /* PREFIX_VEX_0F3A01 */
6194 { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2
) },
6197 /* PREFIX_VEX_0F3A02 */
6201 { VEX_W_TABLE (VEX_W_0F3A02_P_2
) },
6204 /* PREFIX_VEX_0F3A04 */
6208 { VEX_W_TABLE (VEX_W_0F3A04_P_2
) },
6211 /* PREFIX_VEX_0F3A05 */
6215 { VEX_W_TABLE (VEX_W_0F3A05_P_2
) },
6218 /* PREFIX_VEX_0F3A06 */
6222 { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2
) },
6225 /* PREFIX_VEX_0F3A08 */
6229 { "vroundps", { XM
, EXx
, Ib
}, 0 },
6232 /* PREFIX_VEX_0F3A09 */
6236 { "vroundpd", { XM
, EXx
, Ib
}, 0 },
6239 /* PREFIX_VEX_0F3A0A */
6243 { "vroundss", { XMScalar
, VexScalar
, EXxmm_md
, Ib
}, 0 },
6246 /* PREFIX_VEX_0F3A0B */
6250 { "vroundsd", { XMScalar
, VexScalar
, EXxmm_mq
, Ib
}, 0 },
6253 /* PREFIX_VEX_0F3A0C */
6257 { "vblendps", { XM
, Vex
, EXx
, Ib
}, 0 },
6260 /* PREFIX_VEX_0F3A0D */
6264 { "vblendpd", { XM
, Vex
, EXx
, Ib
}, 0 },
6267 /* PREFIX_VEX_0F3A0E */
6271 { "vpblendw", { XM
, Vex
, EXx
, Ib
}, 0 },
6274 /* PREFIX_VEX_0F3A0F */
6278 { "vpalignr", { XM
, Vex
, EXx
, Ib
}, 0 },
6281 /* PREFIX_VEX_0F3A14 */
6285 { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2
) },
6288 /* PREFIX_VEX_0F3A15 */
6292 { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2
) },
6295 /* PREFIX_VEX_0F3A16 */
6299 { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2
) },
6302 /* PREFIX_VEX_0F3A17 */
6306 { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2
) },
6309 /* PREFIX_VEX_0F3A18 */
6313 { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2
) },
6316 /* PREFIX_VEX_0F3A19 */
6320 { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2
) },
6323 /* PREFIX_VEX_0F3A1D */
6327 { VEX_W_TABLE (VEX_W_0F3A1D_P_2
) },
6330 /* PREFIX_VEX_0F3A20 */
6334 { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2
) },
6337 /* PREFIX_VEX_0F3A21 */
6341 { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2
) },
6344 /* PREFIX_VEX_0F3A22 */
6348 { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2
) },
6351 /* PREFIX_VEX_0F3A30 */
6355 { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2
) },
6358 /* PREFIX_VEX_0F3A31 */
6362 { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2
) },
6365 /* PREFIX_VEX_0F3A32 */
6369 { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2
) },
6372 /* PREFIX_VEX_0F3A33 */
6376 { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2
) },
6379 /* PREFIX_VEX_0F3A38 */
6383 { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2
) },
6386 /* PREFIX_VEX_0F3A39 */
6390 { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2
) },
6393 /* PREFIX_VEX_0F3A40 */
6397 { "vdpps", { XM
, Vex
, EXx
, Ib
}, 0 },
6400 /* PREFIX_VEX_0F3A41 */
6404 { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2
) },
6407 /* PREFIX_VEX_0F3A42 */
6411 { "vmpsadbw", { XM
, Vex
, EXx
, Ib
}, 0 },
6414 /* PREFIX_VEX_0F3A44 */
6418 { "vpclmulqdq", { XM
, Vex
, EXx
, PCLMUL
}, 0 },
6421 /* PREFIX_VEX_0F3A46 */
6425 { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2
) },
6428 /* PREFIX_VEX_0F3A48 */
6432 { VEX_W_TABLE (VEX_W_0F3A48_P_2
) },
6435 /* PREFIX_VEX_0F3A49 */
6439 { VEX_W_TABLE (VEX_W_0F3A49_P_2
) },
6442 /* PREFIX_VEX_0F3A4A */
6446 { VEX_W_TABLE (VEX_W_0F3A4A_P_2
) },
6449 /* PREFIX_VEX_0F3A4B */
6453 { VEX_W_TABLE (VEX_W_0F3A4B_P_2
) },
6456 /* PREFIX_VEX_0F3A4C */
6460 { VEX_W_TABLE (VEX_W_0F3A4C_P_2
) },
6463 /* PREFIX_VEX_0F3A5C */
6467 { "vfmaddsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6470 /* PREFIX_VEX_0F3A5D */
6474 { "vfmaddsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6477 /* PREFIX_VEX_0F3A5E */
6481 { "vfmsubaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6484 /* PREFIX_VEX_0F3A5F */
6488 { "vfmsubaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6491 /* PREFIX_VEX_0F3A60 */
6495 { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2
) },
6499 /* PREFIX_VEX_0F3A61 */
6503 { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2
) },
6506 /* PREFIX_VEX_0F3A62 */
6510 { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2
) },
6513 /* PREFIX_VEX_0F3A63 */
6517 { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2
) },
6520 /* PREFIX_VEX_0F3A68 */
6524 { "vfmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6527 /* PREFIX_VEX_0F3A69 */
6531 { "vfmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6534 /* PREFIX_VEX_0F3A6A */
6538 { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2
) },
6541 /* PREFIX_VEX_0F3A6B */
6545 { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2
) },
6548 /* PREFIX_VEX_0F3A6C */
6552 { "vfmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6555 /* PREFIX_VEX_0F3A6D */
6559 { "vfmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6562 /* PREFIX_VEX_0F3A6E */
6566 { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2
) },
6569 /* PREFIX_VEX_0F3A6F */
6573 { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2
) },
6576 /* PREFIX_VEX_0F3A78 */
6580 { "vfnmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6583 /* PREFIX_VEX_0F3A79 */
6587 { "vfnmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6590 /* PREFIX_VEX_0F3A7A */
6594 { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2
) },
6597 /* PREFIX_VEX_0F3A7B */
6601 { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2
) },
6604 /* PREFIX_VEX_0F3A7C */
6608 { "vfnmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6612 /* PREFIX_VEX_0F3A7D */
6616 { "vfnmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6619 /* PREFIX_VEX_0F3A7E */
6623 { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2
) },
6626 /* PREFIX_VEX_0F3A7F */
6630 { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2
) },
6633 /* PREFIX_VEX_0F3ACE */
6637 { VEX_W_TABLE (VEX_W_0F3ACE_P_2
) },
6640 /* PREFIX_VEX_0F3ACF */
6644 { VEX_W_TABLE (VEX_W_0F3ACF_P_2
) },
6647 /* PREFIX_VEX_0F3ADF */
6651 { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2
) },
6654 /* PREFIX_VEX_0F3AF0 */
6659 { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3
) },
6662 #include "i386-dis-evex-prefix.h"
6665 static const struct dis386 x86_64_table
[][2] = {
6668 { "pushP", { es
}, 0 },
6673 { "popP", { es
}, 0 },
6678 { "pushP", { cs
}, 0 },
6683 { "pushP", { ss
}, 0 },
6688 { "popP", { ss
}, 0 },
6693 { "pushP", { ds
}, 0 },
6698 { "popP", { ds
}, 0 },
6703 { "daa", { XX
}, 0 },
6708 { "das", { XX
}, 0 },
6713 { "aaa", { XX
}, 0 },
6718 { "aas", { XX
}, 0 },
6723 { "pushaP", { XX
}, 0 },
6728 { "popaP", { XX
}, 0 },
6733 { MOD_TABLE (MOD_62_32BIT
) },
6734 { EVEX_TABLE (EVEX_0F
) },
6739 { "arpl", { Ew
, Gw
}, 0 },
6740 { "movs", { { OP_G
, movsxd_mode
}, { MOVSXD_Fixup
, movsxd_mode
} }, 0 },
6745 { "ins{R|}", { Yzr
, indirDX
}, 0 },
6746 { "ins{G|}", { Yzr
, indirDX
}, 0 },
6751 { "outs{R|}", { indirDXr
, Xz
}, 0 },
6752 { "outs{G|}", { indirDXr
, Xz
}, 0 },
6757 /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */
6758 { REG_TABLE (REG_80
) },
6763 { "{l|}call{T|}", { Ap
}, 0 },
6768 { "retP", { Iw
, BND
}, 0 },
6769 { "ret@", { Iw
, BND
}, 0 },
6774 { "retP", { BND
}, 0 },
6775 { "ret@", { BND
}, 0 },
6780 { MOD_TABLE (MOD_C4_32BIT
) },
6781 { VEX_C4_TABLE (VEX_0F
) },
6786 { MOD_TABLE (MOD_C5_32BIT
) },
6787 { VEX_C5_TABLE (VEX_0F
) },
6792 { "into", { XX
}, 0 },
6797 { "aam", { Ib
}, 0 },
6802 { "aad", { Ib
}, 0 },
6807 { "callP", { Jv
, BND
}, 0 },
6808 { "call@", { Jv
, BND
}, 0 }
6813 { "jmpP", { Jv
, BND
}, 0 },
6814 { "jmp@", { Jv
, BND
}, 0 }
6819 { "{l|}jmp{T|}", { Ap
}, 0 },
6822 /* X86_64_0F01_REG_0 */
6824 { "sgdt{Q|Q}", { M
}, 0 },
6825 { "sgdt", { M
}, 0 },
6828 /* X86_64_0F01_REG_1 */
6830 { "sidt{Q|Q}", { M
}, 0 },
6831 { "sidt", { M
}, 0 },
6834 /* X86_64_0F01_REG_2 */
6836 { "lgdt{Q|Q}", { M
}, 0 },
6837 { "lgdt", { M
}, 0 },
6840 /* X86_64_0F01_REG_3 */
6842 { "lidt{Q|Q}", { M
}, 0 },
6843 { "lidt", { M
}, 0 },
6847 static const struct dis386 three_byte_table
[][256] = {
6849 /* THREE_BYTE_0F38 */
6852 { "pshufb", { MX
, EM
}, PREFIX_OPCODE
},
6853 { "phaddw", { MX
, EM
}, PREFIX_OPCODE
},
6854 { "phaddd", { MX
, EM
}, PREFIX_OPCODE
},
6855 { "phaddsw", { MX
, EM
}, PREFIX_OPCODE
},
6856 { "pmaddubsw", { MX
, EM
}, PREFIX_OPCODE
},
6857 { "phsubw", { MX
, EM
}, PREFIX_OPCODE
},
6858 { "phsubd", { MX
, EM
}, PREFIX_OPCODE
},
6859 { "phsubsw", { MX
, EM
}, PREFIX_OPCODE
},
6861 { "psignb", { MX
, EM
}, PREFIX_OPCODE
},
6862 { "psignw", { MX
, EM
}, PREFIX_OPCODE
},
6863 { "psignd", { MX
, EM
}, PREFIX_OPCODE
},
6864 { "pmulhrsw", { MX
, EM
}, PREFIX_OPCODE
},
6870 { PREFIX_TABLE (PREFIX_0F3810
) },
6874 { PREFIX_TABLE (PREFIX_0F3814
) },
6875 { PREFIX_TABLE (PREFIX_0F3815
) },
6877 { PREFIX_TABLE (PREFIX_0F3817
) },
6883 { "pabsb", { MX
, EM
}, PREFIX_OPCODE
},
6884 { "pabsw", { MX
, EM
}, PREFIX_OPCODE
},
6885 { "pabsd", { MX
, EM
}, PREFIX_OPCODE
},
6888 { PREFIX_TABLE (PREFIX_0F3820
) },
6889 { PREFIX_TABLE (PREFIX_0F3821
) },
6890 { PREFIX_TABLE (PREFIX_0F3822
) },
6891 { PREFIX_TABLE (PREFIX_0F3823
) },
6892 { PREFIX_TABLE (PREFIX_0F3824
) },
6893 { PREFIX_TABLE (PREFIX_0F3825
) },
6897 { PREFIX_TABLE (PREFIX_0F3828
) },
6898 { PREFIX_TABLE (PREFIX_0F3829
) },
6899 { PREFIX_TABLE (PREFIX_0F382A
) },
6900 { PREFIX_TABLE (PREFIX_0F382B
) },
6906 { PREFIX_TABLE (PREFIX_0F3830
) },
6907 { PREFIX_TABLE (PREFIX_0F3831
) },
6908 { PREFIX_TABLE (PREFIX_0F3832
) },
6909 { PREFIX_TABLE (PREFIX_0F3833
) },
6910 { PREFIX_TABLE (PREFIX_0F3834
) },
6911 { PREFIX_TABLE (PREFIX_0F3835
) },
6913 { PREFIX_TABLE (PREFIX_0F3837
) },
6915 { PREFIX_TABLE (PREFIX_0F3838
) },
6916 { PREFIX_TABLE (PREFIX_0F3839
) },
6917 { PREFIX_TABLE (PREFIX_0F383A
) },
6918 { PREFIX_TABLE (PREFIX_0F383B
) },
6919 { PREFIX_TABLE (PREFIX_0F383C
) },
6920 { PREFIX_TABLE (PREFIX_0F383D
) },
6921 { PREFIX_TABLE (PREFIX_0F383E
) },
6922 { PREFIX_TABLE (PREFIX_0F383F
) },
6924 { PREFIX_TABLE (PREFIX_0F3840
) },
6925 { PREFIX_TABLE (PREFIX_0F3841
) },
6996 { PREFIX_TABLE (PREFIX_0F3880
) },
6997 { PREFIX_TABLE (PREFIX_0F3881
) },
6998 { PREFIX_TABLE (PREFIX_0F3882
) },
7077 { PREFIX_TABLE (PREFIX_0F38C8
) },
7078 { PREFIX_TABLE (PREFIX_0F38C9
) },
7079 { PREFIX_TABLE (PREFIX_0F38CA
) },
7080 { PREFIX_TABLE (PREFIX_0F38CB
) },
7081 { PREFIX_TABLE (PREFIX_0F38CC
) },
7082 { PREFIX_TABLE (PREFIX_0F38CD
) },
7084 { PREFIX_TABLE (PREFIX_0F38CF
) },
7098 { PREFIX_TABLE (PREFIX_0F38DB
) },
7099 { PREFIX_TABLE (PREFIX_0F38DC
) },
7100 { PREFIX_TABLE (PREFIX_0F38DD
) },
7101 { PREFIX_TABLE (PREFIX_0F38DE
) },
7102 { PREFIX_TABLE (PREFIX_0F38DF
) },
7122 { PREFIX_TABLE (PREFIX_0F38F0
) },
7123 { PREFIX_TABLE (PREFIX_0F38F1
) },
7127 { PREFIX_TABLE (PREFIX_0F38F5
) },
7128 { PREFIX_TABLE (PREFIX_0F38F6
) },
7131 { PREFIX_TABLE (PREFIX_0F38F8
) },
7132 { PREFIX_TABLE (PREFIX_0F38F9
) },
7140 /* THREE_BYTE_0F3A */
7152 { PREFIX_TABLE (PREFIX_0F3A08
) },
7153 { PREFIX_TABLE (PREFIX_0F3A09
) },
7154 { PREFIX_TABLE (PREFIX_0F3A0A
) },
7155 { PREFIX_TABLE (PREFIX_0F3A0B
) },
7156 { PREFIX_TABLE (PREFIX_0F3A0C
) },
7157 { PREFIX_TABLE (PREFIX_0F3A0D
) },
7158 { PREFIX_TABLE (PREFIX_0F3A0E
) },
7159 { "palignr", { MX
, EM
, Ib
}, PREFIX_OPCODE
},
7165 { PREFIX_TABLE (PREFIX_0F3A14
) },
7166 { PREFIX_TABLE (PREFIX_0F3A15
) },
7167 { PREFIX_TABLE (PREFIX_0F3A16
) },
7168 { PREFIX_TABLE (PREFIX_0F3A17
) },
7179 { PREFIX_TABLE (PREFIX_0F3A20
) },
7180 { PREFIX_TABLE (PREFIX_0F3A21
) },
7181 { PREFIX_TABLE (PREFIX_0F3A22
) },
7215 { PREFIX_TABLE (PREFIX_0F3A40
) },
7216 { PREFIX_TABLE (PREFIX_0F3A41
) },
7217 { PREFIX_TABLE (PREFIX_0F3A42
) },
7219 { PREFIX_TABLE (PREFIX_0F3A44
) },
7251 { PREFIX_TABLE (PREFIX_0F3A60
) },
7252 { PREFIX_TABLE (PREFIX_0F3A61
) },
7253 { PREFIX_TABLE (PREFIX_0F3A62
) },
7254 { PREFIX_TABLE (PREFIX_0F3A63
) },
7372 { PREFIX_TABLE (PREFIX_0F3ACC
) },
7374 { PREFIX_TABLE (PREFIX_0F3ACE
) },
7375 { PREFIX_TABLE (PREFIX_0F3ACF
) },
7393 { PREFIX_TABLE (PREFIX_0F3ADF
) },
7433 static const struct dis386 xop_table
[][256] = {
7586 { "vpmacssww", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7587 { "vpmacsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7588 { "vpmacssdql", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7596 { "vpmacssdd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7597 { "vpmacssdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7604 { "vpmacsww", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7605 { "vpmacswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7606 { "vpmacsdql", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7614 { "vpmacsdd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7615 { "vpmacsdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7619 { "vpcmov", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7620 { "vpperm", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7623 { "vpmadcsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7641 { "vpmadcswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7653 { "vprotb", { XM
, Vex_2src_1
, Ib
}, 0 },
7654 { "vprotw", { XM
, Vex_2src_1
, Ib
}, 0 },
7655 { "vprotd", { XM
, Vex_2src_1
, Ib
}, 0 },
7656 { "vprotq", { XM
, Vex_2src_1
, Ib
}, 0 },
7666 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC
) },
7667 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD
) },
7668 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE
) },
7669 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF
) },
7702 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC
) },
7703 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED
) },
7704 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE
) },
7705 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF
) },
7729 { REG_TABLE (REG_XOP_TBM_01
) },
7730 { REG_TABLE (REG_XOP_TBM_02
) },
7748 { REG_TABLE (REG_XOP_LWPCB
) },
7872 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80
) },
7873 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81
) },
7874 { "vfrczss", { XM
, EXd
}, 0 },
7875 { "vfrczsd", { XM
, EXq
}, 0 },
7890 { "vprotb", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7891 { "vprotw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7892 { "vprotd", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7893 { "vprotq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7894 { "vpshlb", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7895 { "vpshlw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7896 { "vpshld", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7897 { "vpshlq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7899 { "vpshab", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7900 { "vpshaw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7901 { "vpshad", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7902 { "vpshaq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7945 { "vphaddbw", { XM
, EXxmm
}, 0 },
7946 { "vphaddbd", { XM
, EXxmm
}, 0 },
7947 { "vphaddbq", { XM
, EXxmm
}, 0 },
7950 { "vphaddwd", { XM
, EXxmm
}, 0 },
7951 { "vphaddwq", { XM
, EXxmm
}, 0 },
7956 { "vphadddq", { XM
, EXxmm
}, 0 },
7963 { "vphaddubw", { XM
, EXxmm
}, 0 },
7964 { "vphaddubd", { XM
, EXxmm
}, 0 },
7965 { "vphaddubq", { XM
, EXxmm
}, 0 },
7968 { "vphadduwd", { XM
, EXxmm
}, 0 },
7969 { "vphadduwq", { XM
, EXxmm
}, 0 },
7974 { "vphaddudq", { XM
, EXxmm
}, 0 },
7981 { "vphsubbw", { XM
, EXxmm
}, 0 },
7982 { "vphsubwd", { XM
, EXxmm
}, 0 },
7983 { "vphsubdq", { XM
, EXxmm
}, 0 },
8037 { "bextrS", { Gdq
, Edq
, Id
}, 0 },
8039 { REG_TABLE (REG_XOP_LWP
) },
8309 static const struct dis386 vex_table
[][256] = {
8331 { PREFIX_TABLE (PREFIX_VEX_0F10
) },
8332 { PREFIX_TABLE (PREFIX_VEX_0F11
) },
8333 { PREFIX_TABLE (PREFIX_VEX_0F12
) },
8334 { MOD_TABLE (MOD_VEX_0F13
) },
8335 { "vunpcklpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
8336 { "vunpckhpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
8337 { PREFIX_TABLE (PREFIX_VEX_0F16
) },
8338 { MOD_TABLE (MOD_VEX_0F17
) },
8358 { "vmovapX", { XM
, EXx
}, PREFIX_OPCODE
},
8359 { "vmovapX", { EXxS
, XM
}, PREFIX_OPCODE
},
8360 { PREFIX_TABLE (PREFIX_VEX_0F2A
) },
8361 { MOD_TABLE (MOD_VEX_0F2B
) },
8362 { PREFIX_TABLE (PREFIX_VEX_0F2C
) },
8363 { PREFIX_TABLE (PREFIX_VEX_0F2D
) },
8364 { PREFIX_TABLE (PREFIX_VEX_0F2E
) },
8365 { PREFIX_TABLE (PREFIX_VEX_0F2F
) },
8386 { PREFIX_TABLE (PREFIX_VEX_0F41
) },
8387 { PREFIX_TABLE (PREFIX_VEX_0F42
) },
8389 { PREFIX_TABLE (PREFIX_VEX_0F44
) },
8390 { PREFIX_TABLE (PREFIX_VEX_0F45
) },
8391 { PREFIX_TABLE (PREFIX_VEX_0F46
) },
8392 { PREFIX_TABLE (PREFIX_VEX_0F47
) },
8396 { PREFIX_TABLE (PREFIX_VEX_0F4A
) },
8397 { PREFIX_TABLE (PREFIX_VEX_0F4B
) },
8403 { MOD_TABLE (MOD_VEX_0F50
) },
8404 { PREFIX_TABLE (PREFIX_VEX_0F51
) },
8405 { PREFIX_TABLE (PREFIX_VEX_0F52
) },
8406 { PREFIX_TABLE (PREFIX_VEX_0F53
) },
8407 { "vandpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
8408 { "vandnpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
8409 { "vorpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
8410 { "vxorpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
8412 { PREFIX_TABLE (PREFIX_VEX_0F58
) },
8413 { PREFIX_TABLE (PREFIX_VEX_0F59
) },
8414 { PREFIX_TABLE (PREFIX_VEX_0F5A
) },
8415 { PREFIX_TABLE (PREFIX_VEX_0F5B
) },
8416 { PREFIX_TABLE (PREFIX_VEX_0F5C
) },
8417 { PREFIX_TABLE (PREFIX_VEX_0F5D
) },
8418 { PREFIX_TABLE (PREFIX_VEX_0F5E
) },
8419 { PREFIX_TABLE (PREFIX_VEX_0F5F
) },
8421 { PREFIX_TABLE (PREFIX_VEX_0F60
) },
8422 { PREFIX_TABLE (PREFIX_VEX_0F61
) },
8423 { PREFIX_TABLE (PREFIX_VEX_0F62
) },
8424 { PREFIX_TABLE (PREFIX_VEX_0F63
) },
8425 { PREFIX_TABLE (PREFIX_VEX_0F64
) },
8426 { PREFIX_TABLE (PREFIX_VEX_0F65
) },
8427 { PREFIX_TABLE (PREFIX_VEX_0F66
) },
8428 { PREFIX_TABLE (PREFIX_VEX_0F67
) },
8430 { PREFIX_TABLE (PREFIX_VEX_0F68
) },
8431 { PREFIX_TABLE (PREFIX_VEX_0F69
) },
8432 { PREFIX_TABLE (PREFIX_VEX_0F6A
) },
8433 { PREFIX_TABLE (PREFIX_VEX_0F6B
) },
8434 { PREFIX_TABLE (PREFIX_VEX_0F6C
) },
8435 { PREFIX_TABLE (PREFIX_VEX_0F6D
) },
8436 { PREFIX_TABLE (PREFIX_VEX_0F6E
) },
8437 { PREFIX_TABLE (PREFIX_VEX_0F6F
) },
8439 { PREFIX_TABLE (PREFIX_VEX_0F70
) },
8440 { REG_TABLE (REG_VEX_0F71
) },
8441 { REG_TABLE (REG_VEX_0F72
) },
8442 { REG_TABLE (REG_VEX_0F73
) },
8443 { PREFIX_TABLE (PREFIX_VEX_0F74
) },
8444 { PREFIX_TABLE (PREFIX_VEX_0F75
) },
8445 { PREFIX_TABLE (PREFIX_VEX_0F76
) },
8446 { PREFIX_TABLE (PREFIX_VEX_0F77
) },
8452 { PREFIX_TABLE (PREFIX_VEX_0F7C
) },
8453 { PREFIX_TABLE (PREFIX_VEX_0F7D
) },
8454 { PREFIX_TABLE (PREFIX_VEX_0F7E
) },
8455 { PREFIX_TABLE (PREFIX_VEX_0F7F
) },
8475 { PREFIX_TABLE (PREFIX_VEX_0F90
) },
8476 { PREFIX_TABLE (PREFIX_VEX_0F91
) },
8477 { PREFIX_TABLE (PREFIX_VEX_0F92
) },
8478 { PREFIX_TABLE (PREFIX_VEX_0F93
) },
8484 { PREFIX_TABLE (PREFIX_VEX_0F98
) },
8485 { PREFIX_TABLE (PREFIX_VEX_0F99
) },
8508 { REG_TABLE (REG_VEX_0FAE
) },
8531 { PREFIX_TABLE (PREFIX_VEX_0FC2
) },
8533 { PREFIX_TABLE (PREFIX_VEX_0FC4
) },
8534 { PREFIX_TABLE (PREFIX_VEX_0FC5
) },
8535 { "vshufpX", { XM
, Vex
, EXx
, Ib
}, PREFIX_OPCODE
},
8547 { PREFIX_TABLE (PREFIX_VEX_0FD0
) },
8548 { PREFIX_TABLE (PREFIX_VEX_0FD1
) },
8549 { PREFIX_TABLE (PREFIX_VEX_0FD2
) },
8550 { PREFIX_TABLE (PREFIX_VEX_0FD3
) },
8551 { PREFIX_TABLE (PREFIX_VEX_0FD4
) },
8552 { PREFIX_TABLE (PREFIX_VEX_0FD5
) },
8553 { PREFIX_TABLE (PREFIX_VEX_0FD6
) },
8554 { PREFIX_TABLE (PREFIX_VEX_0FD7
) },
8556 { PREFIX_TABLE (PREFIX_VEX_0FD8
) },
8557 { PREFIX_TABLE (PREFIX_VEX_0FD9
) },
8558 { PREFIX_TABLE (PREFIX_VEX_0FDA
) },
8559 { PREFIX_TABLE (PREFIX_VEX_0FDB
) },
8560 { PREFIX_TABLE (PREFIX_VEX_0FDC
) },
8561 { PREFIX_TABLE (PREFIX_VEX_0FDD
) },
8562 { PREFIX_TABLE (PREFIX_VEX_0FDE
) },
8563 { PREFIX_TABLE (PREFIX_VEX_0FDF
) },
8565 { PREFIX_TABLE (PREFIX_VEX_0FE0
) },
8566 { PREFIX_TABLE (PREFIX_VEX_0FE1
) },
8567 { PREFIX_TABLE (PREFIX_VEX_0FE2
) },
8568 { PREFIX_TABLE (PREFIX_VEX_0FE3
) },
8569 { PREFIX_TABLE (PREFIX_VEX_0FE4
) },
8570 { PREFIX_TABLE (PREFIX_VEX_0FE5
) },
8571 { PREFIX_TABLE (PREFIX_VEX_0FE6
) },
8572 { PREFIX_TABLE (PREFIX_VEX_0FE7
) },
8574 { PREFIX_TABLE (PREFIX_VEX_0FE8
) },
8575 { PREFIX_TABLE (PREFIX_VEX_0FE9
) },
8576 { PREFIX_TABLE (PREFIX_VEX_0FEA
) },
8577 { PREFIX_TABLE (PREFIX_VEX_0FEB
) },
8578 { PREFIX_TABLE (PREFIX_VEX_0FEC
) },
8579 { PREFIX_TABLE (PREFIX_VEX_0FED
) },
8580 { PREFIX_TABLE (PREFIX_VEX_0FEE
) },
8581 { PREFIX_TABLE (PREFIX_VEX_0FEF
) },
8583 { PREFIX_TABLE (PREFIX_VEX_0FF0
) },
8584 { PREFIX_TABLE (PREFIX_VEX_0FF1
) },
8585 { PREFIX_TABLE (PREFIX_VEX_0FF2
) },
8586 { PREFIX_TABLE (PREFIX_VEX_0FF3
) },
8587 { PREFIX_TABLE (PREFIX_VEX_0FF4
) },
8588 { PREFIX_TABLE (PREFIX_VEX_0FF5
) },
8589 { PREFIX_TABLE (PREFIX_VEX_0FF6
) },
8590 { PREFIX_TABLE (PREFIX_VEX_0FF7
) },
8592 { PREFIX_TABLE (PREFIX_VEX_0FF8
) },
8593 { PREFIX_TABLE (PREFIX_VEX_0FF9
) },
8594 { PREFIX_TABLE (PREFIX_VEX_0FFA
) },
8595 { PREFIX_TABLE (PREFIX_VEX_0FFB
) },
8596 { PREFIX_TABLE (PREFIX_VEX_0FFC
) },
8597 { PREFIX_TABLE (PREFIX_VEX_0FFD
) },
8598 { PREFIX_TABLE (PREFIX_VEX_0FFE
) },
8604 { PREFIX_TABLE (PREFIX_VEX_0F3800
) },
8605 { PREFIX_TABLE (PREFIX_VEX_0F3801
) },
8606 { PREFIX_TABLE (PREFIX_VEX_0F3802
) },
8607 { PREFIX_TABLE (PREFIX_VEX_0F3803
) },
8608 { PREFIX_TABLE (PREFIX_VEX_0F3804
) },
8609 { PREFIX_TABLE (PREFIX_VEX_0F3805
) },
8610 { PREFIX_TABLE (PREFIX_VEX_0F3806
) },
8611 { PREFIX_TABLE (PREFIX_VEX_0F3807
) },
8613 { PREFIX_TABLE (PREFIX_VEX_0F3808
) },
8614 { PREFIX_TABLE (PREFIX_VEX_0F3809
) },
8615 { PREFIX_TABLE (PREFIX_VEX_0F380A
) },
8616 { PREFIX_TABLE (PREFIX_VEX_0F380B
) },
8617 { PREFIX_TABLE (PREFIX_VEX_0F380C
) },
8618 { PREFIX_TABLE (PREFIX_VEX_0F380D
) },
8619 { PREFIX_TABLE (PREFIX_VEX_0F380E
) },
8620 { PREFIX_TABLE (PREFIX_VEX_0F380F
) },
8625 { PREFIX_TABLE (PREFIX_VEX_0F3813
) },
8628 { PREFIX_TABLE (PREFIX_VEX_0F3816
) },
8629 { PREFIX_TABLE (PREFIX_VEX_0F3817
) },
8631 { PREFIX_TABLE (PREFIX_VEX_0F3818
) },
8632 { PREFIX_TABLE (PREFIX_VEX_0F3819
) },
8633 { PREFIX_TABLE (PREFIX_VEX_0F381A
) },
8635 { PREFIX_TABLE (PREFIX_VEX_0F381C
) },
8636 { PREFIX_TABLE (PREFIX_VEX_0F381D
) },
8637 { PREFIX_TABLE (PREFIX_VEX_0F381E
) },
8640 { PREFIX_TABLE (PREFIX_VEX_0F3820
) },
8641 { PREFIX_TABLE (PREFIX_VEX_0F3821
) },
8642 { PREFIX_TABLE (PREFIX_VEX_0F3822
) },
8643 { PREFIX_TABLE (PREFIX_VEX_0F3823
) },
8644 { PREFIX_TABLE (PREFIX_VEX_0F3824
) },
8645 { PREFIX_TABLE (PREFIX_VEX_0F3825
) },
8649 { PREFIX_TABLE (PREFIX_VEX_0F3828
) },
8650 { PREFIX_TABLE (PREFIX_VEX_0F3829
) },
8651 { PREFIX_TABLE (PREFIX_VEX_0F382A
) },
8652 { PREFIX_TABLE (PREFIX_VEX_0F382B
) },
8653 { PREFIX_TABLE (PREFIX_VEX_0F382C
) },
8654 { PREFIX_TABLE (PREFIX_VEX_0F382D
) },
8655 { PREFIX_TABLE (PREFIX_VEX_0F382E
) },
8656 { PREFIX_TABLE (PREFIX_VEX_0F382F
) },
8658 { PREFIX_TABLE (PREFIX_VEX_0F3830
) },
8659 { PREFIX_TABLE (PREFIX_VEX_0F3831
) },
8660 { PREFIX_TABLE (PREFIX_VEX_0F3832
) },
8661 { PREFIX_TABLE (PREFIX_VEX_0F3833
) },
8662 { PREFIX_TABLE (PREFIX_VEX_0F3834
) },
8663 { PREFIX_TABLE (PREFIX_VEX_0F3835
) },
8664 { PREFIX_TABLE (PREFIX_VEX_0F3836
) },
8665 { PREFIX_TABLE (PREFIX_VEX_0F3837
) },
8667 { PREFIX_TABLE (PREFIX_VEX_0F3838
) },
8668 { PREFIX_TABLE (PREFIX_VEX_0F3839
) },
8669 { PREFIX_TABLE (PREFIX_VEX_0F383A
) },
8670 { PREFIX_TABLE (PREFIX_VEX_0F383B
) },
8671 { PREFIX_TABLE (PREFIX_VEX_0F383C
) },
8672 { PREFIX_TABLE (PREFIX_VEX_0F383D
) },
8673 { PREFIX_TABLE (PREFIX_VEX_0F383E
) },
8674 { PREFIX_TABLE (PREFIX_VEX_0F383F
) },
8676 { PREFIX_TABLE (PREFIX_VEX_0F3840
) },
8677 { PREFIX_TABLE (PREFIX_VEX_0F3841
) },
8681 { PREFIX_TABLE (PREFIX_VEX_0F3845
) },
8682 { PREFIX_TABLE (PREFIX_VEX_0F3846
) },
8683 { PREFIX_TABLE (PREFIX_VEX_0F3847
) },
8703 { PREFIX_TABLE (PREFIX_VEX_0F3858
) },
8704 { PREFIX_TABLE (PREFIX_VEX_0F3859
) },
8705 { PREFIX_TABLE (PREFIX_VEX_0F385A
) },
8739 { PREFIX_TABLE (PREFIX_VEX_0F3878
) },
8740 { PREFIX_TABLE (PREFIX_VEX_0F3879
) },
8761 { PREFIX_TABLE (PREFIX_VEX_0F388C
) },
8763 { PREFIX_TABLE (PREFIX_VEX_0F388E
) },
8766 { PREFIX_TABLE (PREFIX_VEX_0F3890
) },
8767 { PREFIX_TABLE (PREFIX_VEX_0F3891
) },
8768 { PREFIX_TABLE (PREFIX_VEX_0F3892
) },
8769 { PREFIX_TABLE (PREFIX_VEX_0F3893
) },
8772 { PREFIX_TABLE (PREFIX_VEX_0F3896
) },
8773 { PREFIX_TABLE (PREFIX_VEX_0F3897
) },
8775 { PREFIX_TABLE (PREFIX_VEX_0F3898
) },
8776 { PREFIX_TABLE (PREFIX_VEX_0F3899
) },
8777 { PREFIX_TABLE (PREFIX_VEX_0F389A
) },
8778 { PREFIX_TABLE (PREFIX_VEX_0F389B
) },
8779 { PREFIX_TABLE (PREFIX_VEX_0F389C
) },
8780 { PREFIX_TABLE (PREFIX_VEX_0F389D
) },
8781 { PREFIX_TABLE (PREFIX_VEX_0F389E
) },
8782 { PREFIX_TABLE (PREFIX_VEX_0F389F
) },
8790 { PREFIX_TABLE (PREFIX_VEX_0F38A6
) },
8791 { PREFIX_TABLE (PREFIX_VEX_0F38A7
) },
8793 { PREFIX_TABLE (PREFIX_VEX_0F38A8
) },
8794 { PREFIX_TABLE (PREFIX_VEX_0F38A9
) },
8795 { PREFIX_TABLE (PREFIX_VEX_0F38AA
) },
8796 { PREFIX_TABLE (PREFIX_VEX_0F38AB
) },
8797 { PREFIX_TABLE (PREFIX_VEX_0F38AC
) },
8798 { PREFIX_TABLE (PREFIX_VEX_0F38AD
) },
8799 { PREFIX_TABLE (PREFIX_VEX_0F38AE
) },
8800 { PREFIX_TABLE (PREFIX_VEX_0F38AF
) },
8808 { PREFIX_TABLE (PREFIX_VEX_0F38B6
) },
8809 { PREFIX_TABLE (PREFIX_VEX_0F38B7
) },
8811 { PREFIX_TABLE (PREFIX_VEX_0F38B8
) },
8812 { PREFIX_TABLE (PREFIX_VEX_0F38B9
) },
8813 { PREFIX_TABLE (PREFIX_VEX_0F38BA
) },
8814 { PREFIX_TABLE (PREFIX_VEX_0F38BB
) },
8815 { PREFIX_TABLE (PREFIX_VEX_0F38BC
) },
8816 { PREFIX_TABLE (PREFIX_VEX_0F38BD
) },
8817 { PREFIX_TABLE (PREFIX_VEX_0F38BE
) },
8818 { PREFIX_TABLE (PREFIX_VEX_0F38BF
) },
8836 { PREFIX_TABLE (PREFIX_VEX_0F38CF
) },
8850 { PREFIX_TABLE (PREFIX_VEX_0F38DB
) },
8851 { PREFIX_TABLE (PREFIX_VEX_0F38DC
) },
8852 { PREFIX_TABLE (PREFIX_VEX_0F38DD
) },
8853 { PREFIX_TABLE (PREFIX_VEX_0F38DE
) },
8854 { PREFIX_TABLE (PREFIX_VEX_0F38DF
) },
8876 { PREFIX_TABLE (PREFIX_VEX_0F38F2
) },
8877 { REG_TABLE (REG_VEX_0F38F3
) },
8879 { PREFIX_TABLE (PREFIX_VEX_0F38F5
) },
8880 { PREFIX_TABLE (PREFIX_VEX_0F38F6
) },
8881 { PREFIX_TABLE (PREFIX_VEX_0F38F7
) },
8895 { PREFIX_TABLE (PREFIX_VEX_0F3A00
) },
8896 { PREFIX_TABLE (PREFIX_VEX_0F3A01
) },
8897 { PREFIX_TABLE (PREFIX_VEX_0F3A02
) },
8899 { PREFIX_TABLE (PREFIX_VEX_0F3A04
) },
8900 { PREFIX_TABLE (PREFIX_VEX_0F3A05
) },
8901 { PREFIX_TABLE (PREFIX_VEX_0F3A06
) },
8904 { PREFIX_TABLE (PREFIX_VEX_0F3A08
) },
8905 { PREFIX_TABLE (PREFIX_VEX_0F3A09
) },
8906 { PREFIX_TABLE (PREFIX_VEX_0F3A0A
) },
8907 { PREFIX_TABLE (PREFIX_VEX_0F3A0B
) },
8908 { PREFIX_TABLE (PREFIX_VEX_0F3A0C
) },
8909 { PREFIX_TABLE (PREFIX_VEX_0F3A0D
) },
8910 { PREFIX_TABLE (PREFIX_VEX_0F3A0E
) },
8911 { PREFIX_TABLE (PREFIX_VEX_0F3A0F
) },
8917 { PREFIX_TABLE (PREFIX_VEX_0F3A14
) },
8918 { PREFIX_TABLE (PREFIX_VEX_0F3A15
) },
8919 { PREFIX_TABLE (PREFIX_VEX_0F3A16
) },
8920 { PREFIX_TABLE (PREFIX_VEX_0F3A17
) },
8922 { PREFIX_TABLE (PREFIX_VEX_0F3A18
) },
8923 { PREFIX_TABLE (PREFIX_VEX_0F3A19
) },
8927 { PREFIX_TABLE (PREFIX_VEX_0F3A1D
) },
8931 { PREFIX_TABLE (PREFIX_VEX_0F3A20
) },
8932 { PREFIX_TABLE (PREFIX_VEX_0F3A21
) },
8933 { PREFIX_TABLE (PREFIX_VEX_0F3A22
) },
8949 { PREFIX_TABLE (PREFIX_VEX_0F3A30
) },
8950 { PREFIX_TABLE (PREFIX_VEX_0F3A31
) },
8951 { PREFIX_TABLE (PREFIX_VEX_0F3A32
) },
8952 { PREFIX_TABLE (PREFIX_VEX_0F3A33
) },
8958 { PREFIX_TABLE (PREFIX_VEX_0F3A38
) },
8959 { PREFIX_TABLE (PREFIX_VEX_0F3A39
) },
8967 { PREFIX_TABLE (PREFIX_VEX_0F3A40
) },
8968 { PREFIX_TABLE (PREFIX_VEX_0F3A41
) },
8969 { PREFIX_TABLE (PREFIX_VEX_0F3A42
) },
8971 { PREFIX_TABLE (PREFIX_VEX_0F3A44
) },
8973 { PREFIX_TABLE (PREFIX_VEX_0F3A46
) },
8976 { PREFIX_TABLE (PREFIX_VEX_0F3A48
) },
8977 { PREFIX_TABLE (PREFIX_VEX_0F3A49
) },
8978 { PREFIX_TABLE (PREFIX_VEX_0F3A4A
) },
8979 { PREFIX_TABLE (PREFIX_VEX_0F3A4B
) },
8980 { PREFIX_TABLE (PREFIX_VEX_0F3A4C
) },
8998 { PREFIX_TABLE (PREFIX_VEX_0F3A5C
) },
8999 { PREFIX_TABLE (PREFIX_VEX_0F3A5D
) },
9000 { PREFIX_TABLE (PREFIX_VEX_0F3A5E
) },
9001 { PREFIX_TABLE (PREFIX_VEX_0F3A5F
) },
9003 { PREFIX_TABLE (PREFIX_VEX_0F3A60
) },
9004 { PREFIX_TABLE (PREFIX_VEX_0F3A61
) },
9005 { PREFIX_TABLE (PREFIX_VEX_0F3A62
) },
9006 { PREFIX_TABLE (PREFIX_VEX_0F3A63
) },
9012 { PREFIX_TABLE (PREFIX_VEX_0F3A68
) },
9013 { PREFIX_TABLE (PREFIX_VEX_0F3A69
) },
9014 { PREFIX_TABLE (PREFIX_VEX_0F3A6A
) },
9015 { PREFIX_TABLE (PREFIX_VEX_0F3A6B
) },
9016 { PREFIX_TABLE (PREFIX_VEX_0F3A6C
) },
9017 { PREFIX_TABLE (PREFIX_VEX_0F3A6D
) },
9018 { PREFIX_TABLE (PREFIX_VEX_0F3A6E
) },
9019 { PREFIX_TABLE (PREFIX_VEX_0F3A6F
) },
9030 { PREFIX_TABLE (PREFIX_VEX_0F3A78
) },
9031 { PREFIX_TABLE (PREFIX_VEX_0F3A79
) },
9032 { PREFIX_TABLE (PREFIX_VEX_0F3A7A
) },
9033 { PREFIX_TABLE (PREFIX_VEX_0F3A7B
) },
9034 { PREFIX_TABLE (PREFIX_VEX_0F3A7C
) },
9035 { PREFIX_TABLE (PREFIX_VEX_0F3A7D
) },
9036 { PREFIX_TABLE (PREFIX_VEX_0F3A7E
) },
9037 { PREFIX_TABLE (PREFIX_VEX_0F3A7F
) },
9126 { PREFIX_TABLE(PREFIX_VEX_0F3ACE
) },
9127 { PREFIX_TABLE(PREFIX_VEX_0F3ACF
) },
9145 { PREFIX_TABLE (PREFIX_VEX_0F3ADF
) },
9165 { PREFIX_TABLE (PREFIX_VEX_0F3AF0
) },
9185 #include "i386-dis-evex.h"
9187 static const struct dis386 vex_len_table
[][2] = {
9188 /* VEX_LEN_0F12_P_0_M_0 / VEX_LEN_0F12_P_2_M_0 */
9190 { "vmovlpX", { XM
, Vex128
, EXq
}, 0 },
9193 /* VEX_LEN_0F12_P_0_M_1 */
9195 { "vmovhlps", { XM
, Vex128
, EXq
}, 0 },
9198 /* VEX_LEN_0F13_M_0 */
9200 { "vmovlpX", { EXq
, XM
}, PREFIX_OPCODE
},
9203 /* VEX_LEN_0F16_P_0_M_0 / VEX_LEN_0F16_P_2_M_0 */
9205 { "vmovhpX", { XM
, Vex128
, EXq
}, 0 },
9208 /* VEX_LEN_0F16_P_0_M_1 */
9210 { "vmovlhps", { XM
, Vex128
, EXq
}, 0 },
9213 /* VEX_LEN_0F17_M_0 */
9215 { "vmovhpX", { EXq
, XM
}, PREFIX_OPCODE
},
9218 /* VEX_LEN_0F41_P_0 */
9221 { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1
) },
9223 /* VEX_LEN_0F41_P_2 */
9226 { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1
) },
9228 /* VEX_LEN_0F42_P_0 */
9231 { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1
) },
9233 /* VEX_LEN_0F42_P_2 */
9236 { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1
) },
9238 /* VEX_LEN_0F44_P_0 */
9240 { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0
) },
9242 /* VEX_LEN_0F44_P_2 */
9244 { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0
) },
9246 /* VEX_LEN_0F45_P_0 */
9249 { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1
) },
9251 /* VEX_LEN_0F45_P_2 */
9254 { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1
) },
9256 /* VEX_LEN_0F46_P_0 */
9259 { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1
) },
9261 /* VEX_LEN_0F46_P_2 */
9264 { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1
) },
9266 /* VEX_LEN_0F47_P_0 */
9269 { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1
) },
9271 /* VEX_LEN_0F47_P_2 */
9274 { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1
) },
9276 /* VEX_LEN_0F4A_P_0 */
9279 { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1
) },
9281 /* VEX_LEN_0F4A_P_2 */
9284 { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1
) },
9286 /* VEX_LEN_0F4B_P_0 */
9289 { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1
) },
9291 /* VEX_LEN_0F4B_P_2 */
9294 { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1
) },
9297 /* VEX_LEN_0F6E_P_2 */
9299 { "vmovK", { XMScalar
, Edq
}, 0 },
9302 /* VEX_LEN_0F77_P_1 */
9304 { "vzeroupper", { XX
}, 0 },
9305 { "vzeroall", { XX
}, 0 },
9308 /* VEX_LEN_0F7E_P_1 */
9310 { "vmovq", { XMScalar
, EXxmm_mq
}, 0 },
9313 /* VEX_LEN_0F7E_P_2 */
9315 { "vmovK", { Edq
, XMScalar
}, 0 },
9318 /* VEX_LEN_0F90_P_0 */
9320 { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0
) },
9323 /* VEX_LEN_0F90_P_2 */
9325 { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0
) },
9328 /* VEX_LEN_0F91_P_0 */
9330 { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0
) },
9333 /* VEX_LEN_0F91_P_2 */
9335 { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0
) },
9338 /* VEX_LEN_0F92_P_0 */
9340 { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0
) },
9343 /* VEX_LEN_0F92_P_2 */
9345 { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0
) },
9348 /* VEX_LEN_0F92_P_3 */
9350 { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0
) },
9353 /* VEX_LEN_0F93_P_0 */
9355 { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0
) },
9358 /* VEX_LEN_0F93_P_2 */
9360 { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0
) },
9363 /* VEX_LEN_0F93_P_3 */
9365 { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0
) },
9368 /* VEX_LEN_0F98_P_0 */
9370 { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0
) },
9373 /* VEX_LEN_0F98_P_2 */
9375 { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0
) },
9378 /* VEX_LEN_0F99_P_0 */
9380 { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0
) },
9383 /* VEX_LEN_0F99_P_2 */
9385 { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0
) },
9388 /* VEX_LEN_0FAE_R_2_M_0 */
9390 { "vldmxcsr", { Md
}, 0 },
9393 /* VEX_LEN_0FAE_R_3_M_0 */
9395 { "vstmxcsr", { Md
}, 0 },
9398 /* VEX_LEN_0FC4_P_2 */
9400 { "vpinsrw", { XM
, Vex128
, Edqw
, Ib
}, 0 },
9403 /* VEX_LEN_0FC5_P_2 */
9405 { "vpextrw", { Gdq
, XS
, Ib
}, 0 },
9408 /* VEX_LEN_0FD6_P_2 */
9410 { "vmovq", { EXqVexScalarS
, XMScalar
}, 0 },
9413 /* VEX_LEN_0FF7_P_2 */
9415 { "vmaskmovdqu", { XM
, XS
}, 0 },
9418 /* VEX_LEN_0F3816_P_2 */
9421 { VEX_W_TABLE (VEX_W_0F3816_P_2
) },
9424 /* VEX_LEN_0F3819_P_2 */
9427 { VEX_W_TABLE (VEX_W_0F3819_P_2
) },
9430 /* VEX_LEN_0F381A_P_2_M_0 */
9433 { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0
) },
9436 /* VEX_LEN_0F3836_P_2 */
9439 { VEX_W_TABLE (VEX_W_0F3836_P_2
) },
9442 /* VEX_LEN_0F3841_P_2 */
9444 { "vphminposuw", { XM
, EXx
}, 0 },
9447 /* VEX_LEN_0F385A_P_2_M_0 */
9450 { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0
) },
9453 /* VEX_LEN_0F38DB_P_2 */
9455 { "vaesimc", { XM
, EXx
}, 0 },
9458 /* VEX_LEN_0F38F2_P_0 */
9460 { "andnS", { Gdq
, VexGdq
, Edq
}, 0 },
9463 /* VEX_LEN_0F38F3_R_1_P_0 */
9465 { "blsrS", { VexGdq
, Edq
}, 0 },
9468 /* VEX_LEN_0F38F3_R_2_P_0 */
9470 { "blsmskS", { VexGdq
, Edq
}, 0 },
9473 /* VEX_LEN_0F38F3_R_3_P_0 */
9475 { "blsiS", { VexGdq
, Edq
}, 0 },
9478 /* VEX_LEN_0F38F5_P_0 */
9480 { "bzhiS", { Gdq
, Edq
, VexGdq
}, 0 },
9483 /* VEX_LEN_0F38F5_P_1 */
9485 { "pextS", { Gdq
, VexGdq
, Edq
}, 0 },
9488 /* VEX_LEN_0F38F5_P_3 */
9490 { "pdepS", { Gdq
, VexGdq
, Edq
}, 0 },
9493 /* VEX_LEN_0F38F6_P_3 */
9495 { "mulxS", { Gdq
, VexGdq
, Edq
}, 0 },
9498 /* VEX_LEN_0F38F7_P_0 */
9500 { "bextrS", { Gdq
, Edq
, VexGdq
}, 0 },
9503 /* VEX_LEN_0F38F7_P_1 */
9505 { "sarxS", { Gdq
, Edq
, VexGdq
}, 0 },
9508 /* VEX_LEN_0F38F7_P_2 */
9510 { "shlxS", { Gdq
, Edq
, VexGdq
}, 0 },
9513 /* VEX_LEN_0F38F7_P_3 */
9515 { "shrxS", { Gdq
, Edq
, VexGdq
}, 0 },
9518 /* VEX_LEN_0F3A00_P_2 */
9521 { VEX_W_TABLE (VEX_W_0F3A00_P_2
) },
9524 /* VEX_LEN_0F3A01_P_2 */
9527 { VEX_W_TABLE (VEX_W_0F3A01_P_2
) },
9530 /* VEX_LEN_0F3A06_P_2 */
9533 { VEX_W_TABLE (VEX_W_0F3A06_P_2
) },
9536 /* VEX_LEN_0F3A14_P_2 */
9538 { "vpextrb", { Edqb
, XM
, Ib
}, 0 },
9541 /* VEX_LEN_0F3A15_P_2 */
9543 { "vpextrw", { Edqw
, XM
, Ib
}, 0 },
9546 /* VEX_LEN_0F3A16_P_2 */
9548 { "vpextrK", { Edq
, XM
, Ib
}, 0 },
9551 /* VEX_LEN_0F3A17_P_2 */
9553 { "vextractps", { Edqd
, XM
, Ib
}, 0 },
9556 /* VEX_LEN_0F3A18_P_2 */
9559 { VEX_W_TABLE (VEX_W_0F3A18_P_2
) },
9562 /* VEX_LEN_0F3A19_P_2 */
9565 { VEX_W_TABLE (VEX_W_0F3A19_P_2
) },
9568 /* VEX_LEN_0F3A20_P_2 */
9570 { "vpinsrb", { XM
, Vex128
, Edqb
, Ib
}, 0 },
9573 /* VEX_LEN_0F3A21_P_2 */
9575 { "vinsertps", { XM
, Vex128
, EXd
, Ib
}, 0 },
9578 /* VEX_LEN_0F3A22_P_2 */
9580 { "vpinsrK", { XM
, Vex128
, Edq
, Ib
}, 0 },
9583 /* VEX_LEN_0F3A30_P_2 */
9585 { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0
) },
9588 /* VEX_LEN_0F3A31_P_2 */
9590 { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0
) },
9593 /* VEX_LEN_0F3A32_P_2 */
9595 { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0
) },
9598 /* VEX_LEN_0F3A33_P_2 */
9600 { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0
) },
9603 /* VEX_LEN_0F3A38_P_2 */
9606 { VEX_W_TABLE (VEX_W_0F3A38_P_2
) },
9609 /* VEX_LEN_0F3A39_P_2 */
9612 { VEX_W_TABLE (VEX_W_0F3A39_P_2
) },
9615 /* VEX_LEN_0F3A41_P_2 */
9617 { "vdppd", { XM
, Vex128
, EXx
, Ib
}, 0 },
9620 /* VEX_LEN_0F3A46_P_2 */
9623 { VEX_W_TABLE (VEX_W_0F3A46_P_2
) },
9626 /* VEX_LEN_0F3A60_P_2 */
9628 { "vpcmpestrm", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, 0 },
9631 /* VEX_LEN_0F3A61_P_2 */
9633 { "vpcmpestri", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, 0 },
9636 /* VEX_LEN_0F3A62_P_2 */
9638 { "vpcmpistrm", { XM
, EXx
, Ib
}, 0 },
9641 /* VEX_LEN_0F3A63_P_2 */
9643 { "vpcmpistri", { XM
, EXx
, Ib
}, 0 },
9646 /* VEX_LEN_0F3A6A_P_2 */
9648 { "vfmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
9651 /* VEX_LEN_0F3A6B_P_2 */
9653 { "vfmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
9656 /* VEX_LEN_0F3A6E_P_2 */
9658 { "vfmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
9661 /* VEX_LEN_0F3A6F_P_2 */
9663 { "vfmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
9666 /* VEX_LEN_0F3A7A_P_2 */
9668 { "vfnmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
9671 /* VEX_LEN_0F3A7B_P_2 */
9673 { "vfnmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
9676 /* VEX_LEN_0F3A7E_P_2 */
9678 { "vfnmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
9681 /* VEX_LEN_0F3A7F_P_2 */
9683 { "vfnmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
9686 /* VEX_LEN_0F3ADF_P_2 */
9688 { "vaeskeygenassist", { XM
, EXx
, Ib
}, 0 },
9691 /* VEX_LEN_0F3AF0_P_3 */
9693 { "rorxS", { Gdq
, Edq
, Ib
}, 0 },
9696 /* VEX_LEN_0FXOP_08_CC */
9698 { "vpcomb", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9701 /* VEX_LEN_0FXOP_08_CD */
9703 { "vpcomw", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9706 /* VEX_LEN_0FXOP_08_CE */
9708 { "vpcomd", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9711 /* VEX_LEN_0FXOP_08_CF */
9713 { "vpcomq", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9716 /* VEX_LEN_0FXOP_08_EC */
9718 { "vpcomub", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9721 /* VEX_LEN_0FXOP_08_ED */
9723 { "vpcomuw", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9726 /* VEX_LEN_0FXOP_08_EE */
9728 { "vpcomud", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9731 /* VEX_LEN_0FXOP_08_EF */
9733 { "vpcomuq", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9736 /* VEX_LEN_0FXOP_09_80 */
9738 { "vfrczps", { XM
, EXxmm
}, 0 },
9739 { "vfrczps", { XM
, EXymmq
}, 0 },
9742 /* VEX_LEN_0FXOP_09_81 */
9744 { "vfrczpd", { XM
, EXxmm
}, 0 },
9745 { "vfrczpd", { XM
, EXymmq
}, 0 },
9749 #include "i386-dis-evex-len.h"
9751 static const struct dis386 vex_w_table
[][2] = {
9753 /* VEX_W_0F41_P_0_LEN_1 */
9754 { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1
) },
9755 { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1
) },
9758 /* VEX_W_0F41_P_2_LEN_1 */
9759 { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1
) },
9760 { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1
) }
9763 /* VEX_W_0F42_P_0_LEN_1 */
9764 { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1
) },
9765 { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1
) },
9768 /* VEX_W_0F42_P_2_LEN_1 */
9769 { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1
) },
9770 { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1
) },
9773 /* VEX_W_0F44_P_0_LEN_0 */
9774 { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1
) },
9775 { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1
) },
9778 /* VEX_W_0F44_P_2_LEN_0 */
9779 { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1
) },
9780 { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1
) },
9783 /* VEX_W_0F45_P_0_LEN_1 */
9784 { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1
) },
9785 { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1
) },
9788 /* VEX_W_0F45_P_2_LEN_1 */
9789 { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1
) },
9790 { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1
) },
9793 /* VEX_W_0F46_P_0_LEN_1 */
9794 { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1
) },
9795 { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1
) },
9798 /* VEX_W_0F46_P_2_LEN_1 */
9799 { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1
) },
9800 { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1
) },
9803 /* VEX_W_0F47_P_0_LEN_1 */
9804 { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1
) },
9805 { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1
) },
9808 /* VEX_W_0F47_P_2_LEN_1 */
9809 { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1
) },
9810 { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1
) },
9813 /* VEX_W_0F4A_P_0_LEN_1 */
9814 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1
) },
9815 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1
) },
9818 /* VEX_W_0F4A_P_2_LEN_1 */
9819 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1
) },
9820 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1
) },
9823 /* VEX_W_0F4B_P_0_LEN_1 */
9824 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1
) },
9825 { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1
) },
9828 /* VEX_W_0F4B_P_2_LEN_1 */
9829 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1
) },
9832 /* VEX_W_0F90_P_0_LEN_0 */
9833 { "kmovw", { MaskG
, MaskE
}, 0 },
9834 { "kmovq", { MaskG
, MaskE
}, 0 },
9837 /* VEX_W_0F90_P_2_LEN_0 */
9838 { "kmovb", { MaskG
, MaskBDE
}, 0 },
9839 { "kmovd", { MaskG
, MaskBDE
}, 0 },
9842 /* VEX_W_0F91_P_0_LEN_0 */
9843 { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0
) },
9844 { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0
) },
9847 /* VEX_W_0F91_P_2_LEN_0 */
9848 { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0
) },
9849 { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0
) },
9852 /* VEX_W_0F92_P_0_LEN_0 */
9853 { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0
) },
9856 /* VEX_W_0F92_P_2_LEN_0 */
9857 { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0
) },
9860 /* VEX_W_0F93_P_0_LEN_0 */
9861 { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0
) },
9864 /* VEX_W_0F93_P_2_LEN_0 */
9865 { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0
) },
9868 /* VEX_W_0F98_P_0_LEN_0 */
9869 { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0
) },
9870 { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0
) },
9873 /* VEX_W_0F98_P_2_LEN_0 */
9874 { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0
) },
9875 { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0
) },
9878 /* VEX_W_0F99_P_0_LEN_0 */
9879 { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0
) },
9880 { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0
) },
9883 /* VEX_W_0F99_P_2_LEN_0 */
9884 { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0
) },
9885 { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0
) },
9888 /* VEX_W_0F380C_P_2 */
9889 { "vpermilps", { XM
, Vex
, EXx
}, 0 },
9892 /* VEX_W_0F380D_P_2 */
9893 { "vpermilpd", { XM
, Vex
, EXx
}, 0 },
9896 /* VEX_W_0F380E_P_2 */
9897 { "vtestps", { XM
, EXx
}, 0 },
9900 /* VEX_W_0F380F_P_2 */
9901 { "vtestpd", { XM
, EXx
}, 0 },
9904 /* VEX_W_0F3813_P_2 */
9905 { "vcvtph2ps", { XM
, EXxmmq
}, 0 },
9908 /* VEX_W_0F3816_P_2 */
9909 { "vpermps", { XM
, Vex
, EXx
}, 0 },
9912 /* VEX_W_0F3818_P_2 */
9913 { "vbroadcastss", { XM
, EXxmm_md
}, 0 },
9916 /* VEX_W_0F3819_P_2 */
9917 { "vbroadcastsd", { XM
, EXxmm_mq
}, 0 },
9920 /* VEX_W_0F381A_P_2_M_0 */
9921 { "vbroadcastf128", { XM
, Mxmm
}, 0 },
9924 /* VEX_W_0F382C_P_2_M_0 */
9925 { "vmaskmovps", { XM
, Vex
, Mx
}, 0 },
9928 /* VEX_W_0F382D_P_2_M_0 */
9929 { "vmaskmovpd", { XM
, Vex
, Mx
}, 0 },
9932 /* VEX_W_0F382E_P_2_M_0 */
9933 { "vmaskmovps", { Mx
, Vex
, XM
}, 0 },
9936 /* VEX_W_0F382F_P_2_M_0 */
9937 { "vmaskmovpd", { Mx
, Vex
, XM
}, 0 },
9940 /* VEX_W_0F3836_P_2 */
9941 { "vpermd", { XM
, Vex
, EXx
}, 0 },
9944 /* VEX_W_0F3846_P_2 */
9945 { "vpsravd", { XM
, Vex
, EXx
}, 0 },
9948 /* VEX_W_0F3858_P_2 */
9949 { "vpbroadcastd", { XM
, EXxmm_md
}, 0 },
9952 /* VEX_W_0F3859_P_2 */
9953 { "vpbroadcastq", { XM
, EXxmm_mq
}, 0 },
9956 /* VEX_W_0F385A_P_2_M_0 */
9957 { "vbroadcasti128", { XM
, Mxmm
}, 0 },
9960 /* VEX_W_0F3878_P_2 */
9961 { "vpbroadcastb", { XM
, EXxmm_mb
}, 0 },
9964 /* VEX_W_0F3879_P_2 */
9965 { "vpbroadcastw", { XM
, EXxmm_mw
}, 0 },
9968 /* VEX_W_0F38CF_P_2 */
9969 { "vgf2p8mulb", { XM
, Vex
, EXx
}, 0 },
9972 /* VEX_W_0F3A00_P_2 */
9974 { "vpermq", { XM
, EXx
, Ib
}, 0 },
9977 /* VEX_W_0F3A01_P_2 */
9979 { "vpermpd", { XM
, EXx
, Ib
}, 0 },
9982 /* VEX_W_0F3A02_P_2 */
9983 { "vpblendd", { XM
, Vex
, EXx
, Ib
}, 0 },
9986 /* VEX_W_0F3A04_P_2 */
9987 { "vpermilps", { XM
, EXx
, Ib
}, 0 },
9990 /* VEX_W_0F3A05_P_2 */
9991 { "vpermilpd", { XM
, EXx
, Ib
}, 0 },
9994 /* VEX_W_0F3A06_P_2 */
9995 { "vperm2f128", { XM
, Vex256
, EXx
, Ib
}, 0 },
9998 /* VEX_W_0F3A18_P_2 */
9999 { "vinsertf128", { XM
, Vex256
, EXxmm
, Ib
}, 0 },
10002 /* VEX_W_0F3A19_P_2 */
10003 { "vextractf128", { EXxmm
, XM
, Ib
}, 0 },
10006 /* VEX_W_0F3A1D_P_2 */
10007 { "vcvtps2ph", { EXxmmq
, XM
, EXxEVexS
, Ib
}, 0 },
10010 /* VEX_W_0F3A30_P_2_LEN_0 */
10011 { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0
) },
10012 { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0
) },
10015 /* VEX_W_0F3A31_P_2_LEN_0 */
10016 { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0
) },
10017 { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0
) },
10020 /* VEX_W_0F3A32_P_2_LEN_0 */
10021 { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0
) },
10022 { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0
) },
10025 /* VEX_W_0F3A33_P_2_LEN_0 */
10026 { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0
) },
10027 { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0
) },
10030 /* VEX_W_0F3A38_P_2 */
10031 { "vinserti128", { XM
, Vex256
, EXxmm
, Ib
}, 0 },
10034 /* VEX_W_0F3A39_P_2 */
10035 { "vextracti128", { EXxmm
, XM
, Ib
}, 0 },
10038 /* VEX_W_0F3A46_P_2 */
10039 { "vperm2i128", { XM
, Vex256
, EXx
, Ib
}, 0 },
10042 /* VEX_W_0F3A48_P_2 */
10043 { "vpermil2ps", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
10044 { "vpermil2ps", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
10047 /* VEX_W_0F3A49_P_2 */
10048 { "vpermil2pd", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
10049 { "vpermil2pd", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
10052 /* VEX_W_0F3A4A_P_2 */
10053 { "vblendvps", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10056 /* VEX_W_0F3A4B_P_2 */
10057 { "vblendvpd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10060 /* VEX_W_0F3A4C_P_2 */
10061 { "vpblendvb", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10064 /* VEX_W_0F3ACE_P_2 */
10066 { "vgf2p8affineqb", { XM
, Vex
, EXx
, Ib
}, 0 },
10069 /* VEX_W_0F3ACF_P_2 */
10071 { "vgf2p8affineinvqb", { XM
, Vex
, EXx
, Ib
}, 0 },
10074 #include "i386-dis-evex-w.h"
10077 static const struct dis386 mod_table
[][2] = {
10080 { "leaS", { Gv
, M
}, 0 },
10085 { RM_TABLE (RM_C6_REG_7
) },
10090 { RM_TABLE (RM_C7_REG_7
) },
10094 { "{l|}call^", { indirEp
}, 0 },
10098 { "{l|}jmp^", { indirEp
}, 0 },
10101 /* MOD_0F01_REG_0 */
10102 { X86_64_TABLE (X86_64_0F01_REG_0
) },
10103 { RM_TABLE (RM_0F01_REG_0
) },
10106 /* MOD_0F01_REG_1 */
10107 { X86_64_TABLE (X86_64_0F01_REG_1
) },
10108 { RM_TABLE (RM_0F01_REG_1
) },
10111 /* MOD_0F01_REG_2 */
10112 { X86_64_TABLE (X86_64_0F01_REG_2
) },
10113 { RM_TABLE (RM_0F01_REG_2
) },
10116 /* MOD_0F01_REG_3 */
10117 { X86_64_TABLE (X86_64_0F01_REG_3
) },
10118 { RM_TABLE (RM_0F01_REG_3
) },
10121 /* MOD_0F01_REG_5 */
10122 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0
) },
10123 { RM_TABLE (RM_0F01_REG_5_MOD_3
) },
10126 /* MOD_0F01_REG_7 */
10127 { "invlpg", { Mb
}, 0 },
10128 { RM_TABLE (RM_0F01_REG_7_MOD_3
) },
10131 /* MOD_0F12_PREFIX_0 */
10132 { "movlpX", { XM
, EXq
}, 0 },
10133 { "movhlps", { XM
, EXq
}, 0 },
10136 /* MOD_0F12_PREFIX_2 */
10137 { "movlpX", { XM
, EXq
}, 0 },
10141 { "movlpX", { EXq
, XM
}, PREFIX_OPCODE
},
10144 /* MOD_0F16_PREFIX_0 */
10145 { "movhpX", { XM
, EXq
}, 0 },
10146 { "movlhps", { XM
, EXq
}, 0 },
10149 /* MOD_0F16_PREFIX_2 */
10150 { "movhpX", { XM
, EXq
}, 0 },
10154 { "movhpX", { EXq
, XM
}, PREFIX_OPCODE
},
10157 /* MOD_0F18_REG_0 */
10158 { "prefetchnta", { Mb
}, 0 },
10161 /* MOD_0F18_REG_1 */
10162 { "prefetcht0", { Mb
}, 0 },
10165 /* MOD_0F18_REG_2 */
10166 { "prefetcht1", { Mb
}, 0 },
10169 /* MOD_0F18_REG_3 */
10170 { "prefetcht2", { Mb
}, 0 },
10173 /* MOD_0F18_REG_4 */
10174 { "nop/reserved", { Mb
}, 0 },
10177 /* MOD_0F18_REG_5 */
10178 { "nop/reserved", { Mb
}, 0 },
10181 /* MOD_0F18_REG_6 */
10182 { "nop/reserved", { Mb
}, 0 },
10185 /* MOD_0F18_REG_7 */
10186 { "nop/reserved", { Mb
}, 0 },
10189 /* MOD_0F1A_PREFIX_0 */
10190 { "bndldx", { Gbnd
, Mv_bnd
}, 0 },
10191 { "nopQ", { Ev
}, 0 },
10194 /* MOD_0F1B_PREFIX_0 */
10195 { "bndstx", { Mv_bnd
, Gbnd
}, 0 },
10196 { "nopQ", { Ev
}, 0 },
10199 /* MOD_0F1B_PREFIX_1 */
10200 { "bndmk", { Gbnd
, Mv_bnd
}, 0 },
10201 { "nopQ", { Ev
}, 0 },
10204 /* MOD_0F1C_PREFIX_0 */
10205 { REG_TABLE (REG_0F1C_P_0_MOD_0
) },
10206 { "nopQ", { Ev
}, 0 },
10209 /* MOD_0F1E_PREFIX_1 */
10210 { "nopQ", { Ev
}, 0 },
10211 { REG_TABLE (REG_0F1E_P_1_MOD_3
) },
10216 { "movL", { Rd
, Td
}, 0 },
10221 { "movL", { Td
, Rd
}, 0 },
10224 /* MOD_0F2B_PREFIX_0 */
10225 {"movntps", { Mx
, XM
}, PREFIX_OPCODE
},
10228 /* MOD_0F2B_PREFIX_1 */
10229 {"movntss", { Md
, XM
}, PREFIX_OPCODE
},
10232 /* MOD_0F2B_PREFIX_2 */
10233 {"movntpd", { Mx
, XM
}, PREFIX_OPCODE
},
10236 /* MOD_0F2B_PREFIX_3 */
10237 {"movntsd", { Mq
, XM
}, PREFIX_OPCODE
},
10242 { "movmskpX", { Gdq
, XS
}, PREFIX_OPCODE
},
10245 /* MOD_0F71_REG_2 */
10247 { "psrlw", { MS
, Ib
}, 0 },
10250 /* MOD_0F71_REG_4 */
10252 { "psraw", { MS
, Ib
}, 0 },
10255 /* MOD_0F71_REG_6 */
10257 { "psllw", { MS
, Ib
}, 0 },
10260 /* MOD_0F72_REG_2 */
10262 { "psrld", { MS
, Ib
}, 0 },
10265 /* MOD_0F72_REG_4 */
10267 { "psrad", { MS
, Ib
}, 0 },
10270 /* MOD_0F72_REG_6 */
10272 { "pslld", { MS
, Ib
}, 0 },
10275 /* MOD_0F73_REG_2 */
10277 { "psrlq", { MS
, Ib
}, 0 },
10280 /* MOD_0F73_REG_3 */
10282 { PREFIX_TABLE (PREFIX_0F73_REG_3
) },
10285 /* MOD_0F73_REG_6 */
10287 { "psllq", { MS
, Ib
}, 0 },
10290 /* MOD_0F73_REG_7 */
10292 { PREFIX_TABLE (PREFIX_0F73_REG_7
) },
10295 /* MOD_0FAE_REG_0 */
10296 { "fxsave", { FXSAVE
}, 0 },
10297 { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3
) },
10300 /* MOD_0FAE_REG_1 */
10301 { "fxrstor", { FXSAVE
}, 0 },
10302 { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3
) },
10305 /* MOD_0FAE_REG_2 */
10306 { "ldmxcsr", { Md
}, 0 },
10307 { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3
) },
10310 /* MOD_0FAE_REG_3 */
10311 { "stmxcsr", { Md
}, 0 },
10312 { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3
) },
10315 /* MOD_0FAE_REG_4 */
10316 { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0
) },
10317 { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3
) },
10320 /* MOD_0FAE_REG_5 */
10321 { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_0
) },
10322 { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3
) },
10325 /* MOD_0FAE_REG_6 */
10326 { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0
) },
10327 { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3
) },
10330 /* MOD_0FAE_REG_7 */
10331 { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0
) },
10332 { RM_TABLE (RM_0FAE_REG_7_MOD_3
) },
10336 { "lssS", { Gv
, Mp
}, 0 },
10340 { "lfsS", { Gv
, Mp
}, 0 },
10344 { "lgsS", { Gv
, Mp
}, 0 },
10348 { PREFIX_TABLE (PREFIX_0FC3_MOD_0
) },
10351 /* MOD_0FC7_REG_3 */
10352 { "xrstors", { FXSAVE
}, 0 },
10355 /* MOD_0FC7_REG_4 */
10356 { "xsavec", { FXSAVE
}, 0 },
10359 /* MOD_0FC7_REG_5 */
10360 { "xsaves", { FXSAVE
}, 0 },
10363 /* MOD_0FC7_REG_6 */
10364 { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0
) },
10365 { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3
) }
10368 /* MOD_0FC7_REG_7 */
10369 { "vmptrst", { Mq
}, 0 },
10370 { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3
) }
10375 { "pmovmskb", { Gdq
, MS
}, 0 },
10378 /* MOD_0FE7_PREFIX_2 */
10379 { "movntdq", { Mx
, XM
}, 0 },
10382 /* MOD_0FF0_PREFIX_3 */
10383 { "lddqu", { XM
, M
}, 0 },
10386 /* MOD_0F382A_PREFIX_2 */
10387 { "movntdqa", { XM
, Mx
}, 0 },
10390 /* MOD_0F38F5_PREFIX_2 */
10391 { "wrussK", { M
, Gdq
}, PREFIX_OPCODE
},
10394 /* MOD_0F38F6_PREFIX_0 */
10395 { "wrssK", { M
, Gdq
}, PREFIX_OPCODE
},
10398 /* MOD_0F38F8_PREFIX_1 */
10399 { "enqcmds", { Gva
, M
}, PREFIX_OPCODE
},
10402 /* MOD_0F38F8_PREFIX_2 */
10403 { "movdir64b", { Gva
, M
}, PREFIX_OPCODE
},
10406 /* MOD_0F38F8_PREFIX_3 */
10407 { "enqcmd", { Gva
, M
}, PREFIX_OPCODE
},
10410 /* MOD_0F38F9_PREFIX_0 */
10411 { "movdiri", { Ev
, Gv
}, PREFIX_OPCODE
},
10415 { "bound{S|}", { Gv
, Ma
}, 0 },
10416 { EVEX_TABLE (EVEX_0F
) },
10420 { "lesS", { Gv
, Mp
}, 0 },
10421 { VEX_C4_TABLE (VEX_0F
) },
10425 { "ldsS", { Gv
, Mp
}, 0 },
10426 { VEX_C5_TABLE (VEX_0F
) },
10429 /* MOD_VEX_0F12_PREFIX_0 */
10430 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0
) },
10431 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1
) },
10434 /* MOD_VEX_0F12_PREFIX_2 */
10435 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2_M_0
) },
10439 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0
) },
10442 /* MOD_VEX_0F16_PREFIX_0 */
10443 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0
) },
10444 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1
) },
10447 /* MOD_VEX_0F16_PREFIX_2 */
10448 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2_M_0
) },
10452 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0
) },
10456 { "vmovntpX", { Mx
, XM
}, PREFIX_OPCODE
},
10459 /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
10461 { "kandw", { MaskG
, MaskVex
, MaskR
}, 0 },
10464 /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
10466 { "kandq", { MaskG
, MaskVex
, MaskR
}, 0 },
10469 /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
10471 { "kandb", { MaskG
, MaskVex
, MaskR
}, 0 },
10474 /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
10476 { "kandd", { MaskG
, MaskVex
, MaskR
}, 0 },
10479 /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
10481 { "kandnw", { MaskG
, MaskVex
, MaskR
}, 0 },
10484 /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
10486 { "kandnq", { MaskG
, MaskVex
, MaskR
}, 0 },
10489 /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
10491 { "kandnb", { MaskG
, MaskVex
, MaskR
}, 0 },
10494 /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
10496 { "kandnd", { MaskG
, MaskVex
, MaskR
}, 0 },
10499 /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
10501 { "knotw", { MaskG
, MaskR
}, 0 },
10504 /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
10506 { "knotq", { MaskG
, MaskR
}, 0 },
10509 /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
10511 { "knotb", { MaskG
, MaskR
}, 0 },
10514 /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
10516 { "knotd", { MaskG
, MaskR
}, 0 },
10519 /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
10521 { "korw", { MaskG
, MaskVex
, MaskR
}, 0 },
10524 /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
10526 { "korq", { MaskG
, MaskVex
, MaskR
}, 0 },
10529 /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
10531 { "korb", { MaskG
, MaskVex
, MaskR
}, 0 },
10534 /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
10536 { "kord", { MaskG
, MaskVex
, MaskR
}, 0 },
10539 /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
10541 { "kxnorw", { MaskG
, MaskVex
, MaskR
}, 0 },
10544 /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
10546 { "kxnorq", { MaskG
, MaskVex
, MaskR
}, 0 },
10549 /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
10551 { "kxnorb", { MaskG
, MaskVex
, MaskR
}, 0 },
10554 /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
10556 { "kxnord", { MaskG
, MaskVex
, MaskR
}, 0 },
10559 /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
10561 { "kxorw", { MaskG
, MaskVex
, MaskR
}, 0 },
10564 /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
10566 { "kxorq", { MaskG
, MaskVex
, MaskR
}, 0 },
10569 /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
10571 { "kxorb", { MaskG
, MaskVex
, MaskR
}, 0 },
10574 /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
10576 { "kxord", { MaskG
, MaskVex
, MaskR
}, 0 },
10579 /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
10581 { "kaddw", { MaskG
, MaskVex
, MaskR
}, 0 },
10584 /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
10586 { "kaddq", { MaskG
, MaskVex
, MaskR
}, 0 },
10589 /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
10591 { "kaddb", { MaskG
, MaskVex
, MaskR
}, 0 },
10594 /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
10596 { "kaddd", { MaskG
, MaskVex
, MaskR
}, 0 },
10599 /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
10601 { "kunpckwd", { MaskG
, MaskVex
, MaskR
}, 0 },
10604 /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
10606 { "kunpckdq", { MaskG
, MaskVex
, MaskR
}, 0 },
10609 /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
10611 { "kunpckbw", { MaskG
, MaskVex
, MaskR
}, 0 },
10616 { "vmovmskpX", { Gdq
, XS
}, PREFIX_OPCODE
},
10619 /* MOD_VEX_0F71_REG_2 */
10621 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2
) },
10624 /* MOD_VEX_0F71_REG_4 */
10626 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4
) },
10629 /* MOD_VEX_0F71_REG_6 */
10631 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6
) },
10634 /* MOD_VEX_0F72_REG_2 */
10636 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2
) },
10639 /* MOD_VEX_0F72_REG_4 */
10641 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4
) },
10644 /* MOD_VEX_0F72_REG_6 */
10646 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6
) },
10649 /* MOD_VEX_0F73_REG_2 */
10651 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2
) },
10654 /* MOD_VEX_0F73_REG_3 */
10656 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3
) },
10659 /* MOD_VEX_0F73_REG_6 */
10661 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6
) },
10664 /* MOD_VEX_0F73_REG_7 */
10666 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7
) },
10669 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10670 { "kmovw", { Ew
, MaskG
}, 0 },
10674 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10675 { "kmovq", { Eq
, MaskG
}, 0 },
10679 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10680 { "kmovb", { Eb
, MaskG
}, 0 },
10684 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10685 { "kmovd", { Ed
, MaskG
}, 0 },
10689 /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
10691 { "kmovw", { MaskG
, Rdq
}, 0 },
10694 /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
10696 { "kmovb", { MaskG
, Rdq
}, 0 },
10699 /* MOD_VEX_0F92_P_3_LEN_0 */
10701 { "kmovK", { MaskG
, Rdq
}, 0 },
10704 /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
10706 { "kmovw", { Gdq
, MaskR
}, 0 },
10709 /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
10711 { "kmovb", { Gdq
, MaskR
}, 0 },
10714 /* MOD_VEX_0F93_P_3_LEN_0 */
10716 { "kmovK", { Gdq
, MaskR
}, 0 },
10719 /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
10721 { "kortestw", { MaskG
, MaskR
}, 0 },
10724 /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
10726 { "kortestq", { MaskG
, MaskR
}, 0 },
10729 /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
10731 { "kortestb", { MaskG
, MaskR
}, 0 },
10734 /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
10736 { "kortestd", { MaskG
, MaskR
}, 0 },
10739 /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
10741 { "ktestw", { MaskG
, MaskR
}, 0 },
10744 /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
10746 { "ktestq", { MaskG
, MaskR
}, 0 },
10749 /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
10751 { "ktestb", { MaskG
, MaskR
}, 0 },
10754 /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
10756 { "ktestd", { MaskG
, MaskR
}, 0 },
10759 /* MOD_VEX_0FAE_REG_2 */
10760 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0
) },
10763 /* MOD_VEX_0FAE_REG_3 */
10764 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0
) },
10767 /* MOD_VEX_0FD7_PREFIX_2 */
10769 { "vpmovmskb", { Gdq
, XS
}, 0 },
10772 /* MOD_VEX_0FE7_PREFIX_2 */
10773 { "vmovntdq", { Mx
, XM
}, 0 },
10776 /* MOD_VEX_0FF0_PREFIX_3 */
10777 { "vlddqu", { XM
, M
}, 0 },
10780 /* MOD_VEX_0F381A_PREFIX_2 */
10781 { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0
) },
10784 /* MOD_VEX_0F382A_PREFIX_2 */
10785 { "vmovntdqa", { XM
, Mx
}, 0 },
10788 /* MOD_VEX_0F382C_PREFIX_2 */
10789 { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0
) },
10792 /* MOD_VEX_0F382D_PREFIX_2 */
10793 { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0
) },
10796 /* MOD_VEX_0F382E_PREFIX_2 */
10797 { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0
) },
10800 /* MOD_VEX_0F382F_PREFIX_2 */
10801 { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0
) },
10804 /* MOD_VEX_0F385A_PREFIX_2 */
10805 { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0
) },
10808 /* MOD_VEX_0F388C_PREFIX_2 */
10809 { "vpmaskmov%LW", { XM
, Vex
, Mx
}, 0 },
10812 /* MOD_VEX_0F388E_PREFIX_2 */
10813 { "vpmaskmov%LW", { Mx
, Vex
, XM
}, 0 },
10816 /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
10818 { "kshiftrb", { MaskG
, MaskR
, Ib
}, 0 },
10821 /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
10823 { "kshiftrw", { MaskG
, MaskR
, Ib
}, 0 },
10826 /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
10828 { "kshiftrd", { MaskG
, MaskR
, Ib
}, 0 },
10831 /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
10833 { "kshiftrq", { MaskG
, MaskR
, Ib
}, 0 },
10836 /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
10838 { "kshiftlb", { MaskG
, MaskR
, Ib
}, 0 },
10841 /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
10843 { "kshiftlw", { MaskG
, MaskR
, Ib
}, 0 },
10846 /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
10848 { "kshiftld", { MaskG
, MaskR
, Ib
}, 0 },
10851 /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
10853 { "kshiftlq", { MaskG
, MaskR
, Ib
}, 0 },
10856 #include "i386-dis-evex-mod.h"
10859 static const struct dis386 rm_table
[][8] = {
10862 { "xabort", { Skip_MODRM
, Ib
}, 0 },
10866 { "xbeginT", { Skip_MODRM
, Jdqw
}, 0 },
10869 /* RM_0F01_REG_0 */
10870 { "enclv", { Skip_MODRM
}, 0 },
10871 { "vmcall", { Skip_MODRM
}, 0 },
10872 { "vmlaunch", { Skip_MODRM
}, 0 },
10873 { "vmresume", { Skip_MODRM
}, 0 },
10874 { "vmxoff", { Skip_MODRM
}, 0 },
10875 { "pconfig", { Skip_MODRM
}, 0 },
10878 /* RM_0F01_REG_1 */
10879 { "monitor", { { OP_Monitor
, 0 } }, 0 },
10880 { "mwait", { { OP_Mwait
, 0 } }, 0 },
10881 { "clac", { Skip_MODRM
}, 0 },
10882 { "stac", { Skip_MODRM
}, 0 },
10886 { "encls", { Skip_MODRM
}, 0 },
10889 /* RM_0F01_REG_2 */
10890 { "xgetbv", { Skip_MODRM
}, 0 },
10891 { "xsetbv", { Skip_MODRM
}, 0 },
10894 { "vmfunc", { Skip_MODRM
}, 0 },
10895 { "xend", { Skip_MODRM
}, 0 },
10896 { "xtest", { Skip_MODRM
}, 0 },
10897 { "enclu", { Skip_MODRM
}, 0 },
10900 /* RM_0F01_REG_3 */
10901 { "vmrun", { Skip_MODRM
}, 0 },
10902 { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1
) },
10903 { "vmload", { Skip_MODRM
}, 0 },
10904 { "vmsave", { Skip_MODRM
}, 0 },
10905 { "stgi", { Skip_MODRM
}, 0 },
10906 { "clgi", { Skip_MODRM
}, 0 },
10907 { "skinit", { Skip_MODRM
}, 0 },
10908 { "invlpga", { Skip_MODRM
}, 0 },
10911 /* RM_0F01_REG_5_MOD_3 */
10912 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0
) },
10913 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1
) },
10914 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2
) },
10918 { "rdpkru", { Skip_MODRM
}, 0 },
10919 { "wrpkru", { Skip_MODRM
}, 0 },
10922 /* RM_0F01_REG_7_MOD_3 */
10923 { "swapgs", { Skip_MODRM
}, 0 },
10924 { "rdtscp", { Skip_MODRM
}, 0 },
10925 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2
) },
10926 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_3
) },
10927 { "clzero", { Skip_MODRM
}, 0 },
10928 { "rdpru", { Skip_MODRM
}, 0 },
10931 /* RM_0F1E_P_1_MOD_3_REG_7 */
10932 { "nopQ", { Ev
}, 0 },
10933 { "nopQ", { Ev
}, 0 },
10934 { "endbr64", { Skip_MODRM
}, PREFIX_OPCODE
},
10935 { "endbr32", { Skip_MODRM
}, PREFIX_OPCODE
},
10936 { "nopQ", { Ev
}, 0 },
10937 { "nopQ", { Ev
}, 0 },
10938 { "nopQ", { Ev
}, 0 },
10939 { "nopQ", { Ev
}, 0 },
10942 /* RM_0FAE_REG_6_MOD_3 */
10943 { "mfence", { Skip_MODRM
}, 0 },
10946 /* RM_0FAE_REG_7_MOD_3 */
10947 { "sfence", { Skip_MODRM
}, 0 },
10952 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
10954 /* We use the high bit to indicate different name for the same
10956 #define REP_PREFIX (0xf3 | 0x100)
10957 #define XACQUIRE_PREFIX (0xf2 | 0x200)
10958 #define XRELEASE_PREFIX (0xf3 | 0x400)
10959 #define BND_PREFIX (0xf2 | 0x400)
10960 #define NOTRACK_PREFIX (0x3e | 0x100)
10962 /* Remember if the current op is a jump instruction. */
10963 static bfd_boolean op_is_jump
= FALSE
;
10968 int newrex
, i
, length
;
10973 last_lock_prefix
= -1;
10974 last_repz_prefix
= -1;
10975 last_repnz_prefix
= -1;
10976 last_data_prefix
= -1;
10977 last_addr_prefix
= -1;
10978 last_rex_prefix
= -1;
10979 last_seg_prefix
= -1;
10981 active_seg_prefix
= 0;
10982 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
10983 all_prefixes
[i
] = 0;
10986 /* The maximum instruction length is 15bytes. */
10987 while (length
< MAX_CODE_LENGTH
- 1)
10989 FETCH_DATA (the_info
, codep
+ 1);
10993 /* REX prefixes family. */
11010 if (address_mode
== mode_64bit
)
11014 last_rex_prefix
= i
;
11017 prefixes
|= PREFIX_REPZ
;
11018 last_repz_prefix
= i
;
11021 prefixes
|= PREFIX_REPNZ
;
11022 last_repnz_prefix
= i
;
11025 prefixes
|= PREFIX_LOCK
;
11026 last_lock_prefix
= i
;
11029 prefixes
|= PREFIX_CS
;
11030 last_seg_prefix
= i
;
11031 active_seg_prefix
= PREFIX_CS
;
11034 prefixes
|= PREFIX_SS
;
11035 last_seg_prefix
= i
;
11036 active_seg_prefix
= PREFIX_SS
;
11039 prefixes
|= PREFIX_DS
;
11040 last_seg_prefix
= i
;
11041 active_seg_prefix
= PREFIX_DS
;
11044 prefixes
|= PREFIX_ES
;
11045 last_seg_prefix
= i
;
11046 active_seg_prefix
= PREFIX_ES
;
11049 prefixes
|= PREFIX_FS
;
11050 last_seg_prefix
= i
;
11051 active_seg_prefix
= PREFIX_FS
;
11054 prefixes
|= PREFIX_GS
;
11055 last_seg_prefix
= i
;
11056 active_seg_prefix
= PREFIX_GS
;
11059 prefixes
|= PREFIX_DATA
;
11060 last_data_prefix
= i
;
11063 prefixes
|= PREFIX_ADDR
;
11064 last_addr_prefix
= i
;
11067 /* fwait is really an instruction. If there are prefixes
11068 before the fwait, they belong to the fwait, *not* to the
11069 following instruction. */
11071 if (prefixes
|| rex
)
11073 prefixes
|= PREFIX_FWAIT
;
11075 /* This ensures that the previous REX prefixes are noticed
11076 as unused prefixes, as in the return case below. */
11080 prefixes
= PREFIX_FWAIT
;
11085 /* Rex is ignored when followed by another prefix. */
11091 if (*codep
!= FWAIT_OPCODE
)
11092 all_prefixes
[i
++] = *codep
;
11100 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
11103 static const char *
11104 prefix_name (int pref
, int sizeflag
)
11106 static const char *rexes
[16] =
11109 "rex.B", /* 0x41 */
11110 "rex.X", /* 0x42 */
11111 "rex.XB", /* 0x43 */
11112 "rex.R", /* 0x44 */
11113 "rex.RB", /* 0x45 */
11114 "rex.RX", /* 0x46 */
11115 "rex.RXB", /* 0x47 */
11116 "rex.W", /* 0x48 */
11117 "rex.WB", /* 0x49 */
11118 "rex.WX", /* 0x4a */
11119 "rex.WXB", /* 0x4b */
11120 "rex.WR", /* 0x4c */
11121 "rex.WRB", /* 0x4d */
11122 "rex.WRX", /* 0x4e */
11123 "rex.WRXB", /* 0x4f */
11128 /* REX prefixes family. */
11145 return rexes
[pref
- 0x40];
11165 return (sizeflag
& DFLAG
) ? "data16" : "data32";
11167 if (address_mode
== mode_64bit
)
11168 return (sizeflag
& AFLAG
) ? "addr32" : "addr64";
11170 return (sizeflag
& AFLAG
) ? "addr16" : "addr32";
11175 case XACQUIRE_PREFIX
:
11177 case XRELEASE_PREFIX
:
11181 case NOTRACK_PREFIX
:
11188 static char op_out
[MAX_OPERANDS
][100];
11189 static int op_ad
, op_index
[MAX_OPERANDS
];
11190 static int two_source_ops
;
11191 static bfd_vma op_address
[MAX_OPERANDS
];
11192 static bfd_vma op_riprel
[MAX_OPERANDS
];
11193 static bfd_vma start_pc
;
11196 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
11197 * (see topic "Redundant prefixes" in the "Differences from 8086"
11198 * section of the "Virtual 8086 Mode" chapter.)
11199 * 'pc' should be the address of this instruction, it will
11200 * be used to print the target address if this is a relative jump or call
11201 * The function returns the length of this instruction in bytes.
11204 static char intel_syntax
;
11205 static char intel_mnemonic
= !SYSV386_COMPAT
;
11206 static char open_char
;
11207 static char close_char
;
11208 static char separator_char
;
11209 static char scale_char
;
11217 static enum x86_64_isa isa64
;
11219 /* Here for backwards compatibility. When gdb stops using
11220 print_insn_i386_att and print_insn_i386_intel these functions can
11221 disappear, and print_insn_i386 be merged into print_insn. */
11223 print_insn_i386_att (bfd_vma pc
, disassemble_info
*info
)
11227 return print_insn (pc
, info
);
11231 print_insn_i386_intel (bfd_vma pc
, disassemble_info
*info
)
11235 return print_insn (pc
, info
);
11239 print_insn_i386 (bfd_vma pc
, disassemble_info
*info
)
11243 return print_insn (pc
, info
);
11247 print_i386_disassembler_options (FILE *stream
)
11249 fprintf (stream
, _("\n\
11250 The following i386/x86-64 specific disassembler options are supported for use\n\
11251 with the -M switch (multiple options should be separated by commas):\n"));
11253 fprintf (stream
, _(" x86-64 Disassemble in 64bit mode\n"));
11254 fprintf (stream
, _(" i386 Disassemble in 32bit mode\n"));
11255 fprintf (stream
, _(" i8086 Disassemble in 16bit mode\n"));
11256 fprintf (stream
, _(" att Display instruction in AT&T syntax\n"));
11257 fprintf (stream
, _(" intel Display instruction in Intel syntax\n"));
11258 fprintf (stream
, _(" att-mnemonic\n"
11259 " Display instruction in AT&T mnemonic\n"));
11260 fprintf (stream
, _(" intel-mnemonic\n"
11261 " Display instruction in Intel mnemonic\n"));
11262 fprintf (stream
, _(" addr64 Assume 64bit address size\n"));
11263 fprintf (stream
, _(" addr32 Assume 32bit address size\n"));
11264 fprintf (stream
, _(" addr16 Assume 16bit address size\n"));
11265 fprintf (stream
, _(" data32 Assume 32bit data size\n"));
11266 fprintf (stream
, _(" data16 Assume 16bit data size\n"));
11267 fprintf (stream
, _(" suffix Always display instruction suffix in AT&T syntax\n"));
11268 fprintf (stream
, _(" amd64 Display instruction in AMD64 ISA\n"));
11269 fprintf (stream
, _(" intel64 Display instruction in Intel64 ISA\n"));
11273 static const struct dis386 bad_opcode
= { "(bad)", { XX
}, 0 };
11275 /* Get a pointer to struct dis386 with a valid name. */
11277 static const struct dis386
*
11278 get_valid_dis386 (const struct dis386
*dp
, disassemble_info
*info
)
11280 int vindex
, vex_table_index
;
11282 if (dp
->name
!= NULL
)
11285 switch (dp
->op
[0].bytemode
)
11287 case USE_REG_TABLE
:
11288 dp
= ®_table
[dp
->op
[1].bytemode
][modrm
.reg
];
11291 case USE_MOD_TABLE
:
11292 vindex
= modrm
.mod
== 0x3 ? 1 : 0;
11293 dp
= &mod_table
[dp
->op
[1].bytemode
][vindex
];
11297 dp
= &rm_table
[dp
->op
[1].bytemode
][modrm
.rm
];
11300 case USE_PREFIX_TABLE
:
11303 /* The prefix in VEX is implicit. */
11304 switch (vex
.prefix
)
11309 case REPE_PREFIX_OPCODE
:
11312 case DATA_PREFIX_OPCODE
:
11315 case REPNE_PREFIX_OPCODE
:
11325 int last_prefix
= -1;
11328 /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
11329 When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
11331 if ((prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0)
11333 if (last_repz_prefix
> last_repnz_prefix
)
11336 prefix
= PREFIX_REPZ
;
11337 last_prefix
= last_repz_prefix
;
11342 prefix
= PREFIX_REPNZ
;
11343 last_prefix
= last_repnz_prefix
;
11346 /* Check if prefix should be ignored. */
11347 if ((((prefix_table
[dp
->op
[1].bytemode
][vindex
].prefix_requirement
11348 & PREFIX_IGNORED
) >> PREFIX_IGNORED_SHIFT
)
11353 if (vindex
== 0 && (prefixes
& PREFIX_DATA
) != 0)
11356 prefix
= PREFIX_DATA
;
11357 last_prefix
= last_data_prefix
;
11362 used_prefixes
|= prefix
;
11363 all_prefixes
[last_prefix
] = 0;
11366 dp
= &prefix_table
[dp
->op
[1].bytemode
][vindex
];
11369 case USE_X86_64_TABLE
:
11370 vindex
= address_mode
== mode_64bit
? 1 : 0;
11371 dp
= &x86_64_table
[dp
->op
[1].bytemode
][vindex
];
11374 case USE_3BYTE_TABLE
:
11375 FETCH_DATA (info
, codep
+ 2);
11377 dp
= &three_byte_table
[dp
->op
[1].bytemode
][vindex
];
11379 modrm
.mod
= (*codep
>> 6) & 3;
11380 modrm
.reg
= (*codep
>> 3) & 7;
11381 modrm
.rm
= *codep
& 7;
11384 case USE_VEX_LEN_TABLE
:
11388 switch (vex
.length
)
11401 dp
= &vex_len_table
[dp
->op
[1].bytemode
][vindex
];
11404 case USE_EVEX_LEN_TABLE
:
11408 switch (vex
.length
)
11424 dp
= &evex_len_table
[dp
->op
[1].bytemode
][vindex
];
11427 case USE_XOP_8F_TABLE
:
11428 FETCH_DATA (info
, codep
+ 3);
11429 rex
= ~(*codep
>> 5) & 0x7;
11431 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
11432 switch ((*codep
& 0x1f))
11438 vex_table_index
= XOP_08
;
11441 vex_table_index
= XOP_09
;
11444 vex_table_index
= XOP_0A
;
11448 vex
.w
= *codep
& 0x80;
11449 if (vex
.w
&& address_mode
== mode_64bit
)
11452 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11453 if (address_mode
!= mode_64bit
)
11455 /* In 16/32-bit mode REX_B is silently ignored. */
11459 vex
.length
= (*codep
& 0x4) ? 256 : 128;
11460 switch ((*codep
& 0x3))
11465 vex
.prefix
= DATA_PREFIX_OPCODE
;
11468 vex
.prefix
= REPE_PREFIX_OPCODE
;
11471 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11478 dp
= &xop_table
[vex_table_index
][vindex
];
11481 FETCH_DATA (info
, codep
+ 1);
11482 modrm
.mod
= (*codep
>> 6) & 3;
11483 modrm
.reg
= (*codep
>> 3) & 7;
11484 modrm
.rm
= *codep
& 7;
11487 case USE_VEX_C4_TABLE
:
11489 FETCH_DATA (info
, codep
+ 3);
11490 rex
= ~(*codep
>> 5) & 0x7;
11491 switch ((*codep
& 0x1f))
11497 vex_table_index
= VEX_0F
;
11500 vex_table_index
= VEX_0F38
;
11503 vex_table_index
= VEX_0F3A
;
11507 vex
.w
= *codep
& 0x80;
11508 if (address_mode
== mode_64bit
)
11515 /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
11516 is ignored, other REX bits are 0 and the highest bit in
11517 VEX.vvvv is also ignored (but we mustn't clear it here). */
11520 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11521 vex
.length
= (*codep
& 0x4) ? 256 : 128;
11522 switch ((*codep
& 0x3))
11527 vex
.prefix
= DATA_PREFIX_OPCODE
;
11530 vex
.prefix
= REPE_PREFIX_OPCODE
;
11533 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11540 dp
= &vex_table
[vex_table_index
][vindex
];
11542 /* There is no MODRM byte for VEX0F 77. */
11543 if (vex_table_index
!= VEX_0F
|| vindex
!= 0x77)
11545 FETCH_DATA (info
, codep
+ 1);
11546 modrm
.mod
= (*codep
>> 6) & 3;
11547 modrm
.reg
= (*codep
>> 3) & 7;
11548 modrm
.rm
= *codep
& 7;
11552 case USE_VEX_C5_TABLE
:
11554 FETCH_DATA (info
, codep
+ 2);
11555 rex
= (*codep
& 0x80) ? 0 : REX_R
;
11557 /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
11559 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11560 vex
.length
= (*codep
& 0x4) ? 256 : 128;
11561 switch ((*codep
& 0x3))
11566 vex
.prefix
= DATA_PREFIX_OPCODE
;
11569 vex
.prefix
= REPE_PREFIX_OPCODE
;
11572 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11579 dp
= &vex_table
[dp
->op
[1].bytemode
][vindex
];
11581 /* There is no MODRM byte for VEX 77. */
11582 if (vindex
!= 0x77)
11584 FETCH_DATA (info
, codep
+ 1);
11585 modrm
.mod
= (*codep
>> 6) & 3;
11586 modrm
.reg
= (*codep
>> 3) & 7;
11587 modrm
.rm
= *codep
& 7;
11591 case USE_VEX_W_TABLE
:
11595 dp
= &vex_w_table
[dp
->op
[1].bytemode
][vex
.w
? 1 : 0];
11598 case USE_EVEX_TABLE
:
11599 two_source_ops
= 0;
11602 FETCH_DATA (info
, codep
+ 4);
11603 /* The first byte after 0x62. */
11604 rex
= ~(*codep
>> 5) & 0x7;
11605 vex
.r
= *codep
& 0x10;
11606 switch ((*codep
& 0xf))
11609 return &bad_opcode
;
11611 vex_table_index
= EVEX_0F
;
11614 vex_table_index
= EVEX_0F38
;
11617 vex_table_index
= EVEX_0F3A
;
11621 /* The second byte after 0x62. */
11623 vex
.w
= *codep
& 0x80;
11624 if (vex
.w
&& address_mode
== mode_64bit
)
11627 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11630 if (!(*codep
& 0x4))
11631 return &bad_opcode
;
11633 switch ((*codep
& 0x3))
11638 vex
.prefix
= DATA_PREFIX_OPCODE
;
11641 vex
.prefix
= REPE_PREFIX_OPCODE
;
11644 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11648 /* The third byte after 0x62. */
11651 /* Remember the static rounding bits. */
11652 vex
.ll
= (*codep
>> 5) & 3;
11653 vex
.b
= (*codep
& 0x10) != 0;
11655 vex
.v
= *codep
& 0x8;
11656 vex
.mask_register_specifier
= *codep
& 0x7;
11657 vex
.zeroing
= *codep
& 0x80;
11659 if (address_mode
!= mode_64bit
)
11661 /* In 16/32-bit mode silently ignore following bits. */
11671 dp
= &evex_table
[vex_table_index
][vindex
];
11673 FETCH_DATA (info
, codep
+ 1);
11674 modrm
.mod
= (*codep
>> 6) & 3;
11675 modrm
.reg
= (*codep
>> 3) & 7;
11676 modrm
.rm
= *codep
& 7;
11678 /* Set vector length. */
11679 if (modrm
.mod
== 3 && vex
.b
)
11695 return &bad_opcode
;
11708 if (dp
->name
!= NULL
)
11711 return get_valid_dis386 (dp
, info
);
11715 get_sib (disassemble_info
*info
, int sizeflag
)
11717 /* If modrm.mod == 3, operand must be register. */
11719 && ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
11723 FETCH_DATA (info
, codep
+ 2);
11724 sib
.index
= (codep
[1] >> 3) & 7;
11725 sib
.scale
= (codep
[1] >> 6) & 3;
11726 sib
.base
= codep
[1] & 7;
11731 print_insn (bfd_vma pc
, disassemble_info
*info
)
11733 const struct dis386
*dp
;
11735 char *op_txt
[MAX_OPERANDS
];
11737 int sizeflag
, orig_sizeflag
;
11739 struct dis_private priv
;
11742 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
11743 if ((info
->mach
& bfd_mach_i386_i386
) != 0)
11744 address_mode
= mode_32bit
;
11745 else if (info
->mach
== bfd_mach_i386_i8086
)
11747 address_mode
= mode_16bit
;
11748 priv
.orig_sizeflag
= 0;
11751 address_mode
= mode_64bit
;
11753 if (intel_syntax
== (char) -1)
11754 intel_syntax
= (info
->mach
& bfd_mach_i386_intel_syntax
) != 0;
11756 for (p
= info
->disassembler_options
; p
!= NULL
; )
11758 if (CONST_STRNEQ (p
, "amd64"))
11760 else if (CONST_STRNEQ (p
, "intel64"))
11762 else if (CONST_STRNEQ (p
, "x86-64"))
11764 address_mode
= mode_64bit
;
11765 priv
.orig_sizeflag
|= AFLAG
| DFLAG
;
11767 else if (CONST_STRNEQ (p
, "i386"))
11769 address_mode
= mode_32bit
;
11770 priv
.orig_sizeflag
|= AFLAG
| DFLAG
;
11772 else if (CONST_STRNEQ (p
, "i8086"))
11774 address_mode
= mode_16bit
;
11775 priv
.orig_sizeflag
&= ~(AFLAG
| DFLAG
);
11777 else if (CONST_STRNEQ (p
, "intel"))
11780 if (CONST_STRNEQ (p
+ 5, "-mnemonic"))
11781 intel_mnemonic
= 1;
11783 else if (CONST_STRNEQ (p
, "att"))
11786 if (CONST_STRNEQ (p
+ 3, "-mnemonic"))
11787 intel_mnemonic
= 0;
11789 else if (CONST_STRNEQ (p
, "addr"))
11791 if (address_mode
== mode_64bit
)
11793 if (p
[4] == '3' && p
[5] == '2')
11794 priv
.orig_sizeflag
&= ~AFLAG
;
11795 else if (p
[4] == '6' && p
[5] == '4')
11796 priv
.orig_sizeflag
|= AFLAG
;
11800 if (p
[4] == '1' && p
[5] == '6')
11801 priv
.orig_sizeflag
&= ~AFLAG
;
11802 else if (p
[4] == '3' && p
[5] == '2')
11803 priv
.orig_sizeflag
|= AFLAG
;
11806 else if (CONST_STRNEQ (p
, "data"))
11808 if (p
[4] == '1' && p
[5] == '6')
11809 priv
.orig_sizeflag
&= ~DFLAG
;
11810 else if (p
[4] == '3' && p
[5] == '2')
11811 priv
.orig_sizeflag
|= DFLAG
;
11813 else if (CONST_STRNEQ (p
, "suffix"))
11814 priv
.orig_sizeflag
|= SUFFIX_ALWAYS
;
11816 p
= strchr (p
, ',');
11821 if (address_mode
== mode_64bit
&& sizeof (bfd_vma
) < 8)
11823 (*info
->fprintf_func
) (info
->stream
,
11824 _("64-bit address is disabled"));
11830 names64
= intel_names64
;
11831 names32
= intel_names32
;
11832 names16
= intel_names16
;
11833 names8
= intel_names8
;
11834 names8rex
= intel_names8rex
;
11835 names_seg
= intel_names_seg
;
11836 names_mm
= intel_names_mm
;
11837 names_bnd
= intel_names_bnd
;
11838 names_xmm
= intel_names_xmm
;
11839 names_ymm
= intel_names_ymm
;
11840 names_zmm
= intel_names_zmm
;
11841 index64
= intel_index64
;
11842 index32
= intel_index32
;
11843 names_mask
= intel_names_mask
;
11844 index16
= intel_index16
;
11847 separator_char
= '+';
11852 names64
= att_names64
;
11853 names32
= att_names32
;
11854 names16
= att_names16
;
11855 names8
= att_names8
;
11856 names8rex
= att_names8rex
;
11857 names_seg
= att_names_seg
;
11858 names_mm
= att_names_mm
;
11859 names_bnd
= att_names_bnd
;
11860 names_xmm
= att_names_xmm
;
11861 names_ymm
= att_names_ymm
;
11862 names_zmm
= att_names_zmm
;
11863 index64
= att_index64
;
11864 index32
= att_index32
;
11865 names_mask
= att_names_mask
;
11866 index16
= att_index16
;
11869 separator_char
= ',';
11873 /* The output looks better if we put 7 bytes on a line, since that
11874 puts most long word instructions on a single line. Use 8 bytes
11876 if ((info
->mach
& bfd_mach_l1om
) != 0)
11877 info
->bytes_per_line
= 8;
11879 info
->bytes_per_line
= 7;
11881 info
->private_data
= &priv
;
11882 priv
.max_fetched
= priv
.the_buffer
;
11883 priv
.insn_start
= pc
;
11886 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
11894 start_codep
= priv
.the_buffer
;
11895 codep
= priv
.the_buffer
;
11897 if (OPCODES_SIGSETJMP (priv
.bailout
) != 0)
11901 /* Getting here means we tried for data but didn't get it. That
11902 means we have an incomplete instruction of some sort. Just
11903 print the first byte as a prefix or a .byte pseudo-op. */
11904 if (codep
> priv
.the_buffer
)
11906 name
= prefix_name (priv
.the_buffer
[0], priv
.orig_sizeflag
);
11908 (*info
->fprintf_func
) (info
->stream
, "%s", name
);
11911 /* Just print the first byte as a .byte instruction. */
11912 (*info
->fprintf_func
) (info
->stream
, ".byte 0x%x",
11913 (unsigned int) priv
.the_buffer
[0]);
11923 sizeflag
= priv
.orig_sizeflag
;
11925 if (!ckprefix () || rex_used
)
11927 /* Too many prefixes or unused REX prefixes. */
11929 i
< (int) ARRAY_SIZE (all_prefixes
) && all_prefixes
[i
];
11931 (*info
->fprintf_func
) (info
->stream
, "%s%s",
11933 prefix_name (all_prefixes
[i
], sizeflag
));
11937 insn_codep
= codep
;
11939 FETCH_DATA (info
, codep
+ 1);
11940 two_source_ops
= (*codep
== 0x62) || (*codep
== 0xc8);
11942 if (((prefixes
& PREFIX_FWAIT
)
11943 && ((*codep
< 0xd8) || (*codep
> 0xdf))))
11945 /* Handle prefixes before fwait. */
11946 for (i
= 0; i
< fwait_prefix
&& all_prefixes
[i
];
11948 (*info
->fprintf_func
) (info
->stream
, "%s ",
11949 prefix_name (all_prefixes
[i
], sizeflag
));
11950 (*info
->fprintf_func
) (info
->stream
, "fwait");
11954 if (*codep
== 0x0f)
11956 unsigned char threebyte
;
11959 FETCH_DATA (info
, codep
+ 1);
11960 threebyte
= *codep
;
11961 dp
= &dis386_twobyte
[threebyte
];
11962 need_modrm
= twobyte_has_modrm
[*codep
];
11967 dp
= &dis386
[*codep
];
11968 need_modrm
= onebyte_has_modrm
[*codep
];
11972 /* Save sizeflag for printing the extra prefixes later before updating
11973 it for mnemonic and operand processing. The prefix names depend
11974 only on the address mode. */
11975 orig_sizeflag
= sizeflag
;
11976 if (prefixes
& PREFIX_ADDR
)
11978 if ((prefixes
& PREFIX_DATA
))
11984 FETCH_DATA (info
, codep
+ 1);
11985 modrm
.mod
= (*codep
>> 6) & 3;
11986 modrm
.reg
= (*codep
>> 3) & 7;
11987 modrm
.rm
= *codep
& 7;
11993 memset (&vex
, 0, sizeof (vex
));
11995 if (dp
->name
== NULL
&& dp
->op
[0].bytemode
== FLOATCODE
)
11997 get_sib (info
, sizeflag
);
11998 dofloat (sizeflag
);
12002 dp
= get_valid_dis386 (dp
, info
);
12003 if (dp
!= NULL
&& putop (dp
->name
, sizeflag
) == 0)
12005 get_sib (info
, sizeflag
);
12006 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12009 op_ad
= MAX_OPERANDS
- 1 - i
;
12011 (*dp
->op
[i
].rtn
) (dp
->op
[i
].bytemode
, sizeflag
);
12012 /* For EVEX instruction after the last operand masking
12013 should be printed. */
12014 if (i
== 0 && vex
.evex
)
12016 /* Don't print {%k0}. */
12017 if (vex
.mask_register_specifier
)
12020 oappend (names_mask
[vex
.mask_register_specifier
]);
12030 /* Clear instruction information. */
12033 the_info
->insn_info_valid
= 0;
12034 the_info
->branch_delay_insns
= 0;
12035 the_info
->data_size
= 0;
12036 the_info
->insn_type
= dis_noninsn
;
12037 the_info
->target
= 0;
12038 the_info
->target2
= 0;
12041 /* Reset jump operation indicator. */
12042 op_is_jump
= FALSE
;
12045 int jump_detection
= 0;
12047 /* Extract flags. */
12048 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12050 if ((dp
->op
[i
].rtn
== OP_J
)
12051 || (dp
->op
[i
].rtn
== OP_indirE
))
12052 jump_detection
|= 1;
12053 else if ((dp
->op
[i
].rtn
== BND_Fixup
)
12054 || (!dp
->op
[i
].rtn
&& !dp
->op
[i
].bytemode
))
12055 jump_detection
|= 2;
12056 else if ((dp
->op
[i
].bytemode
== cond_jump_mode
)
12057 || (dp
->op
[i
].bytemode
== loop_jcxz_mode
))
12058 jump_detection
|= 4;
12061 /* Determine if this is a jump or branch. */
12062 if ((jump_detection
& 0x3) == 0x3)
12065 if (jump_detection
& 0x4)
12066 the_info
->insn_type
= dis_condbranch
;
12068 the_info
->insn_type
=
12069 (dp
->name
&& !strncmp(dp
->name
, "call", 4))
12070 ? dis_jsr
: dis_branch
;
12074 /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
12075 are all 0s in inverted form. */
12076 if (need_vex
&& vex
.register_specifier
!= 0)
12078 (*info
->fprintf_func
) (info
->stream
, "(bad)");
12079 return end_codep
- priv
.the_buffer
;
12082 /* Check if the REX prefix is used. */
12083 if ((rex
^ rex_used
) == 0 && !need_vex
&& last_rex_prefix
>= 0)
12084 all_prefixes
[last_rex_prefix
] = 0;
12086 /* Check if the SEG prefix is used. */
12087 if ((prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
| PREFIX_ES
12088 | PREFIX_FS
| PREFIX_GS
)) != 0
12089 && (used_prefixes
& active_seg_prefix
) != 0)
12090 all_prefixes
[last_seg_prefix
] = 0;
12092 /* Check if the ADDR prefix is used. */
12093 if ((prefixes
& PREFIX_ADDR
) != 0
12094 && (used_prefixes
& PREFIX_ADDR
) != 0)
12095 all_prefixes
[last_addr_prefix
] = 0;
12097 /* Check if the DATA prefix is used. */
12098 if ((prefixes
& PREFIX_DATA
) != 0
12099 && (used_prefixes
& PREFIX_DATA
) != 0
12101 all_prefixes
[last_data_prefix
] = 0;
12103 /* Print the extra prefixes. */
12105 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
12106 if (all_prefixes
[i
])
12109 name
= prefix_name (all_prefixes
[i
], orig_sizeflag
);
12112 prefix_length
+= strlen (name
) + 1;
12113 (*info
->fprintf_func
) (info
->stream
, "%s ", name
);
12116 /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
12117 unused, opcode is invalid. Since the PREFIX_DATA prefix may be
12118 used by putop and MMX/SSE operand and may be overriden by the
12119 PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
12121 if (dp
->prefix_requirement
== PREFIX_OPCODE
12123 ? vex
.prefix
== REPE_PREFIX_OPCODE
12124 || vex
.prefix
== REPNE_PREFIX_OPCODE
12126 & (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0)
12128 & (PREFIX_REPZ
| PREFIX_REPNZ
)) == 0)
12130 ? vex
.prefix
== DATA_PREFIX_OPCODE
12132 & (PREFIX_REPZ
| PREFIX_REPNZ
| PREFIX_DATA
))
12134 && (used_prefixes
& PREFIX_DATA
) == 0))
12135 || (vex
.evex
&& !vex
.w
!= !(used_prefixes
& PREFIX_DATA
))))
12137 (*info
->fprintf_func
) (info
->stream
, "(bad)");
12138 return end_codep
- priv
.the_buffer
;
12141 /* Check maximum code length. */
12142 if ((codep
- start_codep
) > MAX_CODE_LENGTH
)
12144 (*info
->fprintf_func
) (info
->stream
, "(bad)");
12145 return MAX_CODE_LENGTH
;
12148 obufp
= mnemonicendp
;
12149 for (i
= strlen (obuf
) + prefix_length
; i
< 6; i
++)
12152 (*info
->fprintf_func
) (info
->stream
, "%s", obuf
);
12154 /* The enter and bound instructions are printed with operands in the same
12155 order as the intel book; everything else is printed in reverse order. */
12156 if (intel_syntax
|| two_source_ops
)
12160 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12161 op_txt
[i
] = op_out
[i
];
12163 if (intel_syntax
&& dp
&& dp
->op
[2].rtn
== OP_Rounding
12164 && dp
->op
[3].rtn
== OP_E
&& dp
->op
[4].rtn
== NULL
)
12166 op_txt
[2] = op_out
[3];
12167 op_txt
[3] = op_out
[2];
12170 for (i
= 0; i
< (MAX_OPERANDS
>> 1); ++i
)
12172 op_ad
= op_index
[i
];
12173 op_index
[i
] = op_index
[MAX_OPERANDS
- 1 - i
];
12174 op_index
[MAX_OPERANDS
- 1 - i
] = op_ad
;
12175 riprel
= op_riprel
[i
];
12176 op_riprel
[i
] = op_riprel
[MAX_OPERANDS
- 1 - i
];
12177 op_riprel
[MAX_OPERANDS
- 1 - i
] = riprel
;
12182 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12183 op_txt
[MAX_OPERANDS
- 1 - i
] = op_out
[i
];
12187 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12191 (*info
->fprintf_func
) (info
->stream
, ",");
12192 if (op_index
[i
] != -1 && !op_riprel
[i
])
12194 bfd_vma target
= (bfd_vma
) op_address
[op_index
[i
]];
12196 if (the_info
&& op_is_jump
)
12198 the_info
->insn_info_valid
= 1;
12199 the_info
->branch_delay_insns
= 0;
12200 the_info
->data_size
= 0;
12201 the_info
->target
= target
;
12202 the_info
->target2
= 0;
12204 (*info
->print_address_func
) (target
, info
);
12207 (*info
->fprintf_func
) (info
->stream
, "%s", op_txt
[i
]);
12211 for (i
= 0; i
< MAX_OPERANDS
; i
++)
12212 if (op_index
[i
] != -1 && op_riprel
[i
])
12214 (*info
->fprintf_func
) (info
->stream
, " # ");
12215 (*info
->print_address_func
) ((bfd_vma
) (start_pc
+ (codep
- start_codep
)
12216 + op_address
[op_index
[i
]]), info
);
12219 return codep
- priv
.the_buffer
;
12222 static const char *float_mem
[] = {
12297 static const unsigned char float_mem_mode
[] = {
12372 #define ST { OP_ST, 0 }
12373 #define STi { OP_STi, 0 }
12375 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
12376 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
12377 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
12378 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
12379 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
12380 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
12381 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
12382 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
12383 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
12385 static const struct dis386 float_reg
[][8] = {
12388 { "fadd", { ST
, STi
}, 0 },
12389 { "fmul", { ST
, STi
}, 0 },
12390 { "fcom", { STi
}, 0 },
12391 { "fcomp", { STi
}, 0 },
12392 { "fsub", { ST
, STi
}, 0 },
12393 { "fsubr", { ST
, STi
}, 0 },
12394 { "fdiv", { ST
, STi
}, 0 },
12395 { "fdivr", { ST
, STi
}, 0 },
12399 { "fld", { STi
}, 0 },
12400 { "fxch", { STi
}, 0 },
12410 { "fcmovb", { ST
, STi
}, 0 },
12411 { "fcmove", { ST
, STi
}, 0 },
12412 { "fcmovbe",{ ST
, STi
}, 0 },
12413 { "fcmovu", { ST
, STi
}, 0 },
12421 { "fcmovnb",{ ST
, STi
}, 0 },
12422 { "fcmovne",{ ST
, STi
}, 0 },
12423 { "fcmovnbe",{ ST
, STi
}, 0 },
12424 { "fcmovnu",{ ST
, STi
}, 0 },
12426 { "fucomi", { ST
, STi
}, 0 },
12427 { "fcomi", { ST
, STi
}, 0 },
12432 { "fadd", { STi
, ST
}, 0 },
12433 { "fmul", { STi
, ST
}, 0 },
12436 { "fsub{!M|r}", { STi
, ST
}, 0 },
12437 { "fsub{M|}", { STi
, ST
}, 0 },
12438 { "fdiv{!M|r}", { STi
, ST
}, 0 },
12439 { "fdiv{M|}", { STi
, ST
}, 0 },
12443 { "ffree", { STi
}, 0 },
12445 { "fst", { STi
}, 0 },
12446 { "fstp", { STi
}, 0 },
12447 { "fucom", { STi
}, 0 },
12448 { "fucomp", { STi
}, 0 },
12454 { "faddp", { STi
, ST
}, 0 },
12455 { "fmulp", { STi
, ST
}, 0 },
12458 { "fsub{!M|r}p", { STi
, ST
}, 0 },
12459 { "fsub{M|}p", { STi
, ST
}, 0 },
12460 { "fdiv{!M|r}p", { STi
, ST
}, 0 },
12461 { "fdiv{M|}p", { STi
, ST
}, 0 },
12465 { "ffreep", { STi
}, 0 },
12470 { "fucomip", { ST
, STi
}, 0 },
12471 { "fcomip", { ST
, STi
}, 0 },
12476 static char *fgrps
[][8] = {
12479 "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12484 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12489 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
12494 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
12499 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
12504 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
12509 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12514 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
12515 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
12520 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12525 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12530 swap_operand (void)
12532 mnemonicendp
[0] = '.';
12533 mnemonicendp
[1] = 's';
12538 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED
,
12539 int sizeflag ATTRIBUTE_UNUSED
)
12541 /* Skip mod/rm byte. */
12547 dofloat (int sizeflag
)
12549 const struct dis386
*dp
;
12550 unsigned char floatop
;
12552 floatop
= codep
[-1];
12554 if (modrm
.mod
!= 3)
12556 int fp_indx
= (floatop
- 0xd8) * 8 + modrm
.reg
;
12558 putop (float_mem
[fp_indx
], sizeflag
);
12561 OP_E (float_mem_mode
[fp_indx
], sizeflag
);
12564 /* Skip mod/rm byte. */
12568 dp
= &float_reg
[floatop
- 0xd8][modrm
.reg
];
12569 if (dp
->name
== NULL
)
12571 putop (fgrps
[dp
->op
[0].bytemode
][modrm
.rm
], sizeflag
);
12573 /* Instruction fnstsw is only one with strange arg. */
12574 if (floatop
== 0xdf && codep
[-1] == 0xe0)
12575 strcpy (op_out
[0], names16
[0]);
12579 putop (dp
->name
, sizeflag
);
12584 (*dp
->op
[0].rtn
) (dp
->op
[0].bytemode
, sizeflag
);
12589 (*dp
->op
[1].rtn
) (dp
->op
[1].bytemode
, sizeflag
);
12593 /* Like oappend (below), but S is a string starting with '%'.
12594 In Intel syntax, the '%' is elided. */
12596 oappend_maybe_intel (const char *s
)
12598 oappend (s
+ intel_syntax
);
12602 OP_ST (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
12604 oappend_maybe_intel ("%st");
12608 OP_STi (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
12610 sprintf (scratchbuf
, "%%st(%d)", modrm
.rm
);
12611 oappend_maybe_intel (scratchbuf
);
12614 /* Capital letters in template are macros. */
12616 putop (const char *in_template
, int sizeflag
)
12621 unsigned int l
= 0, len
= 1;
12624 #define SAVE_LAST(c) \
12625 if (l < len && l < sizeof (last)) \
12630 for (p
= in_template
; *p
; p
++)
12646 while (*++p
!= '|')
12647 if (*p
== '}' || *p
== '\0')
12653 while (*++p
!= '}')
12665 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
12669 if (l
== 0 && len
== 1)
12674 if (sizeflag
& SUFFIX_ALWAYS
)
12687 if (address_mode
== mode_64bit
12688 && !(prefixes
& PREFIX_ADDR
))
12699 if (intel_syntax
&& !alt
)
12701 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
12703 if (sizeflag
& DFLAG
)
12704 *obufp
++ = intel_syntax
? 'd' : 'l';
12706 *obufp
++ = intel_syntax
? 'w' : 's';
12707 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12711 if (intel_syntax
|| !(sizeflag
& SUFFIX_ALWAYS
))
12714 if (modrm
.mod
== 3)
12720 if (sizeflag
& DFLAG
)
12721 *obufp
++ = intel_syntax
? 'd' : 'l';
12724 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12730 case 'E': /* For jcxz/jecxz */
12731 if (address_mode
== mode_64bit
)
12733 if (sizeflag
& AFLAG
)
12739 if (sizeflag
& AFLAG
)
12741 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
12746 if ((prefixes
& PREFIX_ADDR
) || (sizeflag
& SUFFIX_ALWAYS
))
12748 if (sizeflag
& AFLAG
)
12749 *obufp
++ = address_mode
== mode_64bit
? 'q' : 'l';
12751 *obufp
++ = address_mode
== mode_64bit
? 'l' : 'w';
12752 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
12756 if (intel_syntax
|| (obufp
[-1] != 's' && !(sizeflag
& SUFFIX_ALWAYS
)))
12758 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
12762 if (!(rex
& REX_W
))
12763 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12768 if ((prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_CS
12769 || (prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_DS
)
12771 used_prefixes
|= prefixes
& (PREFIX_CS
| PREFIX_DS
);
12774 if (prefixes
& PREFIX_DS
)
12788 if (l
!= 0 || len
!= 1)
12790 if (l
!= 1 || len
!= 2 || last
[0] != 'X')
12795 if (!need_vex
|| !vex
.evex
)
12798 || ((modrm
.mod
== 3 || vex
.b
) && !(sizeflag
& SUFFIX_ALWAYS
)))
12800 switch (vex
.length
)
12818 if (address_mode
== mode_64bit
&& (sizeflag
& SUFFIX_ALWAYS
))
12823 /* Fall through. */
12826 if (l
!= 0 || len
!= 1)
12834 if (sizeflag
& SUFFIX_ALWAYS
)
12838 if (intel_mnemonic
!= cond
)
12842 if ((prefixes
& PREFIX_FWAIT
) == 0)
12845 used_prefixes
|= PREFIX_FWAIT
;
12851 else if (intel_syntax
&& (sizeflag
& DFLAG
))
12855 if (!(rex
& REX_W
))
12856 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12860 && address_mode
== mode_64bit
12861 && isa64
== intel64
)
12866 /* Fall through. */
12869 && address_mode
== mode_64bit
12870 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
12875 /* Fall through. */
12878 if (l
== 0 && len
== 1)
12883 if ((rex
& REX_W
) == 0
12884 && (prefixes
& PREFIX_DATA
))
12886 if ((sizeflag
& DFLAG
) == 0)
12888 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12892 if ((prefixes
& PREFIX_DATA
)
12894 || (sizeflag
& SUFFIX_ALWAYS
))
12901 if (sizeflag
& DFLAG
)
12905 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12911 if (l
!= 1 || len
!= 2 || last
[0] != 'L')
12917 if ((prefixes
& PREFIX_DATA
)
12919 || (sizeflag
& SUFFIX_ALWAYS
))
12926 if (sizeflag
& DFLAG
)
12927 *obufp
++ = intel_syntax
? 'd' : 'l';
12930 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12938 if (address_mode
== mode_64bit
12939 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
12941 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
12945 /* Fall through. */
12948 if (l
== 0 && len
== 1)
12951 if (intel_syntax
&& !alt
)
12954 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
12960 if (sizeflag
& DFLAG
)
12961 *obufp
++ = intel_syntax
? 'd' : 'l';
12964 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12970 if (l
!= 1 || len
!= 2 || last
[0] != 'L')
12975 if ((intel_syntax
&& need_modrm
)
12976 || (modrm
.mod
== 3 && !(sizeflag
& SUFFIX_ALWAYS
)))
12983 else if((address_mode
== mode_64bit
&& need_modrm
)
12984 || (sizeflag
& SUFFIX_ALWAYS
))
12985 *obufp
++ = intel_syntax
? 'd' : 'l';
12992 else if (sizeflag
& DFLAG
)
13001 if (intel_syntax
&& !p
[1]
13002 && ((rex
& REX_W
) || (sizeflag
& DFLAG
)))
13004 if (!(rex
& REX_W
))
13005 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13008 if (l
== 0 && len
== 1)
13012 if (address_mode
== mode_64bit
13013 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13015 if (sizeflag
& SUFFIX_ALWAYS
)
13037 /* Fall through. */
13040 if (l
== 0 && len
== 1)
13045 if (sizeflag
& SUFFIX_ALWAYS
)
13051 if (sizeflag
& DFLAG
)
13055 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13069 if (address_mode
== mode_64bit
13070 && !(prefixes
& PREFIX_ADDR
))
13081 if (l
!= 0 || len
!= 1)
13087 ? vex
.prefix
== DATA_PREFIX_OPCODE
13088 : prefixes
& PREFIX_DATA
)
13091 used_prefixes
|= PREFIX_DATA
;
13097 if (l
== 0 && len
== 1)
13101 if (l
!= 1 || len
!= 2 || last
[0] != 'X')
13109 || ((modrm
.mod
== 3 || vex
.b
) && !(sizeflag
& SUFFIX_ALWAYS
)))
13111 switch (vex
.length
)
13127 if (l
== 0 && len
== 1)
13129 /* operand size flag for cwtl, cbtw */
13138 else if (sizeflag
& DFLAG
)
13142 if (!(rex
& REX_W
))
13143 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13150 && last
[0] != 'L'))
13157 if (last
[0] == 'X')
13158 *obufp
++ = vex
.w
? 'd': 's';
13160 *obufp
++ = vex
.w
? 'q': 'd';
13166 if (isa64
== intel64
&& (rex
& REX_W
))
13172 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
13174 if (sizeflag
& DFLAG
)
13178 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13184 if (address_mode
== mode_64bit
13185 && (isa64
== intel64
13186 || ((sizeflag
& DFLAG
) || (rex
& REX_W
))))
13188 else if ((prefixes
& PREFIX_DATA
))
13190 if (!(sizeflag
& DFLAG
))
13192 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13198 mnemonicendp
= obufp
;
13203 oappend (const char *s
)
13205 obufp
= stpcpy (obufp
, s
);
13211 /* Only print the active segment register. */
13212 if (!active_seg_prefix
)
13215 used_prefixes
|= active_seg_prefix
;
13216 switch (active_seg_prefix
)
13219 oappend_maybe_intel ("%cs:");
13222 oappend_maybe_intel ("%ds:");
13225 oappend_maybe_intel ("%ss:");
13228 oappend_maybe_intel ("%es:");
13231 oappend_maybe_intel ("%fs:");
13234 oappend_maybe_intel ("%gs:");
13242 OP_indirE (int bytemode
, int sizeflag
)
13246 OP_E (bytemode
, sizeflag
);
13250 print_operand_value (char *buf
, int hex
, bfd_vma disp
)
13252 if (address_mode
== mode_64bit
)
13260 sprintf_vma (tmp
, disp
);
13261 for (i
= 0; tmp
[i
] == '0' && tmp
[i
+ 1]; i
++);
13262 strcpy (buf
+ 2, tmp
+ i
);
13266 bfd_signed_vma v
= disp
;
13273 /* Check for possible overflow on 0x8000000000000000. */
13276 strcpy (buf
, "9223372036854775808");
13290 tmp
[28 - i
] = (v
% 10) + '0';
13294 strcpy (buf
, tmp
+ 29 - i
);
13300 sprintf (buf
, "0x%x", (unsigned int) disp
);
13302 sprintf (buf
, "%d", (int) disp
);
13306 /* Put DISP in BUF as signed hex number. */
13309 print_displacement (char *buf
, bfd_vma disp
)
13311 bfd_signed_vma val
= disp
;
13320 /* Check for possible overflow. */
13323 switch (address_mode
)
13326 strcpy (buf
+ j
, "0x8000000000000000");
13329 strcpy (buf
+ j
, "0x80000000");
13332 strcpy (buf
+ j
, "0x8000");
13342 sprintf_vma (tmp
, (bfd_vma
) val
);
13343 for (i
= 0; tmp
[i
] == '0'; i
++)
13345 if (tmp
[i
] == '\0')
13347 strcpy (buf
+ j
, tmp
+ i
);
13351 intel_operand_size (int bytemode
, int sizeflag
)
13355 && (bytemode
== x_mode
13356 || bytemode
== evex_half_bcst_xmmq_mode
))
13359 oappend ("QWORD PTR ");
13361 oappend ("DWORD PTR ");
13370 oappend ("BYTE PTR ");
13375 oappend ("WORD PTR ");
13378 if (address_mode
== mode_64bit
&& isa64
== intel64
)
13380 oappend ("QWORD PTR ");
13383 /* Fall through. */
13385 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13387 oappend ("QWORD PTR ");
13390 /* Fall through. */
13396 oappend ("QWORD PTR ");
13399 if ((sizeflag
& DFLAG
) || bytemode
== dq_mode
)
13400 oappend ("DWORD PTR ");
13402 oappend ("WORD PTR ");
13403 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13407 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
13409 oappend ("WORD PTR ");
13410 if (!(rex
& REX_W
))
13411 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13414 if (sizeflag
& DFLAG
)
13415 oappend ("QWORD PTR ");
13417 oappend ("DWORD PTR ");
13418 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13421 if (!(sizeflag
& DFLAG
) && isa64
== intel64
)
13422 oappend ("WORD PTR ");
13424 oappend ("DWORD PTR ");
13425 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13428 case d_scalar_swap_mode
:
13431 oappend ("DWORD PTR ");
13434 case q_scalar_swap_mode
:
13436 oappend ("QWORD PTR ");
13439 if (address_mode
== mode_64bit
)
13440 oappend ("QWORD PTR ");
13442 oappend ("DWORD PTR ");
13445 if (sizeflag
& DFLAG
)
13446 oappend ("FWORD PTR ");
13448 oappend ("DWORD PTR ");
13449 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13452 oappend ("TBYTE PTR ");
13456 case evex_x_gscat_mode
:
13457 case evex_x_nobcst_mode
:
13458 case b_scalar_mode
:
13459 case w_scalar_mode
:
13462 switch (vex
.length
)
13465 oappend ("XMMWORD PTR ");
13468 oappend ("YMMWORD PTR ");
13471 oappend ("ZMMWORD PTR ");
13478 oappend ("XMMWORD PTR ");
13481 oappend ("XMMWORD PTR ");
13484 oappend ("YMMWORD PTR ");
13487 case evex_half_bcst_xmmq_mode
:
13491 switch (vex
.length
)
13494 oappend ("QWORD PTR ");
13497 oappend ("XMMWORD PTR ");
13500 oappend ("YMMWORD PTR ");
13510 switch (vex
.length
)
13515 oappend ("BYTE PTR ");
13525 switch (vex
.length
)
13530 oappend ("WORD PTR ");
13540 switch (vex
.length
)
13545 oappend ("DWORD PTR ");
13555 switch (vex
.length
)
13560 oappend ("QWORD PTR ");
13570 switch (vex
.length
)
13573 oappend ("WORD PTR ");
13576 oappend ("DWORD PTR ");
13579 oappend ("QWORD PTR ");
13589 switch (vex
.length
)
13592 oappend ("DWORD PTR ");
13595 oappend ("QWORD PTR ");
13598 oappend ("XMMWORD PTR ");
13608 switch (vex
.length
)
13611 oappend ("QWORD PTR ");
13614 oappend ("YMMWORD PTR ");
13617 oappend ("ZMMWORD PTR ");
13627 switch (vex
.length
)
13631 oappend ("XMMWORD PTR ");
13638 oappend ("OWORD PTR ");
13640 case vex_scalar_w_dq_mode
:
13645 oappend ("QWORD PTR ");
13647 oappend ("DWORD PTR ");
13649 case vex_vsib_d_w_dq_mode
:
13650 case vex_vsib_q_w_dq_mode
:
13657 oappend ("QWORD PTR ");
13659 oappend ("DWORD PTR ");
13663 switch (vex
.length
)
13666 oappend ("XMMWORD PTR ");
13669 oappend ("YMMWORD PTR ");
13672 oappend ("ZMMWORD PTR ");
13679 case vex_vsib_q_w_d_mode
:
13680 case vex_vsib_d_w_d_mode
:
13681 if (!need_vex
|| !vex
.evex
)
13684 switch (vex
.length
)
13687 oappend ("QWORD PTR ");
13690 oappend ("XMMWORD PTR ");
13693 oappend ("YMMWORD PTR ");
13701 if (!need_vex
|| vex
.length
!= 128)
13704 oappend ("DWORD PTR ");
13706 oappend ("BYTE PTR ");
13712 oappend ("QWORD PTR ");
13714 oappend ("WORD PTR ");
13724 OP_E_register (int bytemode
, int sizeflag
)
13726 int reg
= modrm
.rm
;
13727 const char **names
;
13733 if ((sizeflag
& SUFFIX_ALWAYS
)
13734 && (bytemode
== b_swap_mode
13735 || bytemode
== bnd_swap_mode
13736 || bytemode
== v_swap_mode
))
13762 names
= address_mode
== mode_64bit
? names64
: names32
;
13765 case bnd_swap_mode
:
13774 if (address_mode
== mode_64bit
&& isa64
== intel64
)
13779 /* Fall through. */
13781 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13787 /* Fall through. */
13799 if ((sizeflag
& DFLAG
)
13800 || (bytemode
!= v_mode
13801 && bytemode
!= v_swap_mode
))
13805 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13809 if (!(sizeflag
& DFLAG
) && isa64
== intel64
)
13813 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13816 names
= (address_mode
== mode_64bit
13817 ? names64
: names32
);
13818 if (!(prefixes
& PREFIX_ADDR
))
13819 names
= (address_mode
== mode_16bit
13820 ? names16
: names
);
13823 /* Remove "addr16/addr32". */
13824 all_prefixes
[last_addr_prefix
] = 0;
13825 names
= (address_mode
!= mode_32bit
13826 ? names32
: names16
);
13827 used_prefixes
|= PREFIX_ADDR
;
13837 names
= names_mask
;
13842 oappend (INTERNAL_DISASSEMBLER_ERROR
);
13845 oappend (names
[reg
]);
13849 OP_E_memory (int bytemode
, int sizeflag
)
13852 int add
= (rex
& REX_B
) ? 8 : 0;
13858 /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */
13860 && bytemode
!= x_mode
13861 && bytemode
!= xmmq_mode
13862 && bytemode
!= evex_half_bcst_xmmq_mode
)
13878 if (address_mode
!= mode_64bit
)
13884 case vex_scalar_w_dq_mode
:
13885 case vex_vsib_d_w_dq_mode
:
13886 case vex_vsib_d_w_d_mode
:
13887 case vex_vsib_q_w_dq_mode
:
13888 case vex_vsib_q_w_d_mode
:
13889 case evex_x_gscat_mode
:
13890 shift
= vex
.w
? 3 : 2;
13893 case evex_half_bcst_xmmq_mode
:
13897 shift
= vex
.w
? 3 : 2;
13900 /* Fall through. */
13904 case evex_x_nobcst_mode
:
13906 switch (vex
.length
)
13930 case q_scalar_swap_mode
:
13937 case d_scalar_swap_mode
:
13940 case w_scalar_mode
:
13944 case b_scalar_mode
:
13951 /* Make necessary corrections to shift for modes that need it.
13952 For these modes we currently have shift 4, 5 or 6 depending on
13953 vex.length (it corresponds to xmmword, ymmword or zmmword
13954 operand). We might want to make it 3, 4 or 5 (e.g. for
13955 xmmq_mode). In case of broadcast enabled the corrections
13956 aren't needed, as element size is always 32 or 64 bits. */
13958 && (bytemode
== xmmq_mode
13959 || bytemode
== evex_half_bcst_xmmq_mode
))
13961 else if (bytemode
== xmmqd_mode
)
13963 else if (bytemode
== xmmdw_mode
)
13965 else if (bytemode
== ymmq_mode
&& vex
.length
== 128)
13973 intel_operand_size (bytemode
, sizeflag
);
13976 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
13978 /* 32/64 bit address mode */
13988 int addr32flag
= !((sizeflag
& AFLAG
)
13989 || bytemode
== v_bnd_mode
13990 || bytemode
== v_bndmk_mode
13991 || bytemode
== bnd_mode
13992 || bytemode
== bnd_swap_mode
);
13993 const char **indexes64
= names64
;
13994 const char **indexes32
= names32
;
14004 vindex
= sib
.index
;
14010 case vex_vsib_d_w_dq_mode
:
14011 case vex_vsib_d_w_d_mode
:
14012 case vex_vsib_q_w_dq_mode
:
14013 case vex_vsib_q_w_d_mode
:
14023 switch (vex
.length
)
14026 indexes64
= indexes32
= names_xmm
;
14030 || bytemode
== vex_vsib_q_w_dq_mode
14031 || bytemode
== vex_vsib_q_w_d_mode
)
14032 indexes64
= indexes32
= names_ymm
;
14034 indexes64
= indexes32
= names_xmm
;
14038 || bytemode
== vex_vsib_q_w_dq_mode
14039 || bytemode
== vex_vsib_q_w_d_mode
)
14040 indexes64
= indexes32
= names_zmm
;
14042 indexes64
= indexes32
= names_ymm
;
14049 haveindex
= vindex
!= 4;
14056 rbase
= base
+ add
;
14064 if (address_mode
== mode_64bit
&& !havesib
)
14067 if (riprel
&& bytemode
== v_bndmk_mode
)
14075 FETCH_DATA (the_info
, codep
+ 1);
14077 if ((disp
& 0x80) != 0)
14079 if (vex
.evex
&& shift
> 0)
14092 && address_mode
!= mode_16bit
)
14094 if (address_mode
== mode_64bit
)
14096 /* Display eiz instead of addr32. */
14097 needindex
= addr32flag
;
14102 /* In 32-bit mode, we need index register to tell [offset]
14103 from [eiz*1 + offset]. */
14108 havedisp
= (havebase
14110 || (havesib
&& (haveindex
|| scale
!= 0)));
14113 if (modrm
.mod
!= 0 || base
== 5)
14115 if (havedisp
|| riprel
)
14116 print_displacement (scratchbuf
, disp
);
14118 print_operand_value (scratchbuf
, 1, disp
);
14119 oappend (scratchbuf
);
14123 oappend (!addr32flag
? "(%rip)" : "(%eip)");
14127 if ((havebase
|| haveindex
|| needindex
|| needaddr32
|| riprel
)
14128 && (address_mode
!= mode_64bit
14129 || ((bytemode
!= v_bnd_mode
)
14130 && (bytemode
!= v_bndmk_mode
)
14131 && (bytemode
!= bnd_mode
)
14132 && (bytemode
!= bnd_swap_mode
))))
14133 used_prefixes
|= PREFIX_ADDR
;
14135 if (havedisp
|| (intel_syntax
&& riprel
))
14137 *obufp
++ = open_char
;
14138 if (intel_syntax
&& riprel
)
14141 oappend (!addr32flag
? "rip" : "eip");
14145 oappend (address_mode
== mode_64bit
&& !addr32flag
14146 ? names64
[rbase
] : names32
[rbase
]);
14149 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
14150 print index to tell base + index from base. */
14154 || (havebase
&& base
!= ESP_REG_NUM
))
14156 if (!intel_syntax
|| havebase
)
14158 *obufp
++ = separator_char
;
14162 oappend (address_mode
== mode_64bit
&& !addr32flag
14163 ? indexes64
[vindex
] : indexes32
[vindex
]);
14165 oappend (address_mode
== mode_64bit
&& !addr32flag
14166 ? index64
: index32
);
14168 *obufp
++ = scale_char
;
14170 sprintf (scratchbuf
, "%d", 1 << scale
);
14171 oappend (scratchbuf
);
14175 && (disp
|| modrm
.mod
!= 0 || base
== 5))
14177 if (!havedisp
|| (bfd_signed_vma
) disp
>= 0)
14182 else if (modrm
.mod
!= 1 && disp
!= -disp
)
14186 disp
= - (bfd_signed_vma
) disp
;
14190 print_displacement (scratchbuf
, disp
);
14192 print_operand_value (scratchbuf
, 1, disp
);
14193 oappend (scratchbuf
);
14196 *obufp
++ = close_char
;
14199 else if (intel_syntax
)
14201 if (modrm
.mod
!= 0 || base
== 5)
14203 if (!active_seg_prefix
)
14205 oappend (names_seg
[ds_reg
- es_reg
]);
14208 print_operand_value (scratchbuf
, 1, disp
);
14209 oappend (scratchbuf
);
14213 else if (bytemode
== v_bnd_mode
14214 || bytemode
== v_bndmk_mode
14215 || bytemode
== bnd_mode
14216 || bytemode
== bnd_swap_mode
)
14223 /* 16 bit address mode */
14224 used_prefixes
|= prefixes
& PREFIX_ADDR
;
14231 if ((disp
& 0x8000) != 0)
14236 FETCH_DATA (the_info
, codep
+ 1);
14238 if ((disp
& 0x80) != 0)
14240 if (vex
.evex
&& shift
> 0)
14245 if ((disp
& 0x8000) != 0)
14251 if (modrm
.mod
!= 0 || modrm
.rm
== 6)
14253 print_displacement (scratchbuf
, disp
);
14254 oappend (scratchbuf
);
14257 if (modrm
.mod
!= 0 || modrm
.rm
!= 6)
14259 *obufp
++ = open_char
;
14261 oappend (index16
[modrm
.rm
]);
14263 && (disp
|| modrm
.mod
!= 0 || modrm
.rm
== 6))
14265 if ((bfd_signed_vma
) disp
>= 0)
14270 else if (modrm
.mod
!= 1)
14274 disp
= - (bfd_signed_vma
) disp
;
14277 print_displacement (scratchbuf
, disp
);
14278 oappend (scratchbuf
);
14281 *obufp
++ = close_char
;
14284 else if (intel_syntax
)
14286 if (!active_seg_prefix
)
14288 oappend (names_seg
[ds_reg
- es_reg
]);
14291 print_operand_value (scratchbuf
, 1, disp
& 0xffff);
14292 oappend (scratchbuf
);
14295 if (vex
.evex
&& vex
.b
14296 && (bytemode
== x_mode
14297 || bytemode
== xmmq_mode
14298 || bytemode
== evex_half_bcst_xmmq_mode
))
14301 || bytemode
== xmmq_mode
14302 || bytemode
== evex_half_bcst_xmmq_mode
)
14304 switch (vex
.length
)
14307 oappend ("{1to2}");
14310 oappend ("{1to4}");
14313 oappend ("{1to8}");
14321 switch (vex
.length
)
14324 oappend ("{1to4}");
14327 oappend ("{1to8}");
14330 oappend ("{1to16}");
14340 OP_E (int bytemode
, int sizeflag
)
14342 /* Skip mod/rm byte. */
14346 if (modrm
.mod
== 3)
14347 OP_E_register (bytemode
, sizeflag
);
14349 OP_E_memory (bytemode
, sizeflag
);
14353 OP_G (int bytemode
, int sizeflag
)
14356 const char **names
;
14365 oappend (names8rex
[modrm
.reg
+ add
]);
14367 oappend (names8
[modrm
.reg
+ add
]);
14370 oappend (names16
[modrm
.reg
+ add
]);
14375 oappend (names32
[modrm
.reg
+ add
]);
14378 oappend (names64
[modrm
.reg
+ add
]);
14381 if (modrm
.reg
> 0x3)
14386 oappend (names_bnd
[modrm
.reg
]);
14396 oappend (names64
[modrm
.reg
+ add
]);
14399 if ((sizeflag
& DFLAG
)
14400 || (bytemode
!= v_mode
&& bytemode
!= movsxd_mode
))
14401 oappend (names32
[modrm
.reg
+ add
]);
14403 oappend (names16
[modrm
.reg
+ add
]);
14404 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14408 names
= (address_mode
== mode_64bit
14409 ? names64
: names32
);
14410 if (!(prefixes
& PREFIX_ADDR
))
14412 if (address_mode
== mode_16bit
)
14417 /* Remove "addr16/addr32". */
14418 all_prefixes
[last_addr_prefix
] = 0;
14419 names
= (address_mode
!= mode_32bit
14420 ? names32
: names16
);
14421 used_prefixes
|= PREFIX_ADDR
;
14423 oappend (names
[modrm
.reg
+ add
]);
14426 if (address_mode
== mode_64bit
)
14427 oappend (names64
[modrm
.reg
+ add
]);
14429 oappend (names32
[modrm
.reg
+ add
]);
14433 if ((modrm
.reg
+ add
) > 0x7)
14438 oappend (names_mask
[modrm
.reg
+ add
]);
14441 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14454 FETCH_DATA (the_info
, codep
+ 8);
14455 a
= *codep
++ & 0xff;
14456 a
|= (*codep
++ & 0xff) << 8;
14457 a
|= (*codep
++ & 0xff) << 16;
14458 a
|= (*codep
++ & 0xffu
) << 24;
14459 b
= *codep
++ & 0xff;
14460 b
|= (*codep
++ & 0xff) << 8;
14461 b
|= (*codep
++ & 0xff) << 16;
14462 b
|= (*codep
++ & 0xffu
) << 24;
14463 x
= a
+ ((bfd_vma
) b
<< 32);
14471 static bfd_signed_vma
14474 bfd_signed_vma x
= 0;
14476 FETCH_DATA (the_info
, codep
+ 4);
14477 x
= *codep
++ & (bfd_signed_vma
) 0xff;
14478 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
14479 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
14480 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
14484 static bfd_signed_vma
14487 bfd_signed_vma x
= 0;
14489 FETCH_DATA (the_info
, codep
+ 4);
14490 x
= *codep
++ & (bfd_signed_vma
) 0xff;
14491 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
14492 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
14493 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
14495 x
= (x
^ ((bfd_signed_vma
) 1 << 31)) - ((bfd_signed_vma
) 1 << 31);
14505 FETCH_DATA (the_info
, codep
+ 2);
14506 x
= *codep
++ & 0xff;
14507 x
|= (*codep
++ & 0xff) << 8;
14512 set_op (bfd_vma op
, int riprel
)
14514 op_index
[op_ad
] = op_ad
;
14515 if (address_mode
== mode_64bit
)
14517 op_address
[op_ad
] = op
;
14518 op_riprel
[op_ad
] = riprel
;
14522 /* Mask to get a 32-bit address. */
14523 op_address
[op_ad
] = op
& 0xffffffff;
14524 op_riprel
[op_ad
] = riprel
& 0xffffffff;
14529 OP_REG (int code
, int sizeflag
)
14536 case es_reg
: case ss_reg
: case cs_reg
:
14537 case ds_reg
: case fs_reg
: case gs_reg
:
14538 oappend (names_seg
[code
- es_reg
]);
14550 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
14551 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
14552 s
= names16
[code
- ax_reg
+ add
];
14554 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
14555 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
14558 s
= names8rex
[code
- al_reg
+ add
];
14560 s
= names8
[code
- al_reg
];
14562 case rAX_reg
: case rCX_reg
: case rDX_reg
: case rBX_reg
:
14563 case rSP_reg
: case rBP_reg
: case rSI_reg
: case rDI_reg
:
14564 if (address_mode
== mode_64bit
14565 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14567 s
= names64
[code
- rAX_reg
+ add
];
14570 code
+= eAX_reg
- rAX_reg
;
14571 /* Fall through. */
14572 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
14573 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
14576 s
= names64
[code
- eAX_reg
+ add
];
14579 if (sizeflag
& DFLAG
)
14580 s
= names32
[code
- eAX_reg
+ add
];
14582 s
= names16
[code
- eAX_reg
+ add
];
14583 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14587 s
= INTERNAL_DISASSEMBLER_ERROR
;
14594 OP_IMREG (int code
, int sizeflag
)
14606 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
14607 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
14608 s
= names16
[code
- ax_reg
];
14610 case es_reg
: case ss_reg
: case cs_reg
:
14611 case ds_reg
: case fs_reg
: case gs_reg
:
14612 s
= names_seg
[code
- es_reg
];
14614 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
14615 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
14618 s
= names8rex
[code
- al_reg
];
14620 s
= names8
[code
- al_reg
];
14622 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
14623 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
14626 s
= names64
[code
- eAX_reg
];
14629 if (sizeflag
& DFLAG
)
14630 s
= names32
[code
- eAX_reg
];
14632 s
= names16
[code
- eAX_reg
];
14633 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14636 case z_mode_ax_reg
:
14637 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
14641 if (!(rex
& REX_W
))
14642 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14645 s
= INTERNAL_DISASSEMBLER_ERROR
;
14652 OP_I (int bytemode
, int sizeflag
)
14655 bfd_signed_vma mask
= -1;
14660 FETCH_DATA (the_info
, codep
+ 1);
14670 if (sizeflag
& DFLAG
)
14680 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14696 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14701 scratchbuf
[0] = '$';
14702 print_operand_value (scratchbuf
+ 1, 1, op
);
14703 oappend_maybe_intel (scratchbuf
);
14704 scratchbuf
[0] = '\0';
14708 OP_I64 (int bytemode
, int sizeflag
)
14710 if (bytemode
!= v_mode
|| address_mode
!= mode_64bit
|| !(rex
& REX_W
))
14712 OP_I (bytemode
, sizeflag
);
14718 scratchbuf
[0] = '$';
14719 print_operand_value (scratchbuf
+ 1, 1, get64 ());
14720 oappend_maybe_intel (scratchbuf
);
14721 scratchbuf
[0] = '\0';
14725 OP_sI (int bytemode
, int sizeflag
)
14733 FETCH_DATA (the_info
, codep
+ 1);
14735 if ((op
& 0x80) != 0)
14737 if (bytemode
== b_T_mode
)
14739 if (address_mode
!= mode_64bit
14740 || !((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14742 /* The operand-size prefix is overridden by a REX prefix. */
14743 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
14751 if (!(rex
& REX_W
))
14753 if (sizeflag
& DFLAG
)
14761 /* The operand-size prefix is overridden by a REX prefix. */
14762 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
14768 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14772 scratchbuf
[0] = '$';
14773 print_operand_value (scratchbuf
+ 1, 1, op
);
14774 oappend_maybe_intel (scratchbuf
);
14778 OP_J (int bytemode
, int sizeflag
)
14782 bfd_vma segment
= 0;
14787 FETCH_DATA (the_info
, codep
+ 1);
14789 if ((disp
& 0x80) != 0)
14793 if (isa64
!= intel64
)
14796 if ((sizeflag
& DFLAG
)
14797 || (address_mode
== mode_64bit
14798 && ((isa64
== intel64
&& bytemode
!= dqw_mode
)
14799 || (rex
& REX_W
))))
14804 if ((disp
& 0x8000) != 0)
14806 /* In 16bit mode, address is wrapped around at 64k within
14807 the same segment. Otherwise, a data16 prefix on a jump
14808 instruction means that the pc is masked to 16 bits after
14809 the displacement is added! */
14811 if ((prefixes
& PREFIX_DATA
) == 0)
14812 segment
= ((start_pc
+ (codep
- start_codep
))
14813 & ~((bfd_vma
) 0xffff));
14815 if (address_mode
!= mode_64bit
14816 || (isa64
!= intel64
&& !(rex
& REX_W
)))
14817 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14820 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14823 disp
= ((start_pc
+ (codep
- start_codep
) + disp
) & mask
) | segment
;
14825 print_operand_value (scratchbuf
, 1, disp
);
14826 oappend (scratchbuf
);
14830 OP_SEG (int bytemode
, int sizeflag
)
14832 if (bytemode
== w_mode
)
14833 oappend (names_seg
[modrm
.reg
]);
14835 OP_E (modrm
.mod
== 3 ? bytemode
: w_mode
, sizeflag
);
14839 OP_DIR (int dummy ATTRIBUTE_UNUSED
, int sizeflag
)
14843 if (sizeflag
& DFLAG
)
14853 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14855 sprintf (scratchbuf
, "0x%x:0x%x", seg
, offset
);
14857 sprintf (scratchbuf
, "$0x%x,$0x%x", seg
, offset
);
14858 oappend (scratchbuf
);
14862 OP_OFF (int bytemode
, int sizeflag
)
14866 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
14867 intel_operand_size (bytemode
, sizeflag
);
14870 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
14877 if (!active_seg_prefix
)
14879 oappend (names_seg
[ds_reg
- es_reg
]);
14883 print_operand_value (scratchbuf
, 1, off
);
14884 oappend (scratchbuf
);
14888 OP_OFF64 (int bytemode
, int sizeflag
)
14892 if (address_mode
!= mode_64bit
14893 || (prefixes
& PREFIX_ADDR
))
14895 OP_OFF (bytemode
, sizeflag
);
14899 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
14900 intel_operand_size (bytemode
, sizeflag
);
14907 if (!active_seg_prefix
)
14909 oappend (names_seg
[ds_reg
- es_reg
]);
14913 print_operand_value (scratchbuf
, 1, off
);
14914 oappend (scratchbuf
);
14918 ptr_reg (int code
, int sizeflag
)
14922 *obufp
++ = open_char
;
14923 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
14924 if (address_mode
== mode_64bit
)
14926 if (!(sizeflag
& AFLAG
))
14927 s
= names32
[code
- eAX_reg
];
14929 s
= names64
[code
- eAX_reg
];
14931 else if (sizeflag
& AFLAG
)
14932 s
= names32
[code
- eAX_reg
];
14934 s
= names16
[code
- eAX_reg
];
14936 *obufp
++ = close_char
;
14941 OP_ESreg (int code
, int sizeflag
)
14947 case 0x6d: /* insw/insl */
14948 intel_operand_size (z_mode
, sizeflag
);
14950 case 0xa5: /* movsw/movsl/movsq */
14951 case 0xa7: /* cmpsw/cmpsl/cmpsq */
14952 case 0xab: /* stosw/stosl */
14953 case 0xaf: /* scasw/scasl */
14954 intel_operand_size (v_mode
, sizeflag
);
14957 intel_operand_size (b_mode
, sizeflag
);
14960 oappend_maybe_intel ("%es:");
14961 ptr_reg (code
, sizeflag
);
14965 OP_DSreg (int code
, int sizeflag
)
14971 case 0x6f: /* outsw/outsl */
14972 intel_operand_size (z_mode
, sizeflag
);
14974 case 0xa5: /* movsw/movsl/movsq */
14975 case 0xa7: /* cmpsw/cmpsl/cmpsq */
14976 case 0xad: /* lodsw/lodsl/lodsq */
14977 intel_operand_size (v_mode
, sizeflag
);
14980 intel_operand_size (b_mode
, sizeflag
);
14983 /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
14984 default segment register DS is printed. */
14985 if (!active_seg_prefix
)
14986 active_seg_prefix
= PREFIX_DS
;
14988 ptr_reg (code
, sizeflag
);
14992 OP_C (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15000 else if (address_mode
!= mode_64bit
&& (prefixes
& PREFIX_LOCK
))
15002 all_prefixes
[last_lock_prefix
] = 0;
15003 used_prefixes
|= PREFIX_LOCK
;
15008 sprintf (scratchbuf
, "%%cr%d", modrm
.reg
+ add
);
15009 oappend_maybe_intel (scratchbuf
);
15013 OP_D (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15022 sprintf (scratchbuf
, "db%d", modrm
.reg
+ add
);
15024 sprintf (scratchbuf
, "%%db%d", modrm
.reg
+ add
);
15025 oappend (scratchbuf
);
15029 OP_T (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15031 sprintf (scratchbuf
, "%%tr%d", modrm
.reg
);
15032 oappend_maybe_intel (scratchbuf
);
15036 OP_R (int bytemode
, int sizeflag
)
15038 /* Skip mod/rm byte. */
15041 OP_E_register (bytemode
, sizeflag
);
15045 OP_MMX (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15047 int reg
= modrm
.reg
;
15048 const char **names
;
15050 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15051 if (prefixes
& PREFIX_DATA
)
15060 oappend (names
[reg
]);
15064 OP_XMM (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
15066 int reg
= modrm
.reg
;
15067 const char **names
;
15079 && bytemode
!= xmm_mode
15080 && bytemode
!= xmmq_mode
15081 && bytemode
!= evex_half_bcst_xmmq_mode
15082 && bytemode
!= ymm_mode
15083 && bytemode
!= scalar_mode
)
15085 switch (vex
.length
)
15092 || (bytemode
!= vex_vsib_q_w_dq_mode
15093 && bytemode
!= vex_vsib_q_w_d_mode
))
15105 else if (bytemode
== xmmq_mode
15106 || bytemode
== evex_half_bcst_xmmq_mode
)
15108 switch (vex
.length
)
15121 else if (bytemode
== ymm_mode
)
15125 oappend (names
[reg
]);
15129 OP_EM (int bytemode
, int sizeflag
)
15132 const char **names
;
15134 if (modrm
.mod
!= 3)
15137 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
15139 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
15140 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15142 OP_E (bytemode
, sizeflag
);
15146 if ((sizeflag
& SUFFIX_ALWAYS
) && bytemode
== v_swap_mode
)
15149 /* Skip mod/rm byte. */
15152 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15154 if (prefixes
& PREFIX_DATA
)
15163 oappend (names
[reg
]);
15166 /* cvt* are the only instructions in sse2 which have
15167 both SSE and MMX operands and also have 0x66 prefix
15168 in their opcode. 0x66 was originally used to differentiate
15169 between SSE and MMX instruction(operands). So we have to handle the
15170 cvt* separately using OP_EMC and OP_MXC */
15172 OP_EMC (int bytemode
, int sizeflag
)
15174 if (modrm
.mod
!= 3)
15176 if (intel_syntax
&& bytemode
== v_mode
)
15178 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
15179 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15181 OP_E (bytemode
, sizeflag
);
15185 /* Skip mod/rm byte. */
15188 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15189 oappend (names_mm
[modrm
.rm
]);
15193 OP_MXC (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15195 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15196 oappend (names_mm
[modrm
.reg
]);
15200 OP_EX (int bytemode
, int sizeflag
)
15203 const char **names
;
15205 /* Skip mod/rm byte. */
15209 if (modrm
.mod
!= 3)
15211 OP_E_memory (bytemode
, sizeflag
);
15226 if ((sizeflag
& SUFFIX_ALWAYS
)
15227 && (bytemode
== x_swap_mode
15228 || bytemode
== d_swap_mode
15229 || bytemode
== d_scalar_swap_mode
15230 || bytemode
== q_swap_mode
15231 || bytemode
== q_scalar_swap_mode
))
15235 && bytemode
!= xmm_mode
15236 && bytemode
!= xmmdw_mode
15237 && bytemode
!= xmmqd_mode
15238 && bytemode
!= xmm_mb_mode
15239 && bytemode
!= xmm_mw_mode
15240 && bytemode
!= xmm_md_mode
15241 && bytemode
!= xmm_mq_mode
15242 && bytemode
!= xmmq_mode
15243 && bytemode
!= evex_half_bcst_xmmq_mode
15244 && bytemode
!= ymm_mode
15245 && bytemode
!= d_scalar_swap_mode
15246 && bytemode
!= q_scalar_swap_mode
15247 && bytemode
!= vex_scalar_w_dq_mode
)
15249 switch (vex
.length
)
15264 else if (bytemode
== xmmq_mode
15265 || bytemode
== evex_half_bcst_xmmq_mode
)
15267 switch (vex
.length
)
15280 else if (bytemode
== ymm_mode
)
15284 oappend (names
[reg
]);
15288 OP_MS (int bytemode
, int sizeflag
)
15290 if (modrm
.mod
== 3)
15291 OP_EM (bytemode
, sizeflag
);
15297 OP_XS (int bytemode
, int sizeflag
)
15299 if (modrm
.mod
== 3)
15300 OP_EX (bytemode
, sizeflag
);
15306 OP_M (int bytemode
, int sizeflag
)
15308 if (modrm
.mod
== 3)
15309 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
15312 OP_E (bytemode
, sizeflag
);
15316 OP_0f07 (int bytemode
, int sizeflag
)
15318 if (modrm
.mod
!= 3 || modrm
.rm
!= 0)
15321 OP_E (bytemode
, sizeflag
);
15324 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
15325 32bit mode and "xchg %rax,%rax" in 64bit mode. */
15328 NOP_Fixup1 (int bytemode
, int sizeflag
)
15330 if ((prefixes
& PREFIX_DATA
) != 0
15333 && address_mode
== mode_64bit
))
15334 OP_REG (bytemode
, sizeflag
);
15336 strcpy (obuf
, "nop");
15340 NOP_Fixup2 (int bytemode
, int sizeflag
)
15342 if ((prefixes
& PREFIX_DATA
) != 0
15345 && address_mode
== mode_64bit
))
15346 OP_IMREG (bytemode
, sizeflag
);
15349 static const char *const Suffix3DNow
[] = {
15350 /* 00 */ NULL
, NULL
, NULL
, NULL
,
15351 /* 04 */ NULL
, NULL
, NULL
, NULL
,
15352 /* 08 */ NULL
, NULL
, NULL
, NULL
,
15353 /* 0C */ "pi2fw", "pi2fd", NULL
, NULL
,
15354 /* 10 */ NULL
, NULL
, NULL
, NULL
,
15355 /* 14 */ NULL
, NULL
, NULL
, NULL
,
15356 /* 18 */ NULL
, NULL
, NULL
, NULL
,
15357 /* 1C */ "pf2iw", "pf2id", NULL
, NULL
,
15358 /* 20 */ NULL
, NULL
, NULL
, NULL
,
15359 /* 24 */ NULL
, NULL
, NULL
, NULL
,
15360 /* 28 */ NULL
, NULL
, NULL
, NULL
,
15361 /* 2C */ NULL
, NULL
, NULL
, NULL
,
15362 /* 30 */ NULL
, NULL
, NULL
, NULL
,
15363 /* 34 */ NULL
, NULL
, NULL
, NULL
,
15364 /* 38 */ NULL
, NULL
, NULL
, NULL
,
15365 /* 3C */ NULL
, NULL
, NULL
, NULL
,
15366 /* 40 */ NULL
, NULL
, NULL
, NULL
,
15367 /* 44 */ NULL
, NULL
, NULL
, NULL
,
15368 /* 48 */ NULL
, NULL
, NULL
, NULL
,
15369 /* 4C */ NULL
, NULL
, NULL
, NULL
,
15370 /* 50 */ NULL
, NULL
, NULL
, NULL
,
15371 /* 54 */ NULL
, NULL
, NULL
, NULL
,
15372 /* 58 */ NULL
, NULL
, NULL
, NULL
,
15373 /* 5C */ NULL
, NULL
, NULL
, NULL
,
15374 /* 60 */ NULL
, NULL
, NULL
, NULL
,
15375 /* 64 */ NULL
, NULL
, NULL
, NULL
,
15376 /* 68 */ NULL
, NULL
, NULL
, NULL
,
15377 /* 6C */ NULL
, NULL
, NULL
, NULL
,
15378 /* 70 */ NULL
, NULL
, NULL
, NULL
,
15379 /* 74 */ NULL
, NULL
, NULL
, NULL
,
15380 /* 78 */ NULL
, NULL
, NULL
, NULL
,
15381 /* 7C */ NULL
, NULL
, NULL
, NULL
,
15382 /* 80 */ NULL
, NULL
, NULL
, NULL
,
15383 /* 84 */ NULL
, NULL
, NULL
, NULL
,
15384 /* 88 */ NULL
, NULL
, "pfnacc", NULL
,
15385 /* 8C */ NULL
, NULL
, "pfpnacc", NULL
,
15386 /* 90 */ "pfcmpge", NULL
, NULL
, NULL
,
15387 /* 94 */ "pfmin", NULL
, "pfrcp", "pfrsqrt",
15388 /* 98 */ NULL
, NULL
, "pfsub", NULL
,
15389 /* 9C */ NULL
, NULL
, "pfadd", NULL
,
15390 /* A0 */ "pfcmpgt", NULL
, NULL
, NULL
,
15391 /* A4 */ "pfmax", NULL
, "pfrcpit1", "pfrsqit1",
15392 /* A8 */ NULL
, NULL
, "pfsubr", NULL
,
15393 /* AC */ NULL
, NULL
, "pfacc", NULL
,
15394 /* B0 */ "pfcmpeq", NULL
, NULL
, NULL
,
15395 /* B4 */ "pfmul", NULL
, "pfrcpit2", "pmulhrw",
15396 /* B8 */ NULL
, NULL
, NULL
, "pswapd",
15397 /* BC */ NULL
, NULL
, NULL
, "pavgusb",
15398 /* C0 */ NULL
, NULL
, NULL
, NULL
,
15399 /* C4 */ NULL
, NULL
, NULL
, NULL
,
15400 /* C8 */ NULL
, NULL
, NULL
, NULL
,
15401 /* CC */ NULL
, NULL
, NULL
, NULL
,
15402 /* D0 */ NULL
, NULL
, NULL
, NULL
,
15403 /* D4 */ NULL
, NULL
, NULL
, NULL
,
15404 /* D8 */ NULL
, NULL
, NULL
, NULL
,
15405 /* DC */ NULL
, NULL
, NULL
, NULL
,
15406 /* E0 */ NULL
, NULL
, NULL
, NULL
,
15407 /* E4 */ NULL
, NULL
, NULL
, NULL
,
15408 /* E8 */ NULL
, NULL
, NULL
, NULL
,
15409 /* EC */ NULL
, NULL
, NULL
, NULL
,
15410 /* F0 */ NULL
, NULL
, NULL
, NULL
,
15411 /* F4 */ NULL
, NULL
, NULL
, NULL
,
15412 /* F8 */ NULL
, NULL
, NULL
, NULL
,
15413 /* FC */ NULL
, NULL
, NULL
, NULL
,
15417 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15419 const char *mnemonic
;
15421 FETCH_DATA (the_info
, codep
+ 1);
15422 /* AMD 3DNow! instructions are specified by an opcode suffix in the
15423 place where an 8-bit immediate would normally go. ie. the last
15424 byte of the instruction. */
15425 obufp
= mnemonicendp
;
15426 mnemonic
= Suffix3DNow
[*codep
++ & 0xff];
15428 oappend (mnemonic
);
15431 /* Since a variable sized modrm/sib chunk is between the start
15432 of the opcode (0x0f0f) and the opcode suffix, we need to do
15433 all the modrm processing first, and don't know until now that
15434 we have a bad opcode. This necessitates some cleaning up. */
15435 op_out
[0][0] = '\0';
15436 op_out
[1][0] = '\0';
15439 mnemonicendp
= obufp
;
15442 static struct op simd_cmp_op
[] =
15444 { STRING_COMMA_LEN ("eq") },
15445 { STRING_COMMA_LEN ("lt") },
15446 { STRING_COMMA_LEN ("le") },
15447 { STRING_COMMA_LEN ("unord") },
15448 { STRING_COMMA_LEN ("neq") },
15449 { STRING_COMMA_LEN ("nlt") },
15450 { STRING_COMMA_LEN ("nle") },
15451 { STRING_COMMA_LEN ("ord") }
15455 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15457 unsigned int cmp_type
;
15459 FETCH_DATA (the_info
, codep
+ 1);
15460 cmp_type
= *codep
++ & 0xff;
15461 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
))
15464 char *p
= mnemonicendp
- 2;
15468 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
15469 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
15473 /* We have a reserved extension byte. Output it directly. */
15474 scratchbuf
[0] = '$';
15475 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
15476 oappend_maybe_intel (scratchbuf
);
15477 scratchbuf
[0] = '\0';
15482 OP_Mwait (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
15484 /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx */
15487 strcpy (op_out
[0], names32
[0]);
15488 strcpy (op_out
[1], names32
[1]);
15489 if (bytemode
== eBX_reg
)
15490 strcpy (op_out
[2], names32
[3]);
15491 two_source_ops
= 1;
15493 /* Skip mod/rm byte. */
15499 OP_Monitor (int bytemode ATTRIBUTE_UNUSED
,
15500 int sizeflag ATTRIBUTE_UNUSED
)
15502 /* monitor %{e,r,}ax,%ecx,%edx" */
15505 const char **names
= (address_mode
== mode_64bit
15506 ? names64
: names32
);
15508 if (prefixes
& PREFIX_ADDR
)
15510 /* Remove "addr16/addr32". */
15511 all_prefixes
[last_addr_prefix
] = 0;
15512 names
= (address_mode
!= mode_32bit
15513 ? names32
: names16
);
15514 used_prefixes
|= PREFIX_ADDR
;
15516 else if (address_mode
== mode_16bit
)
15518 strcpy (op_out
[0], names
[0]);
15519 strcpy (op_out
[1], names32
[1]);
15520 strcpy (op_out
[2], names32
[2]);
15521 two_source_ops
= 1;
15523 /* Skip mod/rm byte. */
15531 /* Throw away prefixes and 1st. opcode byte. */
15532 codep
= insn_codep
+ 1;
15537 REP_Fixup (int bytemode
, int sizeflag
)
15539 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
15541 if (prefixes
& PREFIX_REPZ
)
15542 all_prefixes
[last_repz_prefix
] = REP_PREFIX
;
15549 OP_IMREG (bytemode
, sizeflag
);
15552 OP_ESreg (bytemode
, sizeflag
);
15555 OP_DSreg (bytemode
, sizeflag
);
15564 SEP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15566 if ( isa64
!= amd64
)
15571 mnemonicendp
= obufp
;
15575 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
15579 BND_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15581 if (prefixes
& PREFIX_REPNZ
)
15582 all_prefixes
[last_repnz_prefix
] = BND_PREFIX
;
15585 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
15589 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED
,
15590 int sizeflag ATTRIBUTE_UNUSED
)
15592 if (active_seg_prefix
== PREFIX_DS
15593 && (address_mode
!= mode_64bit
|| last_data_prefix
< 0))
15595 /* NOTRACK prefix is only valid on indirect branch instructions.
15596 NB: DATA prefix is unsupported for Intel64. */
15597 active_seg_prefix
= 0;
15598 all_prefixes
[last_seg_prefix
] = NOTRACK_PREFIX
;
15602 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
15603 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
15607 HLE_Fixup1 (int bytemode
, int sizeflag
)
15610 && (prefixes
& PREFIX_LOCK
) != 0)
15612 if (prefixes
& PREFIX_REPZ
)
15613 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15614 if (prefixes
& PREFIX_REPNZ
)
15615 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
15618 OP_E (bytemode
, sizeflag
);
15621 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
15622 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
15626 HLE_Fixup2 (int bytemode
, int sizeflag
)
15628 if (modrm
.mod
!= 3)
15630 if (prefixes
& PREFIX_REPZ
)
15631 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15632 if (prefixes
& PREFIX_REPNZ
)
15633 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
15636 OP_E (bytemode
, sizeflag
);
15639 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
15640 "xrelease" for memory operand. No check for LOCK prefix. */
15643 HLE_Fixup3 (int bytemode
, int sizeflag
)
15646 && last_repz_prefix
> last_repnz_prefix
15647 && (prefixes
& PREFIX_REPZ
) != 0)
15648 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15650 OP_E (bytemode
, sizeflag
);
15654 CMPXCHG8B_Fixup (int bytemode
, int sizeflag
)
15659 /* Change cmpxchg8b to cmpxchg16b. */
15660 char *p
= mnemonicendp
- 2;
15661 mnemonicendp
= stpcpy (p
, "16b");
15664 else if ((prefixes
& PREFIX_LOCK
) != 0)
15666 if (prefixes
& PREFIX_REPZ
)
15667 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15668 if (prefixes
& PREFIX_REPNZ
)
15669 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
15672 OP_M (bytemode
, sizeflag
);
15676 XMM_Fixup (int reg
, int sizeflag ATTRIBUTE_UNUSED
)
15678 const char **names
;
15682 switch (vex
.length
)
15696 oappend (names
[reg
]);
15700 CRC32_Fixup (int bytemode
, int sizeflag
)
15702 /* Add proper suffix to "crc32". */
15703 char *p
= mnemonicendp
;
15722 if (sizeflag
& DFLAG
)
15726 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15730 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15737 if (modrm
.mod
== 3)
15741 /* Skip mod/rm byte. */
15746 add
= (rex
& REX_B
) ? 8 : 0;
15747 if (bytemode
== b_mode
)
15751 oappend (names8rex
[modrm
.rm
+ add
]);
15753 oappend (names8
[modrm
.rm
+ add
]);
15759 oappend (names64
[modrm
.rm
+ add
]);
15760 else if ((prefixes
& PREFIX_DATA
))
15761 oappend (names16
[modrm
.rm
+ add
]);
15763 oappend (names32
[modrm
.rm
+ add
]);
15767 OP_E (bytemode
, sizeflag
);
15771 FXSAVE_Fixup (int bytemode
, int sizeflag
)
15773 /* Add proper suffix to "fxsave" and "fxrstor". */
15777 char *p
= mnemonicendp
;
15783 OP_M (bytemode
, sizeflag
);
15787 PCMPESTR_Fixup (int bytemode
, int sizeflag
)
15789 /* Add proper suffix to "{,v}pcmpestr{i,m}". */
15792 char *p
= mnemonicendp
;
15797 else if (sizeflag
& SUFFIX_ALWAYS
)
15804 OP_EX (bytemode
, sizeflag
);
15807 /* Display the destination register operand for instructions with
15811 OP_VEX (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
15814 const char **names
;
15822 reg
= vex
.register_specifier
;
15823 vex
.register_specifier
= 0;
15824 if (address_mode
!= mode_64bit
)
15826 else if (vex
.evex
&& !vex
.v
)
15829 if (bytemode
== vex_scalar_mode
)
15831 oappend (names_xmm
[reg
]);
15835 switch (vex
.length
)
15842 case vex_vsib_q_w_dq_mode
:
15843 case vex_vsib_q_w_d_mode
:
15859 names
= names_mask
;
15873 case vex_vsib_q_w_dq_mode
:
15874 case vex_vsib_q_w_d_mode
:
15875 names
= vex
.w
? names_ymm
: names_xmm
;
15884 names
= names_mask
;
15887 /* See PR binutils/20893 for a reproducer. */
15899 oappend (names
[reg
]);
15902 /* Get the VEX immediate byte without moving codep. */
15904 static unsigned char
15905 get_vex_imm8 (int sizeflag
, int opnum
)
15907 int bytes_before_imm
= 0;
15909 if (modrm
.mod
!= 3)
15911 /* There are SIB/displacement bytes. */
15912 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
15914 /* 32/64 bit address mode */
15915 int base
= modrm
.rm
;
15917 /* Check SIB byte. */
15920 FETCH_DATA (the_info
, codep
+ 1);
15922 /* When decoding the third source, don't increase
15923 bytes_before_imm as this has already been incremented
15924 by one in OP_E_memory while decoding the second
15927 bytes_before_imm
++;
15930 /* Don't increase bytes_before_imm when decoding the third source,
15931 it has already been incremented by OP_E_memory while decoding
15932 the second source operand. */
15938 /* When modrm.rm == 5 or modrm.rm == 4 and base in
15939 SIB == 5, there is a 4 byte displacement. */
15941 /* No displacement. */
15943 /* Fall through. */
15945 /* 4 byte displacement. */
15946 bytes_before_imm
+= 4;
15949 /* 1 byte displacement. */
15950 bytes_before_imm
++;
15957 /* 16 bit address mode */
15958 /* Don't increase bytes_before_imm when decoding the third source,
15959 it has already been incremented by OP_E_memory while decoding
15960 the second source operand. */
15966 /* When modrm.rm == 6, there is a 2 byte displacement. */
15968 /* No displacement. */
15970 /* Fall through. */
15972 /* 2 byte displacement. */
15973 bytes_before_imm
+= 2;
15976 /* 1 byte displacement: when decoding the third source,
15977 don't increase bytes_before_imm as this has already
15978 been incremented by one in OP_E_memory while decoding
15979 the second source operand. */
15981 bytes_before_imm
++;
15989 FETCH_DATA (the_info
, codep
+ bytes_before_imm
+ 1);
15990 return codep
[bytes_before_imm
];
15994 OP_EX_VexReg (int bytemode
, int sizeflag
, int reg
)
15996 const char **names
;
15998 if (reg
== -1 && modrm
.mod
!= 3)
16000 OP_E_memory (bytemode
, sizeflag
);
16012 if (address_mode
!= mode_64bit
)
16016 switch (vex
.length
)
16027 oappend (names
[reg
]);
16031 OP_EX_VexImmW (int bytemode
, int sizeflag
)
16034 static unsigned char vex_imm8
;
16036 if (vex_w_done
== 0)
16040 /* Skip mod/rm byte. */
16044 vex_imm8
= get_vex_imm8 (sizeflag
, 0);
16047 reg
= vex_imm8
>> 4;
16049 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
16051 else if (vex_w_done
== 1)
16056 reg
= vex_imm8
>> 4;
16058 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
16062 /* Output the imm8 directly. */
16063 scratchbuf
[0] = '$';
16064 print_operand_value (scratchbuf
+ 1, 1, vex_imm8
& 0xf);
16065 oappend_maybe_intel (scratchbuf
);
16066 scratchbuf
[0] = '\0';
16072 OP_Vex_2src (int bytemode
, int sizeflag
)
16074 if (modrm
.mod
== 3)
16076 int reg
= modrm
.rm
;
16080 oappend (names_xmm
[reg
]);
16085 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
16087 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
16088 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16090 OP_E (bytemode
, sizeflag
);
16095 OP_Vex_2src_1 (int bytemode
, int sizeflag
)
16097 if (modrm
.mod
== 3)
16099 /* Skip mod/rm byte. */
16106 unsigned int reg
= vex
.register_specifier
;
16107 vex
.register_specifier
= 0;
16109 if (address_mode
!= mode_64bit
)
16111 oappend (names_xmm
[reg
]);
16114 OP_Vex_2src (bytemode
, sizeflag
);
16118 OP_Vex_2src_2 (int bytemode
, int sizeflag
)
16121 OP_Vex_2src (bytemode
, sizeflag
);
16124 unsigned int reg
= vex
.register_specifier
;
16125 vex
.register_specifier
= 0;
16127 if (address_mode
!= mode_64bit
)
16129 oappend (names_xmm
[reg
]);
16134 OP_EX_VexW (int bytemode
, int sizeflag
)
16140 /* Skip mod/rm byte. */
16145 reg
= get_vex_imm8 (sizeflag
, 0) >> 4;
16150 reg
= get_vex_imm8 (sizeflag
, 1) >> 4;
16153 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
16161 OP_REG_VexI4 (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16164 const char **names
;
16166 FETCH_DATA (the_info
, codep
+ 1);
16169 if (bytemode
!= x_mode
)
16173 if (address_mode
!= mode_64bit
)
16176 switch (vex
.length
)
16187 oappend (names
[reg
]);
16191 OP_XMM_VexW (int bytemode
, int sizeflag
)
16193 /* Turn off the REX.W bit since it is used for swapping operands
16196 OP_XMM (bytemode
, sizeflag
);
16200 OP_EX_Vex (int bytemode
, int sizeflag
)
16202 if (modrm
.mod
!= 3)
16204 OP_EX (bytemode
, sizeflag
);
16208 OP_XMM_Vex (int bytemode
, int sizeflag
)
16210 if (modrm
.mod
!= 3)
16212 OP_XMM (bytemode
, sizeflag
);
16215 static struct op vex_cmp_op
[] =
16217 { STRING_COMMA_LEN ("eq") },
16218 { STRING_COMMA_LEN ("lt") },
16219 { STRING_COMMA_LEN ("le") },
16220 { STRING_COMMA_LEN ("unord") },
16221 { STRING_COMMA_LEN ("neq") },
16222 { STRING_COMMA_LEN ("nlt") },
16223 { STRING_COMMA_LEN ("nle") },
16224 { STRING_COMMA_LEN ("ord") },
16225 { STRING_COMMA_LEN ("eq_uq") },
16226 { STRING_COMMA_LEN ("nge") },
16227 { STRING_COMMA_LEN ("ngt") },
16228 { STRING_COMMA_LEN ("false") },
16229 { STRING_COMMA_LEN ("neq_oq") },
16230 { STRING_COMMA_LEN ("ge") },
16231 { STRING_COMMA_LEN ("gt") },
16232 { STRING_COMMA_LEN ("true") },
16233 { STRING_COMMA_LEN ("eq_os") },
16234 { STRING_COMMA_LEN ("lt_oq") },
16235 { STRING_COMMA_LEN ("le_oq") },
16236 { STRING_COMMA_LEN ("unord_s") },
16237 { STRING_COMMA_LEN ("neq_us") },
16238 { STRING_COMMA_LEN ("nlt_uq") },
16239 { STRING_COMMA_LEN ("nle_uq") },
16240 { STRING_COMMA_LEN ("ord_s") },
16241 { STRING_COMMA_LEN ("eq_us") },
16242 { STRING_COMMA_LEN ("nge_uq") },
16243 { STRING_COMMA_LEN ("ngt_uq") },
16244 { STRING_COMMA_LEN ("false_os") },
16245 { STRING_COMMA_LEN ("neq_os") },
16246 { STRING_COMMA_LEN ("ge_oq") },
16247 { STRING_COMMA_LEN ("gt_oq") },
16248 { STRING_COMMA_LEN ("true_us") },
16252 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16254 unsigned int cmp_type
;
16256 FETCH_DATA (the_info
, codep
+ 1);
16257 cmp_type
= *codep
++ & 0xff;
16258 if (cmp_type
< ARRAY_SIZE (vex_cmp_op
))
16261 char *p
= mnemonicendp
- 2;
16265 sprintf (p
, "%s%s", vex_cmp_op
[cmp_type
].name
, suffix
);
16266 mnemonicendp
+= vex_cmp_op
[cmp_type
].len
;
16270 /* We have a reserved extension byte. Output it directly. */
16271 scratchbuf
[0] = '$';
16272 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16273 oappend_maybe_intel (scratchbuf
);
16274 scratchbuf
[0] = '\0';
16279 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
,
16280 int sizeflag ATTRIBUTE_UNUSED
)
16282 unsigned int cmp_type
;
16287 FETCH_DATA (the_info
, codep
+ 1);
16288 cmp_type
= *codep
++ & 0xff;
16289 /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
16290 If it's the case, print suffix, otherwise - print the immediate. */
16291 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
)
16296 char *p
= mnemonicendp
- 2;
16298 /* vpcmp* can have both one- and two-lettered suffix. */
16312 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
16313 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
16317 /* We have a reserved extension byte. Output it directly. */
16318 scratchbuf
[0] = '$';
16319 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16320 oappend_maybe_intel (scratchbuf
);
16321 scratchbuf
[0] = '\0';
16325 static const struct op xop_cmp_op
[] =
16327 { STRING_COMMA_LEN ("lt") },
16328 { STRING_COMMA_LEN ("le") },
16329 { STRING_COMMA_LEN ("gt") },
16330 { STRING_COMMA_LEN ("ge") },
16331 { STRING_COMMA_LEN ("eq") },
16332 { STRING_COMMA_LEN ("neq") },
16333 { STRING_COMMA_LEN ("false") },
16334 { STRING_COMMA_LEN ("true") }
16338 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED
,
16339 int sizeflag ATTRIBUTE_UNUSED
)
16341 unsigned int cmp_type
;
16343 FETCH_DATA (the_info
, codep
+ 1);
16344 cmp_type
= *codep
++ & 0xff;
16345 if (cmp_type
< ARRAY_SIZE (xop_cmp_op
))
16348 char *p
= mnemonicendp
- 2;
16350 /* vpcom* can have both one- and two-lettered suffix. */
16364 sprintf (p
, "%s%s", xop_cmp_op
[cmp_type
].name
, suffix
);
16365 mnemonicendp
+= xop_cmp_op
[cmp_type
].len
;
16369 /* We have a reserved extension byte. Output it directly. */
16370 scratchbuf
[0] = '$';
16371 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16372 oappend_maybe_intel (scratchbuf
);
16373 scratchbuf
[0] = '\0';
16377 static const struct op pclmul_op
[] =
16379 { STRING_COMMA_LEN ("lql") },
16380 { STRING_COMMA_LEN ("hql") },
16381 { STRING_COMMA_LEN ("lqh") },
16382 { STRING_COMMA_LEN ("hqh") }
16386 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED
,
16387 int sizeflag ATTRIBUTE_UNUSED
)
16389 unsigned int pclmul_type
;
16391 FETCH_DATA (the_info
, codep
+ 1);
16392 pclmul_type
= *codep
++ & 0xff;
16393 switch (pclmul_type
)
16404 if (pclmul_type
< ARRAY_SIZE (pclmul_op
))
16407 char *p
= mnemonicendp
- 3;
16412 sprintf (p
, "%s%s", pclmul_op
[pclmul_type
].name
, suffix
);
16413 mnemonicendp
+= pclmul_op
[pclmul_type
].len
;
16417 /* We have a reserved extension byte. Output it directly. */
16418 scratchbuf
[0] = '$';
16419 print_operand_value (scratchbuf
+ 1, 1, pclmul_type
);
16420 oappend_maybe_intel (scratchbuf
);
16421 scratchbuf
[0] = '\0';
16426 MOVBE_Fixup (int bytemode
, int sizeflag
)
16428 /* Add proper suffix to "movbe". */
16429 char *p
= mnemonicendp
;
16438 if (sizeflag
& SUFFIX_ALWAYS
)
16444 if (sizeflag
& DFLAG
)
16448 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16453 oappend (INTERNAL_DISASSEMBLER_ERROR
);
16460 OP_M (bytemode
, sizeflag
);
16464 MOVSXD_Fixup (int bytemode
, int sizeflag
)
16466 /* Add proper suffix to "movsxd". */
16467 char *p
= mnemonicendp
;
16492 oappend (INTERNAL_DISASSEMBLER_ERROR
);
16499 OP_E (bytemode
, sizeflag
);
16503 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16506 const char **names
;
16508 /* Skip mod/rm byte. */
16522 oappend (names
[reg
]);
16526 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16528 const char **names
;
16529 unsigned int reg
= vex
.register_specifier
;
16530 vex
.register_specifier
= 0;
16537 if (address_mode
!= mode_64bit
)
16539 oappend (names
[reg
]);
16543 OP_Mask (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16546 || (bytemode
!= mask_mode
&& bytemode
!= mask_bd_mode
))
16550 if ((rex
& REX_R
) != 0 || !vex
.r
)
16556 oappend (names_mask
[modrm
.reg
]);
16560 OP_Rounding (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16562 if (modrm
.mod
== 3 && vex
.b
)
16565 case evex_rounding_64_mode
:
16566 if (address_mode
!= mode_64bit
)
16571 /* Fall through. */
16572 case evex_rounding_mode
:
16573 oappend (names_rounding
[vex
.ll
]);
16575 case evex_sae_mode
: