1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988-2021 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
24 modified by John Hassey (hassey@dg-rtp.dg.com)
25 x86-64 support added by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
28 /* The main tables describing the instructions is essentially a copy
29 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30 Programmers Manual. Usually, there is a capital letter, followed
31 by a small letter. The capital letter tell the addressing mode,
32 and the small letter tells about the operand size. Refer to
33 the Intel manual for details. */
36 #include "disassemble.h"
38 #include "opcode/i386.h"
39 #include "libiberty.h"
40 #include "safe-ctype.h"
44 static int print_insn (bfd_vma
, disassemble_info
*);
45 static void dofloat (int);
46 static void OP_ST (int, int);
47 static void OP_STi (int, int);
48 static int putop (const char *, int);
49 static void oappend (const char *);
50 static void append_seg (void);
51 static void OP_indirE (int, int);
52 static void print_operand_value (char *, int, bfd_vma
);
53 static void OP_E_register (int, int);
54 static void OP_E_memory (int, int);
55 static void print_displacement (char *, bfd_vma
);
56 static void OP_E (int, int);
57 static void OP_G (int, int);
58 static bfd_vma
get64 (void);
59 static bfd_signed_vma
get32 (void);
60 static bfd_signed_vma
get32s (void);
61 static int get16 (void);
62 static void set_op (bfd_vma
, int);
63 static void OP_Skip_MODRM (int, int);
64 static void OP_REG (int, int);
65 static void OP_IMREG (int, int);
66 static void OP_I (int, int);
67 static void OP_I64 (int, int);
68 static void OP_sI (int, int);
69 static void OP_J (int, int);
70 static void OP_SEG (int, int);
71 static void OP_DIR (int, int);
72 static void OP_OFF (int, int);
73 static void OP_OFF64 (int, int);
74 static void ptr_reg (int, int);
75 static void OP_ESreg (int, int);
76 static void OP_DSreg (int, int);
77 static void OP_C (int, int);
78 static void OP_D (int, int);
79 static void OP_T (int, int);
80 static void OP_MMX (int, int);
81 static void OP_XMM (int, int);
82 static void OP_EM (int, int);
83 static void OP_EX (int, int);
84 static void OP_EMC (int,int);
85 static void OP_MXC (int,int);
86 static void OP_MS (int, int);
87 static void OP_XS (int, int);
88 static void OP_M (int, int);
89 static void OP_VEX (int, int);
90 static void OP_VexR (int, int);
91 static void OP_VexW (int, int);
92 static void OP_Rounding (int, int);
93 static void OP_REG_VexI4 (int, int);
94 static void OP_VexI4 (int, int);
95 static void PCLMUL_Fixup (int, int);
96 static void VPCMP_Fixup (int, int);
97 static void VPCOM_Fixup (int, int);
98 static void OP_0f07 (int, int);
99 static void OP_Monitor (int, int);
100 static void OP_Mwait (int, int);
101 static void NOP_Fixup1 (int, int);
102 static void NOP_Fixup2 (int, int);
103 static void OP_3DNowSuffix (int, int);
104 static void CMP_Fixup (int, int);
105 static void BadOp (void);
106 static void REP_Fixup (int, int);
107 static void SEP_Fixup (int, int);
108 static void BND_Fixup (int, int);
109 static void NOTRACK_Fixup (int, int);
110 static void HLE_Fixup1 (int, int);
111 static void HLE_Fixup2 (int, int);
112 static void HLE_Fixup3 (int, int);
113 static void CMPXCHG8B_Fixup (int, int);
114 static void XMM_Fixup (int, int);
115 static void FXSAVE_Fixup (int, int);
117 static void MOVSXD_Fixup (int, int);
119 static void OP_Mask (int, int);
122 /* Points to first byte not fetched. */
123 bfd_byte
*max_fetched
;
124 bfd_byte the_buffer
[MAX_MNEM_SIZE
];
127 OPCODES_SIGJMP_BUF bailout
;
137 enum address_mode address_mode
;
139 /* Flags for the prefixes for the current instruction. See below. */
142 /* REX prefix the current instruction. See below. */
144 /* Bits of REX we've already used. */
146 /* Mark parts used in the REX prefix. When we are testing for
147 empty prefix (for 8bit register REX extension), just mask it
148 out. Otherwise test for REX bit is excuse for existence of REX
149 only in case value is nonzero. */
150 #define USED_REX(value) \
155 rex_used |= (value) | REX_OPCODE; \
158 rex_used |= REX_OPCODE; \
161 /* Flags for prefixes which we somehow handled when printing the
162 current instruction. */
163 static int used_prefixes
;
165 /* Flags stored in PREFIXES. */
166 #define PREFIX_REPZ 1
167 #define PREFIX_REPNZ 2
168 #define PREFIX_LOCK 4
170 #define PREFIX_SS 0x10
171 #define PREFIX_DS 0x20
172 #define PREFIX_ES 0x40
173 #define PREFIX_FS 0x80
174 #define PREFIX_GS 0x100
175 #define PREFIX_DATA 0x200
176 #define PREFIX_ADDR 0x400
177 #define PREFIX_FWAIT 0x800
179 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
180 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
182 #define FETCH_DATA(info, addr) \
183 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
184 ? 1 : fetch_data ((info), (addr)))
187 fetch_data (struct disassemble_info
*info
, bfd_byte
*addr
)
190 struct dis_private
*priv
= (struct dis_private
*) info
->private_data
;
191 bfd_vma start
= priv
->insn_start
+ (priv
->max_fetched
- priv
->the_buffer
);
193 if (addr
<= priv
->the_buffer
+ MAX_MNEM_SIZE
)
194 status
= (*info
->read_memory_func
) (start
,
196 addr
- priv
->max_fetched
,
202 /* If we did manage to read at least one byte, then
203 print_insn_i386 will do something sensible. Otherwise, print
204 an error. We do that here because this is where we know
206 if (priv
->max_fetched
== priv
->the_buffer
)
207 (*info
->memory_error_func
) (status
, start
, info
);
208 OPCODES_SIGLONGJMP (priv
->bailout
, 1);
211 priv
->max_fetched
= addr
;
215 /* Possible values for prefix requirement. */
216 #define PREFIX_IGNORED_SHIFT 16
217 #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
218 #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
219 #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
220 #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
221 #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
223 /* Opcode prefixes. */
224 #define PREFIX_OPCODE (PREFIX_REPZ \
228 /* Prefixes ignored. */
229 #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \
230 | PREFIX_IGNORED_REPNZ \
231 | PREFIX_IGNORED_DATA)
233 #define XX { NULL, 0 }
234 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
236 #define Eb { OP_E, b_mode }
237 #define Ebnd { OP_E, bnd_mode }
238 #define EbS { OP_E, b_swap_mode }
239 #define EbndS { OP_E, bnd_swap_mode }
240 #define Ev { OP_E, v_mode }
241 #define Eva { OP_E, va_mode }
242 #define Ev_bnd { OP_E, v_bnd_mode }
243 #define EvS { OP_E, v_swap_mode }
244 #define Ed { OP_E, d_mode }
245 #define Edq { OP_E, dq_mode }
246 #define Edqw { OP_E, dqw_mode }
247 #define Edqb { OP_E, dqb_mode }
248 #define Edb { OP_E, db_mode }
249 #define Edw { OP_E, dw_mode }
250 #define Edqd { OP_E, dqd_mode }
251 #define Eq { OP_E, q_mode }
252 #define indirEv { OP_indirE, indir_v_mode }
253 #define indirEp { OP_indirE, f_mode }
254 #define stackEv { OP_E, stack_v_mode }
255 #define Em { OP_E, m_mode }
256 #define Ew { OP_E, w_mode }
257 #define M { OP_M, 0 } /* lea, lgdt, etc. */
258 #define Ma { OP_M, a_mode }
259 #define Mb { OP_M, b_mode }
260 #define Md { OP_M, d_mode }
261 #define Mo { OP_M, o_mode }
262 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
263 #define Mq { OP_M, q_mode }
264 #define Mv { OP_M, v_mode }
265 #define Mv_bnd { OP_M, v_bndmk_mode }
266 #define Mx { OP_M, x_mode }
267 #define Mxmm { OP_M, xmm_mode }
268 #define Gb { OP_G, b_mode }
269 #define Gbnd { OP_G, bnd_mode }
270 #define Gv { OP_G, v_mode }
271 #define Gd { OP_G, d_mode }
272 #define Gdq { OP_G, dq_mode }
273 #define Gm { OP_G, m_mode }
274 #define Gva { OP_G, va_mode }
275 #define Gw { OP_G, w_mode }
276 #define Ib { OP_I, b_mode }
277 #define sIb { OP_sI, b_mode } /* sign extened byte */
278 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
279 #define Iv { OP_I, v_mode }
280 #define sIv { OP_sI, v_mode }
281 #define Iv64 { OP_I64, v_mode }
282 #define Id { OP_I, d_mode }
283 #define Iw { OP_I, w_mode }
284 #define I1 { OP_I, const_1_mode }
285 #define Jb { OP_J, b_mode }
286 #define Jv { OP_J, v_mode }
287 #define Jdqw { OP_J, dqw_mode }
288 #define Cm { OP_C, m_mode }
289 #define Dm { OP_D, m_mode }
290 #define Td { OP_T, d_mode }
291 #define Skip_MODRM { OP_Skip_MODRM, 0 }
293 #define RMeAX { OP_REG, eAX_reg }
294 #define RMeBX { OP_REG, eBX_reg }
295 #define RMeCX { OP_REG, eCX_reg }
296 #define RMeDX { OP_REG, eDX_reg }
297 #define RMeSP { OP_REG, eSP_reg }
298 #define RMeBP { OP_REG, eBP_reg }
299 #define RMeSI { OP_REG, eSI_reg }
300 #define RMeDI { OP_REG, eDI_reg }
301 #define RMrAX { OP_REG, rAX_reg }
302 #define RMrBX { OP_REG, rBX_reg }
303 #define RMrCX { OP_REG, rCX_reg }
304 #define RMrDX { OP_REG, rDX_reg }
305 #define RMrSP { OP_REG, rSP_reg }
306 #define RMrBP { OP_REG, rBP_reg }
307 #define RMrSI { OP_REG, rSI_reg }
308 #define RMrDI { OP_REG, rDI_reg }
309 #define RMAL { OP_REG, al_reg }
310 #define RMCL { OP_REG, cl_reg }
311 #define RMDL { OP_REG, dl_reg }
312 #define RMBL { OP_REG, bl_reg }
313 #define RMAH { OP_REG, ah_reg }
314 #define RMCH { OP_REG, ch_reg }
315 #define RMDH { OP_REG, dh_reg }
316 #define RMBH { OP_REG, bh_reg }
317 #define RMAX { OP_REG, ax_reg }
318 #define RMDX { OP_REG, dx_reg }
320 #define eAX { OP_IMREG, eAX_reg }
321 #define AL { OP_IMREG, al_reg }
322 #define CL { OP_IMREG, cl_reg }
323 #define zAX { OP_IMREG, z_mode_ax_reg }
324 #define indirDX { OP_IMREG, indir_dx_reg }
326 #define Sw { OP_SEG, w_mode }
327 #define Sv { OP_SEG, v_mode }
328 #define Ap { OP_DIR, 0 }
329 #define Ob { OP_OFF64, b_mode }
330 #define Ov { OP_OFF64, v_mode }
331 #define Xb { OP_DSreg, eSI_reg }
332 #define Xv { OP_DSreg, eSI_reg }
333 #define Xz { OP_DSreg, eSI_reg }
334 #define Yb { OP_ESreg, eDI_reg }
335 #define Yv { OP_ESreg, eDI_reg }
336 #define DSBX { OP_DSreg, eBX_reg }
338 #define es { OP_REG, es_reg }
339 #define ss { OP_REG, ss_reg }
340 #define cs { OP_REG, cs_reg }
341 #define ds { OP_REG, ds_reg }
342 #define fs { OP_REG, fs_reg }
343 #define gs { OP_REG, gs_reg }
345 #define MX { OP_MMX, 0 }
346 #define XM { OP_XMM, 0 }
347 #define XMScalar { OP_XMM, scalar_mode }
348 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
349 #define XMM { OP_XMM, xmm_mode }
350 #define TMM { OP_XMM, tmm_mode }
351 #define XMxmmq { OP_XMM, xmmq_mode }
352 #define EM { OP_EM, v_mode }
353 #define EMS { OP_EM, v_swap_mode }
354 #define EMd { OP_EM, d_mode }
355 #define EMx { OP_EM, x_mode }
356 #define EXbwUnit { OP_EX, bw_unit_mode }
357 #define EXw { OP_EX, w_mode }
358 #define EXd { OP_EX, d_mode }
359 #define EXdS { OP_EX, d_swap_mode }
360 #define EXq { OP_EX, q_mode }
361 #define EXqS { OP_EX, q_swap_mode }
362 #define EXx { OP_EX, x_mode }
363 #define EXxS { OP_EX, x_swap_mode }
364 #define EXxmm { OP_EX, xmm_mode }
365 #define EXymm { OP_EX, ymm_mode }
366 #define EXtmm { OP_EX, tmm_mode }
367 #define EXxmmq { OP_EX, xmmq_mode }
368 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
369 #define EXxmm_mb { OP_EX, xmm_mb_mode }
370 #define EXxmm_mw { OP_EX, xmm_mw_mode }
371 #define EXxmm_md { OP_EX, xmm_md_mode }
372 #define EXxmm_mq { OP_EX, xmm_mq_mode }
373 #define EXxmmdw { OP_EX, xmmdw_mode }
374 #define EXxmmqd { OP_EX, xmmqd_mode }
375 #define EXymmq { OP_EX, ymmq_mode }
376 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
377 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
378 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
379 #define MS { OP_MS, v_mode }
380 #define XS { OP_XS, v_mode }
381 #define EMCq { OP_EMC, q_mode }
382 #define MXC { OP_MXC, 0 }
383 #define OPSUF { OP_3DNowSuffix, 0 }
384 #define SEP { SEP_Fixup, 0 }
385 #define CMP { CMP_Fixup, 0 }
386 #define XMM0 { XMM_Fixup, 0 }
387 #define FXSAVE { FXSAVE_Fixup, 0 }
389 #define Vex { OP_VEX, vex_mode }
390 #define VexW { OP_VexW, vex_mode }
391 #define VexScalar { OP_VEX, vex_scalar_mode }
392 #define VexScalarR { OP_VexR, vex_scalar_mode }
393 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
394 #define VexGdq { OP_VEX, dq_mode }
395 #define VexTmm { OP_VEX, tmm_mode }
396 #define XMVexI4 { OP_REG_VexI4, x_mode }
397 #define XMVexScalarI4 { OP_REG_VexI4, scalar_mode }
398 #define VexI4 { OP_VexI4, 0 }
399 #define PCLMUL { PCLMUL_Fixup, 0 }
400 #define VPCMP { VPCMP_Fixup, 0 }
401 #define VPCOM { VPCOM_Fixup, 0 }
403 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
404 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
405 #define EXxEVexS { OP_Rounding, evex_sae_mode }
407 #define XMask { OP_Mask, mask_mode }
408 #define MaskG { OP_G, mask_mode }
409 #define MaskE { OP_E, mask_mode }
410 #define MaskBDE { OP_E, mask_bd_mode }
411 #define MaskVex { OP_VEX, mask_mode }
413 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
414 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
415 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
416 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
418 #define MVexSIBMEM { OP_M, vex_sibmem_mode }
420 /* Used handle "rep" prefix for string instructions. */
421 #define Xbr { REP_Fixup, eSI_reg }
422 #define Xvr { REP_Fixup, eSI_reg }
423 #define Ybr { REP_Fixup, eDI_reg }
424 #define Yvr { REP_Fixup, eDI_reg }
425 #define Yzr { REP_Fixup, eDI_reg }
426 #define indirDXr { REP_Fixup, indir_dx_reg }
427 #define ALr { REP_Fixup, al_reg }
428 #define eAXr { REP_Fixup, eAX_reg }
430 /* Used handle HLE prefix for lockable instructions. */
431 #define Ebh1 { HLE_Fixup1, b_mode }
432 #define Evh1 { HLE_Fixup1, v_mode }
433 #define Ebh2 { HLE_Fixup2, b_mode }
434 #define Evh2 { HLE_Fixup2, v_mode }
435 #define Ebh3 { HLE_Fixup3, b_mode }
436 #define Evh3 { HLE_Fixup3, v_mode }
438 #define BND { BND_Fixup, 0 }
439 #define NOTRACK { NOTRACK_Fixup, 0 }
441 #define cond_jump_flag { NULL, cond_jump_mode }
442 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
444 /* bits in sizeflag */
445 #define SUFFIX_ALWAYS 4
453 /* byte operand with operand swapped */
455 /* byte operand, sign extend like 'T' suffix */
457 /* operand size depends on prefixes */
459 /* operand size depends on prefixes with operand swapped */
461 /* operand size depends on address prefix */
465 /* double word operand */
467 /* double word operand with operand swapped */
469 /* quad word operand */
471 /* quad word operand with operand swapped */
473 /* ten-byte operand */
475 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
476 broadcast enabled. */
478 /* Similar to x_mode, but with different EVEX mem shifts. */
480 /* Similar to x_mode, but with yet different EVEX mem shifts. */
482 /* Similar to x_mode, but with disabled broadcast. */
484 /* Similar to x_mode, but with operands swapped and disabled broadcast
487 /* 16-byte XMM operand */
489 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
490 memory operand (depending on vector length). Broadcast isn't
493 /* Same as xmmq_mode, but broadcast is allowed. */
494 evex_half_bcst_xmmq_mode
,
495 /* XMM register or byte memory operand */
497 /* XMM register or word memory operand */
499 /* XMM register or double word memory operand */
501 /* XMM register or quad word memory operand */
503 /* 16-byte XMM, word, double word or quad word operand. */
505 /* 16-byte XMM, double word, quad word operand or xmm word operand. */
507 /* 32-byte YMM operand */
509 /* quad word, ymmword or zmmword memory operand. */
511 /* 32-byte YMM or 16-byte word operand */
515 /* d_mode in 32bit, q_mode in 64bit mode. */
517 /* pair of v_mode operands */
523 /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode. */
525 /* operand size depends on REX prefixes. */
527 /* registers like dq_mode, memory like w_mode, displacements like
528 v_mode without considering Intel64 ISA. */
532 /* bounds operand with operand swapped */
534 /* 4- or 6-byte pointer operand */
537 /* v_mode for indirect branch opcodes. */
539 /* v_mode for stack-related opcodes. */
541 /* non-quad operand size depends on prefixes */
543 /* 16-byte operand */
545 /* registers like dq_mode, memory like b_mode. */
547 /* registers like d_mode, memory like b_mode. */
549 /* registers like d_mode, memory like w_mode. */
551 /* registers like dq_mode, memory like d_mode. */
553 /* normal vex mode */
556 /* Operand size depends on the VEX.W bit, with VSIB dword indices. */
557 vex_vsib_d_w_dq_mode
,
558 /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */
560 /* Operand size depends on the VEX.W bit, with VSIB qword indices. */
561 vex_vsib_q_w_dq_mode
,
562 /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */
564 /* mandatory non-vector SIB. */
567 /* scalar, ignore vector length. */
569 /* like vex_mode, ignore vector length. */
571 /* Operand size depends on the VEX.W bit, ignore vector length. */
572 vex_scalar_w_dq_mode
,
574 /* Static rounding. */
576 /* Static rounding, 64-bit mode only. */
577 evex_rounding_64_mode
,
578 /* Supress all exceptions. */
581 /* Mask register operand. */
583 /* Mask register operand. */
651 #define FLOAT NULL, { { NULL, FLOATCODE } }, 0
653 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0
654 #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P
655 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
656 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
657 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
658 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
659 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
660 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
661 #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
662 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
663 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
664 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
665 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
666 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
667 #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I))
668 #define EVEX_LEN_TABLE(I) DIS386 (USE_EVEX_LEN_TABLE, (I))
695 REG_0F3A0F_PREFIX_1_MOD_3
,
708 REG_VEX_0F3849_X86_64_P_0_W_0_M_1
,
713 REG_0FXOP_09_12_M_1_L_0
,
807 MOD_VEX_0F12_PREFIX_0
,
808 MOD_VEX_0F12_PREFIX_2
,
810 MOD_VEX_0F16_PREFIX_0
,
811 MOD_VEX_0F16_PREFIX_2
,
814 MOD_VEX_W_0_0F41_P_0_LEN_1
,
815 MOD_VEX_W_1_0F41_P_0_LEN_1
,
816 MOD_VEX_W_0_0F41_P_2_LEN_1
,
817 MOD_VEX_W_1_0F41_P_2_LEN_1
,
818 MOD_VEX_W_0_0F42_P_0_LEN_1
,
819 MOD_VEX_W_1_0F42_P_0_LEN_1
,
820 MOD_VEX_W_0_0F42_P_2_LEN_1
,
821 MOD_VEX_W_1_0F42_P_2_LEN_1
,
822 MOD_VEX_W_0_0F44_P_0_LEN_1
,
823 MOD_VEX_W_1_0F44_P_0_LEN_1
,
824 MOD_VEX_W_0_0F44_P_2_LEN_1
,
825 MOD_VEX_W_1_0F44_P_2_LEN_1
,
826 MOD_VEX_W_0_0F45_P_0_LEN_1
,
827 MOD_VEX_W_1_0F45_P_0_LEN_1
,
828 MOD_VEX_W_0_0F45_P_2_LEN_1
,
829 MOD_VEX_W_1_0F45_P_2_LEN_1
,
830 MOD_VEX_W_0_0F46_P_0_LEN_1
,
831 MOD_VEX_W_1_0F46_P_0_LEN_1
,
832 MOD_VEX_W_0_0F46_P_2_LEN_1
,
833 MOD_VEX_W_1_0F46_P_2_LEN_1
,
834 MOD_VEX_W_0_0F47_P_0_LEN_1
,
835 MOD_VEX_W_1_0F47_P_0_LEN_1
,
836 MOD_VEX_W_0_0F47_P_2_LEN_1
,
837 MOD_VEX_W_1_0F47_P_2_LEN_1
,
838 MOD_VEX_W_0_0F4A_P_0_LEN_1
,
839 MOD_VEX_W_1_0F4A_P_0_LEN_1
,
840 MOD_VEX_W_0_0F4A_P_2_LEN_1
,
841 MOD_VEX_W_1_0F4A_P_2_LEN_1
,
842 MOD_VEX_W_0_0F4B_P_0_LEN_1
,
843 MOD_VEX_W_1_0F4B_P_0_LEN_1
,
844 MOD_VEX_W_0_0F4B_P_2_LEN_1
,
856 MOD_VEX_W_0_0F91_P_0_LEN_0
,
857 MOD_VEX_W_1_0F91_P_0_LEN_0
,
858 MOD_VEX_W_0_0F91_P_2_LEN_0
,
859 MOD_VEX_W_1_0F91_P_2_LEN_0
,
860 MOD_VEX_W_0_0F92_P_0_LEN_0
,
861 MOD_VEX_W_0_0F92_P_2_LEN_0
,
862 MOD_VEX_0F92_P_3_LEN_0
,
863 MOD_VEX_W_0_0F93_P_0_LEN_0
,
864 MOD_VEX_W_0_0F93_P_2_LEN_0
,
865 MOD_VEX_0F93_P_3_LEN_0
,
866 MOD_VEX_W_0_0F98_P_0_LEN_0
,
867 MOD_VEX_W_1_0F98_P_0_LEN_0
,
868 MOD_VEX_W_0_0F98_P_2_LEN_0
,
869 MOD_VEX_W_1_0F98_P_2_LEN_0
,
870 MOD_VEX_W_0_0F99_P_0_LEN_0
,
871 MOD_VEX_W_1_0F99_P_0_LEN_0
,
872 MOD_VEX_W_0_0F99_P_2_LEN_0
,
873 MOD_VEX_W_1_0F99_P_2_LEN_0
,
878 MOD_VEX_0FF0_PREFIX_3
,
885 MOD_VEX_0F3849_X86_64_P_0_W_0
,
886 MOD_VEX_0F3849_X86_64_P_2_W_0
,
887 MOD_VEX_0F3849_X86_64_P_3_W_0
,
888 MOD_VEX_0F384B_X86_64_P_1_W_0
,
889 MOD_VEX_0F384B_X86_64_P_2_W_0
,
890 MOD_VEX_0F384B_X86_64_P_3_W_0
,
892 MOD_VEX_0F385C_X86_64_P_1_W_0
,
893 MOD_VEX_0F385E_X86_64_P_0_W_0
,
894 MOD_VEX_0F385E_X86_64_P_1_W_0
,
895 MOD_VEX_0F385E_X86_64_P_2_W_0
,
896 MOD_VEX_0F385E_X86_64_P_3_W_0
,
906 MOD_EVEX_0F12_PREFIX_0
,
907 MOD_EVEX_0F12_PREFIX_2
,
909 MOD_EVEX_0F16_PREFIX_0
,
910 MOD_EVEX_0F16_PREFIX_2
,
918 MOD_EVEX_0F382A_P_1_W_1
,
920 MOD_EVEX_0F383A_P_1_W_0
,
928 MOD_EVEX_0F38C6_REG_1
,
929 MOD_EVEX_0F38C6_REG_2
,
930 MOD_EVEX_0F38C6_REG_5
,
931 MOD_EVEX_0F38C6_REG_6
,
932 MOD_EVEX_0F38C7_REG_1
,
933 MOD_EVEX_0F38C7_REG_2
,
934 MOD_EVEX_0F38C7_REG_5
,
935 MOD_EVEX_0F38C7_REG_6
948 RM_0F1E_P_1_MOD_3_REG_7
,
949 RM_0F3A0F_P_1_MOD_3_REG_0
,
950 RM_0FAE_REG_6_MOD_3_P_0
,
952 RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0
958 PREFIX_0F01_REG_1_RM_4
,
959 PREFIX_0F01_REG_1_RM_5
,
960 PREFIX_0F01_REG_1_RM_6
,
961 PREFIX_0F01_REG_1_RM_7
,
962 PREFIX_0F01_REG_3_RM_1
,
963 PREFIX_0F01_REG_5_MOD_0
,
964 PREFIX_0F01_REG_5_MOD_3_RM_0
,
965 PREFIX_0F01_REG_5_MOD_3_RM_1
,
966 PREFIX_0F01_REG_5_MOD_3_RM_2
,
967 PREFIX_0F01_REG_5_MOD_3_RM_4
,
968 PREFIX_0F01_REG_5_MOD_3_RM_5
,
969 PREFIX_0F01_REG_5_MOD_3_RM_6
,
970 PREFIX_0F01_REG_5_MOD_3_RM_7
,
971 PREFIX_0F01_REG_7_MOD_3_RM_2
,
972 PREFIX_0F01_REG_7_MOD_3_RM_6
,
973 PREFIX_0F01_REG_7_MOD_3_RM_7
,
1011 PREFIX_0FAE_REG_0_MOD_3
,
1012 PREFIX_0FAE_REG_1_MOD_3
,
1013 PREFIX_0FAE_REG_2_MOD_3
,
1014 PREFIX_0FAE_REG_3_MOD_3
,
1015 PREFIX_0FAE_REG_4_MOD_0
,
1016 PREFIX_0FAE_REG_4_MOD_3
,
1017 PREFIX_0FAE_REG_5_MOD_3
,
1018 PREFIX_0FAE_REG_6_MOD_0
,
1019 PREFIX_0FAE_REG_6_MOD_3
,
1020 PREFIX_0FAE_REG_7_MOD_0
,
1025 PREFIX_0FC7_REG_6_MOD_0
,
1026 PREFIX_0FC7_REG_6_MOD_3
,
1027 PREFIX_0FC7_REG_7_MOD_3
,
1090 PREFIX_VEX_0F3849_X86_64
,
1091 PREFIX_VEX_0F384B_X86_64
,
1092 PREFIX_VEX_0F385C_X86_64
,
1093 PREFIX_VEX_0F385E_X86_64
,
1192 X86_64_0F01_REG_1_RM_5_PREFIX_2
,
1193 X86_64_0F01_REG_1_RM_6_PREFIX_2
,
1194 X86_64_0F01_REG_1_RM_7_PREFIX_2
,
1203 X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1
,
1204 X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1
,
1205 X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1
,
1206 X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1
,
1207 X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1
,
1208 X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3
,
1209 X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1
,
1210 X86_64_0FC7_REG_6_MOD_3_PREFIX_1
1215 THREE_BYTE_0F38
= 0,
1242 VEX_LEN_0F12_P_0_M_0
= 0,
1243 VEX_LEN_0F12_P_0_M_1
,
1244 #define VEX_LEN_0F12_P_2_M_0 VEX_LEN_0F12_P_0_M_0
1246 VEX_LEN_0F16_P_0_M_0
,
1247 VEX_LEN_0F16_P_0_M_1
,
1248 #define VEX_LEN_0F16_P_2_M_0 VEX_LEN_0F16_P_0_M_0
1284 VEX_LEN_0FAE_R_2_M_0
,
1285 VEX_LEN_0FAE_R_3_M_0
,
1295 VEX_LEN_0F3849_X86_64_P_0_W_0_M_0
,
1296 VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0
,
1297 VEX_LEN_0F3849_X86_64_P_2_W_0_M_0
,
1298 VEX_LEN_0F3849_X86_64_P_3_W_0_M_0
,
1299 VEX_LEN_0F384B_X86_64_P_1_W_0_M_0
,
1300 VEX_LEN_0F384B_X86_64_P_2_W_0_M_0
,
1301 VEX_LEN_0F384B_X86_64_P_3_W_0_M_0
,
1303 VEX_LEN_0F385C_X86_64_P_1_W_0_M_0
,
1304 VEX_LEN_0F385E_X86_64_P_0_W_0_M_0
,
1305 VEX_LEN_0F385E_X86_64_P_1_W_0_M_0
,
1306 VEX_LEN_0F385E_X86_64_P_2_W_0_M_0
,
1307 VEX_LEN_0F385E_X86_64_P_3_W_0_M_0
,
1347 VEX_LEN_0FXOP_08_85
,
1348 VEX_LEN_0FXOP_08_86
,
1349 VEX_LEN_0FXOP_08_87
,
1350 VEX_LEN_0FXOP_08_8E
,
1351 VEX_LEN_0FXOP_08_8F
,
1352 VEX_LEN_0FXOP_08_95
,
1353 VEX_LEN_0FXOP_08_96
,
1354 VEX_LEN_0FXOP_08_97
,
1355 VEX_LEN_0FXOP_08_9E
,
1356 VEX_LEN_0FXOP_08_9F
,
1357 VEX_LEN_0FXOP_08_A3
,
1358 VEX_LEN_0FXOP_08_A6
,
1359 VEX_LEN_0FXOP_08_B6
,
1360 VEX_LEN_0FXOP_08_C0
,
1361 VEX_LEN_0FXOP_08_C1
,
1362 VEX_LEN_0FXOP_08_C2
,
1363 VEX_LEN_0FXOP_08_C3
,
1364 VEX_LEN_0FXOP_08_CC
,
1365 VEX_LEN_0FXOP_08_CD
,
1366 VEX_LEN_0FXOP_08_CE
,
1367 VEX_LEN_0FXOP_08_CF
,
1368 VEX_LEN_0FXOP_08_EC
,
1369 VEX_LEN_0FXOP_08_ED
,
1370 VEX_LEN_0FXOP_08_EE
,
1371 VEX_LEN_0FXOP_08_EF
,
1372 VEX_LEN_0FXOP_09_01
,
1373 VEX_LEN_0FXOP_09_02
,
1374 VEX_LEN_0FXOP_09_12_M_1
,
1375 VEX_LEN_0FXOP_09_82_W_0
,
1376 VEX_LEN_0FXOP_09_83_W_0
,
1377 VEX_LEN_0FXOP_09_90
,
1378 VEX_LEN_0FXOP_09_91
,
1379 VEX_LEN_0FXOP_09_92
,
1380 VEX_LEN_0FXOP_09_93
,
1381 VEX_LEN_0FXOP_09_94
,
1382 VEX_LEN_0FXOP_09_95
,
1383 VEX_LEN_0FXOP_09_96
,
1384 VEX_LEN_0FXOP_09_97
,
1385 VEX_LEN_0FXOP_09_98
,
1386 VEX_LEN_0FXOP_09_99
,
1387 VEX_LEN_0FXOP_09_9A
,
1388 VEX_LEN_0FXOP_09_9B
,
1389 VEX_LEN_0FXOP_09_C1
,
1390 VEX_LEN_0FXOP_09_C2
,
1391 VEX_LEN_0FXOP_09_C3
,
1392 VEX_LEN_0FXOP_09_C6
,
1393 VEX_LEN_0FXOP_09_C7
,
1394 VEX_LEN_0FXOP_09_CB
,
1395 VEX_LEN_0FXOP_09_D1
,
1396 VEX_LEN_0FXOP_09_D2
,
1397 VEX_LEN_0FXOP_09_D3
,
1398 VEX_LEN_0FXOP_09_D6
,
1399 VEX_LEN_0FXOP_09_D7
,
1400 VEX_LEN_0FXOP_09_DB
,
1401 VEX_LEN_0FXOP_09_E1
,
1402 VEX_LEN_0FXOP_09_E2
,
1403 VEX_LEN_0FXOP_09_E3
,
1404 VEX_LEN_0FXOP_0A_12
,
1416 EVEX_LEN_0F3819_W_0
,
1417 EVEX_LEN_0F3819_W_1
,
1418 EVEX_LEN_0F381A_W_0_M_0
,
1419 EVEX_LEN_0F381A_W_1_M_0
,
1420 EVEX_LEN_0F381B_W_0_M_0
,
1421 EVEX_LEN_0F381B_W_1_M_0
,
1423 EVEX_LEN_0F385A_W_0_M_0
,
1424 EVEX_LEN_0F385A_W_1_M_0
,
1425 EVEX_LEN_0F385B_W_0_M_0
,
1426 EVEX_LEN_0F385B_W_1_M_0
,
1427 EVEX_LEN_0F38C6_R_1_M_0
,
1428 EVEX_LEN_0F38C6_R_2_M_0
,
1429 EVEX_LEN_0F38C6_R_5_M_0
,
1430 EVEX_LEN_0F38C6_R_6_M_0
,
1431 EVEX_LEN_0F38C7_R_1_M_0_W_0
,
1432 EVEX_LEN_0F38C7_R_1_M_0_W_1
,
1433 EVEX_LEN_0F38C7_R_2_M_0_W_0
,
1434 EVEX_LEN_0F38C7_R_2_M_0_W_1
,
1435 EVEX_LEN_0F38C7_R_5_M_0_W_0
,
1436 EVEX_LEN_0F38C7_R_5_M_0_W_1
,
1437 EVEX_LEN_0F38C7_R_6_M_0_W_0
,
1438 EVEX_LEN_0F38C7_R_6_M_0_W_1
,
1439 EVEX_LEN_0F3A00_W_1
,
1440 EVEX_LEN_0F3A01_W_1
,
1445 EVEX_LEN_0F3A18_W_0
,
1446 EVEX_LEN_0F3A18_W_1
,
1447 EVEX_LEN_0F3A19_W_0
,
1448 EVEX_LEN_0F3A19_W_1
,
1449 EVEX_LEN_0F3A1A_W_0
,
1450 EVEX_LEN_0F3A1A_W_1
,
1451 EVEX_LEN_0F3A1B_W_0
,
1452 EVEX_LEN_0F3A1B_W_1
,
1454 EVEX_LEN_0F3A21_W_0
,
1456 EVEX_LEN_0F3A23_W_0
,
1457 EVEX_LEN_0F3A23_W_1
,
1458 EVEX_LEN_0F3A38_W_0
,
1459 EVEX_LEN_0F3A38_W_1
,
1460 EVEX_LEN_0F3A39_W_0
,
1461 EVEX_LEN_0F3A39_W_1
,
1462 EVEX_LEN_0F3A3A_W_0
,
1463 EVEX_LEN_0F3A3A_W_1
,
1464 EVEX_LEN_0F3A3B_W_0
,
1465 EVEX_LEN_0F3A3B_W_1
,
1466 EVEX_LEN_0F3A43_W_0
,
1472 VEX_W_0F41_P_0_LEN_1
= 0,
1473 VEX_W_0F41_P_2_LEN_1
,
1474 VEX_W_0F42_P_0_LEN_1
,
1475 VEX_W_0F42_P_2_LEN_1
,
1476 VEX_W_0F44_P_0_LEN_0
,
1477 VEX_W_0F44_P_2_LEN_0
,
1478 VEX_W_0F45_P_0_LEN_1
,
1479 VEX_W_0F45_P_2_LEN_1
,
1480 VEX_W_0F46_P_0_LEN_1
,
1481 VEX_W_0F46_P_2_LEN_1
,
1482 VEX_W_0F47_P_0_LEN_1
,
1483 VEX_W_0F47_P_2_LEN_1
,
1484 VEX_W_0F4A_P_0_LEN_1
,
1485 VEX_W_0F4A_P_2_LEN_1
,
1486 VEX_W_0F4B_P_0_LEN_1
,
1487 VEX_W_0F4B_P_2_LEN_1
,
1488 VEX_W_0F90_P_0_LEN_0
,
1489 VEX_W_0F90_P_2_LEN_0
,
1490 VEX_W_0F91_P_0_LEN_0
,
1491 VEX_W_0F91_P_2_LEN_0
,
1492 VEX_W_0F92_P_0_LEN_0
,
1493 VEX_W_0F92_P_2_LEN_0
,
1494 VEX_W_0F93_P_0_LEN_0
,
1495 VEX_W_0F93_P_2_LEN_0
,
1496 VEX_W_0F98_P_0_LEN_0
,
1497 VEX_W_0F98_P_2_LEN_0
,
1498 VEX_W_0F99_P_0_LEN_0
,
1499 VEX_W_0F99_P_2_LEN_0
,
1508 VEX_W_0F381A_M_0_L_1
,
1515 VEX_W_0F3849_X86_64_P_0
,
1516 VEX_W_0F3849_X86_64_P_2
,
1517 VEX_W_0F3849_X86_64_P_3
,
1518 VEX_W_0F384B_X86_64_P_1
,
1519 VEX_W_0F384B_X86_64_P_2
,
1520 VEX_W_0F384B_X86_64_P_3
,
1527 VEX_W_0F385A_M_0_L_0
,
1528 VEX_W_0F385C_X86_64_P_1
,
1529 VEX_W_0F385E_X86_64_P_0
,
1530 VEX_W_0F385E_X86_64_P_1
,
1531 VEX_W_0F385E_X86_64_P_2
,
1532 VEX_W_0F385E_X86_64_P_3
,
1554 VEX_W_0FXOP_08_85_L_0
,
1555 VEX_W_0FXOP_08_86_L_0
,
1556 VEX_W_0FXOP_08_87_L_0
,
1557 VEX_W_0FXOP_08_8E_L_0
,
1558 VEX_W_0FXOP_08_8F_L_0
,
1559 VEX_W_0FXOP_08_95_L_0
,
1560 VEX_W_0FXOP_08_96_L_0
,
1561 VEX_W_0FXOP_08_97_L_0
,
1562 VEX_W_0FXOP_08_9E_L_0
,
1563 VEX_W_0FXOP_08_9F_L_0
,
1564 VEX_W_0FXOP_08_A6_L_0
,
1565 VEX_W_0FXOP_08_B6_L_0
,
1566 VEX_W_0FXOP_08_C0_L_0
,
1567 VEX_W_0FXOP_08_C1_L_0
,
1568 VEX_W_0FXOP_08_C2_L_0
,
1569 VEX_W_0FXOP_08_C3_L_0
,
1570 VEX_W_0FXOP_08_CC_L_0
,
1571 VEX_W_0FXOP_08_CD_L_0
,
1572 VEX_W_0FXOP_08_CE_L_0
,
1573 VEX_W_0FXOP_08_CF_L_0
,
1574 VEX_W_0FXOP_08_EC_L_0
,
1575 VEX_W_0FXOP_08_ED_L_0
,
1576 VEX_W_0FXOP_08_EE_L_0
,
1577 VEX_W_0FXOP_08_EF_L_0
,
1583 VEX_W_0FXOP_09_C1_L_0
,
1584 VEX_W_0FXOP_09_C2_L_0
,
1585 VEX_W_0FXOP_09_C3_L_0
,
1586 VEX_W_0FXOP_09_C6_L_0
,
1587 VEX_W_0FXOP_09_C7_L_0
,
1588 VEX_W_0FXOP_09_CB_L_0
,
1589 VEX_W_0FXOP_09_D1_L_0
,
1590 VEX_W_0FXOP_09_D2_L_0
,
1591 VEX_W_0FXOP_09_D3_L_0
,
1592 VEX_W_0FXOP_09_D6_L_0
,
1593 VEX_W_0FXOP_09_D7_L_0
,
1594 VEX_W_0FXOP_09_DB_L_0
,
1595 VEX_W_0FXOP_09_E1_L_0
,
1596 VEX_W_0FXOP_09_E2_L_0
,
1597 VEX_W_0FXOP_09_E3_L_0
,
1603 EVEX_W_0F12_P_0_M_1
,
1606 EVEX_W_0F16_P_0_M_1
,
1726 EVEX_W_0F38C7_R_1_M_0
,
1727 EVEX_W_0F38C7_R_2_M_0
,
1728 EVEX_W_0F38C7_R_5_M_0
,
1729 EVEX_W_0F38C7_R_6_M_0
,
1754 typedef void (*op_rtn
) (int bytemode
, int sizeflag
);
1763 unsigned int prefix_requirement
;
1766 /* Upper case letters in the instruction names here are macros.
1767 'A' => print 'b' if no register operands or suffix_always is true
1768 'B' => print 'b' if suffix_always is true
1769 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
1771 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
1772 suffix_always is true
1773 'E' => print 'e' if 32-bit form of jcxz
1774 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
1775 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
1776 'H' => print ",pt" or ",pn" branch hint
1779 'K' => print 'd' or 'q' if rex prefix is present.
1781 'M' => print 'r' if intel_mnemonic is false.
1782 'N' => print 'n' if instruction has no wait "prefix"
1783 'O' => print 'd' or 'o' (or 'q' in Intel mode)
1784 'P' => behave as 'T' except with register operand outside of suffix_always
1786 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
1788 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
1789 'S' => print 'w', 'l' or 'q' if suffix_always is true
1790 'T' => print 'w', 'l'/'d', or 'q' if instruction has an operand size
1791 prefix or if suffix_always is true.
1794 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
1795 'X' => print 's', 'd' depending on data16 prefix (for XMM)
1797 'Z' => print 'q' in 64bit mode and 'l' otherwise, if suffix_always is true.
1798 '!' => change condition from true to false or from false to true.
1799 '%' => add 1 upper case letter to the macro.
1800 '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size
1801 prefix or suffix_always is true (lcall/ljmp).
1802 '@' => in 64bit mode for Intel64 ISA or if instruction
1803 has no operand sizing prefix, print 'q' if suffix_always is true or
1804 nothing otherwise; behave as 'P' in all other cases
1806 2 upper case letter macros:
1807 "XY" => print 'x' or 'y' if suffix_always is true or no register
1808 operands and no broadcast.
1809 "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
1810 register operands and no broadcast.
1811 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
1812 "XV" => print "{vex3}" pseudo prefix
1813 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand, cond
1814 being false, or no operand at all in 64bit mode, or if suffix_always
1816 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
1817 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
1818 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
1819 "DQ" => print 'd' or 'q' depending on the VEX.W bit
1820 "BW" => print 'b' or 'w' depending on the VEX.W bit
1821 "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
1822 an operand size prefix, or suffix_always is true. print
1823 'q' if rex prefix is present.
1825 Many of the above letters print nothing in Intel mode. See "putop"
1828 Braces '{' and '}', and vertical bars '|', indicate alternative
1829 mnemonic strings for AT&T and Intel. */
1831 static const struct dis386 dis386
[] = {
1833 { "addB", { Ebh1
, Gb
}, 0 },
1834 { "addS", { Evh1
, Gv
}, 0 },
1835 { "addB", { Gb
, EbS
}, 0 },
1836 { "addS", { Gv
, EvS
}, 0 },
1837 { "addB", { AL
, Ib
}, 0 },
1838 { "addS", { eAX
, Iv
}, 0 },
1839 { X86_64_TABLE (X86_64_06
) },
1840 { X86_64_TABLE (X86_64_07
) },
1842 { "orB", { Ebh1
, Gb
}, 0 },
1843 { "orS", { Evh1
, Gv
}, 0 },
1844 { "orB", { Gb
, EbS
}, 0 },
1845 { "orS", { Gv
, EvS
}, 0 },
1846 { "orB", { AL
, Ib
}, 0 },
1847 { "orS", { eAX
, Iv
}, 0 },
1848 { X86_64_TABLE (X86_64_0E
) },
1849 { Bad_Opcode
}, /* 0x0f extended opcode escape */
1851 { "adcB", { Ebh1
, Gb
}, 0 },
1852 { "adcS", { Evh1
, Gv
}, 0 },
1853 { "adcB", { Gb
, EbS
}, 0 },
1854 { "adcS", { Gv
, EvS
}, 0 },
1855 { "adcB", { AL
, Ib
}, 0 },
1856 { "adcS", { eAX
, Iv
}, 0 },
1857 { X86_64_TABLE (X86_64_16
) },
1858 { X86_64_TABLE (X86_64_17
) },
1860 { "sbbB", { Ebh1
, Gb
}, 0 },
1861 { "sbbS", { Evh1
, Gv
}, 0 },
1862 { "sbbB", { Gb
, EbS
}, 0 },
1863 { "sbbS", { Gv
, EvS
}, 0 },
1864 { "sbbB", { AL
, Ib
}, 0 },
1865 { "sbbS", { eAX
, Iv
}, 0 },
1866 { X86_64_TABLE (X86_64_1E
) },
1867 { X86_64_TABLE (X86_64_1F
) },
1869 { "andB", { Ebh1
, Gb
}, 0 },
1870 { "andS", { Evh1
, Gv
}, 0 },
1871 { "andB", { Gb
, EbS
}, 0 },
1872 { "andS", { Gv
, EvS
}, 0 },
1873 { "andB", { AL
, Ib
}, 0 },
1874 { "andS", { eAX
, Iv
}, 0 },
1875 { Bad_Opcode
}, /* SEG ES prefix */
1876 { X86_64_TABLE (X86_64_27
) },
1878 { "subB", { Ebh1
, Gb
}, 0 },
1879 { "subS", { Evh1
, Gv
}, 0 },
1880 { "subB", { Gb
, EbS
}, 0 },
1881 { "subS", { Gv
, EvS
}, 0 },
1882 { "subB", { AL
, Ib
}, 0 },
1883 { "subS", { eAX
, Iv
}, 0 },
1884 { Bad_Opcode
}, /* SEG CS prefix */
1885 { X86_64_TABLE (X86_64_2F
) },
1887 { "xorB", { Ebh1
, Gb
}, 0 },
1888 { "xorS", { Evh1
, Gv
}, 0 },
1889 { "xorB", { Gb
, EbS
}, 0 },
1890 { "xorS", { Gv
, EvS
}, 0 },
1891 { "xorB", { AL
, Ib
}, 0 },
1892 { "xorS", { eAX
, Iv
}, 0 },
1893 { Bad_Opcode
}, /* SEG SS prefix */
1894 { X86_64_TABLE (X86_64_37
) },
1896 { "cmpB", { Eb
, Gb
}, 0 },
1897 { "cmpS", { Ev
, Gv
}, 0 },
1898 { "cmpB", { Gb
, EbS
}, 0 },
1899 { "cmpS", { Gv
, EvS
}, 0 },
1900 { "cmpB", { AL
, Ib
}, 0 },
1901 { "cmpS", { eAX
, Iv
}, 0 },
1902 { Bad_Opcode
}, /* SEG DS prefix */
1903 { X86_64_TABLE (X86_64_3F
) },
1905 { "inc{S|}", { RMeAX
}, 0 },
1906 { "inc{S|}", { RMeCX
}, 0 },
1907 { "inc{S|}", { RMeDX
}, 0 },
1908 { "inc{S|}", { RMeBX
}, 0 },
1909 { "inc{S|}", { RMeSP
}, 0 },
1910 { "inc{S|}", { RMeBP
}, 0 },
1911 { "inc{S|}", { RMeSI
}, 0 },
1912 { "inc{S|}", { RMeDI
}, 0 },
1914 { "dec{S|}", { RMeAX
}, 0 },
1915 { "dec{S|}", { RMeCX
}, 0 },
1916 { "dec{S|}", { RMeDX
}, 0 },
1917 { "dec{S|}", { RMeBX
}, 0 },
1918 { "dec{S|}", { RMeSP
}, 0 },
1919 { "dec{S|}", { RMeBP
}, 0 },
1920 { "dec{S|}", { RMeSI
}, 0 },
1921 { "dec{S|}", { RMeDI
}, 0 },
1923 { "push{!P|}", { RMrAX
}, 0 },
1924 { "push{!P|}", { RMrCX
}, 0 },
1925 { "push{!P|}", { RMrDX
}, 0 },
1926 { "push{!P|}", { RMrBX
}, 0 },
1927 { "push{!P|}", { RMrSP
}, 0 },
1928 { "push{!P|}", { RMrBP
}, 0 },
1929 { "push{!P|}", { RMrSI
}, 0 },
1930 { "push{!P|}", { RMrDI
}, 0 },
1932 { "pop{!P|}", { RMrAX
}, 0 },
1933 { "pop{!P|}", { RMrCX
}, 0 },
1934 { "pop{!P|}", { RMrDX
}, 0 },
1935 { "pop{!P|}", { RMrBX
}, 0 },
1936 { "pop{!P|}", { RMrSP
}, 0 },
1937 { "pop{!P|}", { RMrBP
}, 0 },
1938 { "pop{!P|}", { RMrSI
}, 0 },
1939 { "pop{!P|}", { RMrDI
}, 0 },
1941 { X86_64_TABLE (X86_64_60
) },
1942 { X86_64_TABLE (X86_64_61
) },
1943 { X86_64_TABLE (X86_64_62
) },
1944 { X86_64_TABLE (X86_64_63
) },
1945 { Bad_Opcode
}, /* seg fs */
1946 { Bad_Opcode
}, /* seg gs */
1947 { Bad_Opcode
}, /* op size prefix */
1948 { Bad_Opcode
}, /* adr size prefix */
1950 { "pushP", { sIv
}, 0 },
1951 { "imulS", { Gv
, Ev
, Iv
}, 0 },
1952 { "pushP", { sIbT
}, 0 },
1953 { "imulS", { Gv
, Ev
, sIb
}, 0 },
1954 { "ins{b|}", { Ybr
, indirDX
}, 0 },
1955 { X86_64_TABLE (X86_64_6D
) },
1956 { "outs{b|}", { indirDXr
, Xb
}, 0 },
1957 { X86_64_TABLE (X86_64_6F
) },
1959 { "joH", { Jb
, BND
, cond_jump_flag
}, 0 },
1960 { "jnoH", { Jb
, BND
, cond_jump_flag
}, 0 },
1961 { "jbH", { Jb
, BND
, cond_jump_flag
}, 0 },
1962 { "jaeH", { Jb
, BND
, cond_jump_flag
}, 0 },
1963 { "jeH", { Jb
, BND
, cond_jump_flag
}, 0 },
1964 { "jneH", { Jb
, BND
, cond_jump_flag
}, 0 },
1965 { "jbeH", { Jb
, BND
, cond_jump_flag
}, 0 },
1966 { "jaH", { Jb
, BND
, cond_jump_flag
}, 0 },
1968 { "jsH", { Jb
, BND
, cond_jump_flag
}, 0 },
1969 { "jnsH", { Jb
, BND
, cond_jump_flag
}, 0 },
1970 { "jpH", { Jb
, BND
, cond_jump_flag
}, 0 },
1971 { "jnpH", { Jb
, BND
, cond_jump_flag
}, 0 },
1972 { "jlH", { Jb
, BND
, cond_jump_flag
}, 0 },
1973 { "jgeH", { Jb
, BND
, cond_jump_flag
}, 0 },
1974 { "jleH", { Jb
, BND
, cond_jump_flag
}, 0 },
1975 { "jgH", { Jb
, BND
, cond_jump_flag
}, 0 },
1977 { REG_TABLE (REG_80
) },
1978 { REG_TABLE (REG_81
) },
1979 { X86_64_TABLE (X86_64_82
) },
1980 { REG_TABLE (REG_83
) },
1981 { "testB", { Eb
, Gb
}, 0 },
1982 { "testS", { Ev
, Gv
}, 0 },
1983 { "xchgB", { Ebh2
, Gb
}, 0 },
1984 { "xchgS", { Evh2
, Gv
}, 0 },
1986 { "movB", { Ebh3
, Gb
}, 0 },
1987 { "movS", { Evh3
, Gv
}, 0 },
1988 { "movB", { Gb
, EbS
}, 0 },
1989 { "movS", { Gv
, EvS
}, 0 },
1990 { "movD", { Sv
, Sw
}, 0 },
1991 { MOD_TABLE (MOD_8D
) },
1992 { "movD", { Sw
, Sv
}, 0 },
1993 { REG_TABLE (REG_8F
) },
1995 { PREFIX_TABLE (PREFIX_90
) },
1996 { "xchgS", { RMeCX
, eAX
}, 0 },
1997 { "xchgS", { RMeDX
, eAX
}, 0 },
1998 { "xchgS", { RMeBX
, eAX
}, 0 },
1999 { "xchgS", { RMeSP
, eAX
}, 0 },
2000 { "xchgS", { RMeBP
, eAX
}, 0 },
2001 { "xchgS", { RMeSI
, eAX
}, 0 },
2002 { "xchgS", { RMeDI
, eAX
}, 0 },
2004 { "cW{t|}R", { XX
}, 0 },
2005 { "cR{t|}O", { XX
}, 0 },
2006 { X86_64_TABLE (X86_64_9A
) },
2007 { Bad_Opcode
}, /* fwait */
2008 { "pushfP", { XX
}, 0 },
2009 { "popfP", { XX
}, 0 },
2010 { "sahf", { XX
}, 0 },
2011 { "lahf", { XX
}, 0 },
2013 { "mov%LB", { AL
, Ob
}, 0 },
2014 { "mov%LS", { eAX
, Ov
}, 0 },
2015 { "mov%LB", { Ob
, AL
}, 0 },
2016 { "mov%LS", { Ov
, eAX
}, 0 },
2017 { "movs{b|}", { Ybr
, Xb
}, 0 },
2018 { "movs{R|}", { Yvr
, Xv
}, 0 },
2019 { "cmps{b|}", { Xb
, Yb
}, 0 },
2020 { "cmps{R|}", { Xv
, Yv
}, 0 },
2022 { "testB", { AL
, Ib
}, 0 },
2023 { "testS", { eAX
, Iv
}, 0 },
2024 { "stosB", { Ybr
, AL
}, 0 },
2025 { "stosS", { Yvr
, eAX
}, 0 },
2026 { "lodsB", { ALr
, Xb
}, 0 },
2027 { "lodsS", { eAXr
, Xv
}, 0 },
2028 { "scasB", { AL
, Yb
}, 0 },
2029 { "scasS", { eAX
, Yv
}, 0 },
2031 { "movB", { RMAL
, Ib
}, 0 },
2032 { "movB", { RMCL
, Ib
}, 0 },
2033 { "movB", { RMDL
, Ib
}, 0 },
2034 { "movB", { RMBL
, Ib
}, 0 },
2035 { "movB", { RMAH
, Ib
}, 0 },
2036 { "movB", { RMCH
, Ib
}, 0 },
2037 { "movB", { RMDH
, Ib
}, 0 },
2038 { "movB", { RMBH
, Ib
}, 0 },
2040 { "mov%LV", { RMeAX
, Iv64
}, 0 },
2041 { "mov%LV", { RMeCX
, Iv64
}, 0 },
2042 { "mov%LV", { RMeDX
, Iv64
}, 0 },
2043 { "mov%LV", { RMeBX
, Iv64
}, 0 },
2044 { "mov%LV", { RMeSP
, Iv64
}, 0 },
2045 { "mov%LV", { RMeBP
, Iv64
}, 0 },
2046 { "mov%LV", { RMeSI
, Iv64
}, 0 },
2047 { "mov%LV", { RMeDI
, Iv64
}, 0 },
2049 { REG_TABLE (REG_C0
) },
2050 { REG_TABLE (REG_C1
) },
2051 { X86_64_TABLE (X86_64_C2
) },
2052 { X86_64_TABLE (X86_64_C3
) },
2053 { X86_64_TABLE (X86_64_C4
) },
2054 { X86_64_TABLE (X86_64_C5
) },
2055 { REG_TABLE (REG_C6
) },
2056 { REG_TABLE (REG_C7
) },
2058 { "enterP", { Iw
, Ib
}, 0 },
2059 { "leaveP", { XX
}, 0 },
2060 { "{l|}ret{|f}%LP", { Iw
}, 0 },
2061 { "{l|}ret{|f}%LP", { XX
}, 0 },
2062 { "int3", { XX
}, 0 },
2063 { "int", { Ib
}, 0 },
2064 { X86_64_TABLE (X86_64_CE
) },
2065 { "iret%LP", { XX
}, 0 },
2067 { REG_TABLE (REG_D0
) },
2068 { REG_TABLE (REG_D1
) },
2069 { REG_TABLE (REG_D2
) },
2070 { REG_TABLE (REG_D3
) },
2071 { X86_64_TABLE (X86_64_D4
) },
2072 { X86_64_TABLE (X86_64_D5
) },
2074 { "xlat", { DSBX
}, 0 },
2085 { "loopneFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2086 { "loopeFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2087 { "loopFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2088 { "jEcxzH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2089 { "inB", { AL
, Ib
}, 0 },
2090 { "inG", { zAX
, Ib
}, 0 },
2091 { "outB", { Ib
, AL
}, 0 },
2092 { "outG", { Ib
, zAX
}, 0 },
2094 { X86_64_TABLE (X86_64_E8
) },
2095 { X86_64_TABLE (X86_64_E9
) },
2096 { X86_64_TABLE (X86_64_EA
) },
2097 { "jmp", { Jb
, BND
}, 0 },
2098 { "inB", { AL
, indirDX
}, 0 },
2099 { "inG", { zAX
, indirDX
}, 0 },
2100 { "outB", { indirDX
, AL
}, 0 },
2101 { "outG", { indirDX
, zAX
}, 0 },
2103 { Bad_Opcode
}, /* lock prefix */
2104 { "icebp", { XX
}, 0 },
2105 { Bad_Opcode
}, /* repne */
2106 { Bad_Opcode
}, /* repz */
2107 { "hlt", { XX
}, 0 },
2108 { "cmc", { XX
}, 0 },
2109 { REG_TABLE (REG_F6
) },
2110 { REG_TABLE (REG_F7
) },
2112 { "clc", { XX
}, 0 },
2113 { "stc", { XX
}, 0 },
2114 { "cli", { XX
}, 0 },
2115 { "sti", { XX
}, 0 },
2116 { "cld", { XX
}, 0 },
2117 { "std", { XX
}, 0 },
2118 { REG_TABLE (REG_FE
) },
2119 { REG_TABLE (REG_FF
) },
2122 static const struct dis386 dis386_twobyte
[] = {
2124 { REG_TABLE (REG_0F00
) },
2125 { REG_TABLE (REG_0F01
) },
2126 { "larS", { Gv
, Ew
}, 0 },
2127 { "lslS", { Gv
, Ew
}, 0 },
2129 { "syscall", { XX
}, 0 },
2130 { "clts", { XX
}, 0 },
2131 { "sysret%LQ", { XX
}, 0 },
2133 { "invd", { XX
}, 0 },
2134 { PREFIX_TABLE (PREFIX_0F09
) },
2136 { "ud2", { XX
}, 0 },
2138 { REG_TABLE (REG_0F0D
) },
2139 { "femms", { XX
}, 0 },
2140 { "", { MX
, EM
, OPSUF
}, 0 }, /* See OP_3DNowSuffix. */
2142 { PREFIX_TABLE (PREFIX_0F10
) },
2143 { PREFIX_TABLE (PREFIX_0F11
) },
2144 { PREFIX_TABLE (PREFIX_0F12
) },
2145 { MOD_TABLE (MOD_0F13
) },
2146 { "unpcklpX", { XM
, EXx
}, PREFIX_OPCODE
},
2147 { "unpckhpX", { XM
, EXx
}, PREFIX_OPCODE
},
2148 { PREFIX_TABLE (PREFIX_0F16
) },
2149 { MOD_TABLE (MOD_0F17
) },
2151 { REG_TABLE (REG_0F18
) },
2152 { "nopQ", { Ev
}, 0 },
2153 { PREFIX_TABLE (PREFIX_0F1A
) },
2154 { PREFIX_TABLE (PREFIX_0F1B
) },
2155 { PREFIX_TABLE (PREFIX_0F1C
) },
2156 { "nopQ", { Ev
}, 0 },
2157 { PREFIX_TABLE (PREFIX_0F1E
) },
2158 { "nopQ", { Ev
}, 0 },
2160 { "movZ", { Em
, Cm
}, 0 },
2161 { "movZ", { Em
, Dm
}, 0 },
2162 { "movZ", { Cm
, Em
}, 0 },
2163 { "movZ", { Dm
, Em
}, 0 },
2164 { X86_64_TABLE (X86_64_0F24
) },
2166 { X86_64_TABLE (X86_64_0F26
) },
2169 { "movapX", { XM
, EXx
}, PREFIX_OPCODE
},
2170 { "movapX", { EXxS
, XM
}, PREFIX_OPCODE
},
2171 { PREFIX_TABLE (PREFIX_0F2A
) },
2172 { PREFIX_TABLE (PREFIX_0F2B
) },
2173 { PREFIX_TABLE (PREFIX_0F2C
) },
2174 { PREFIX_TABLE (PREFIX_0F2D
) },
2175 { PREFIX_TABLE (PREFIX_0F2E
) },
2176 { PREFIX_TABLE (PREFIX_0F2F
) },
2178 { "wrmsr", { XX
}, 0 },
2179 { "rdtsc", { XX
}, 0 },
2180 { "rdmsr", { XX
}, 0 },
2181 { "rdpmc", { XX
}, 0 },
2182 { "sysenter", { SEP
}, 0 },
2183 { "sysexit%LQ", { SEP
}, 0 },
2185 { "getsec", { XX
}, 0 },
2187 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38
, PREFIX_OPCODE
) },
2189 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A
, PREFIX_OPCODE
) },
2196 { "cmovoS", { Gv
, Ev
}, 0 },
2197 { "cmovnoS", { Gv
, Ev
}, 0 },
2198 { "cmovbS", { Gv
, Ev
}, 0 },
2199 { "cmovaeS", { Gv
, Ev
}, 0 },
2200 { "cmoveS", { Gv
, Ev
}, 0 },
2201 { "cmovneS", { Gv
, Ev
}, 0 },
2202 { "cmovbeS", { Gv
, Ev
}, 0 },
2203 { "cmovaS", { Gv
, Ev
}, 0 },
2205 { "cmovsS", { Gv
, Ev
}, 0 },
2206 { "cmovnsS", { Gv
, Ev
}, 0 },
2207 { "cmovpS", { Gv
, Ev
}, 0 },
2208 { "cmovnpS", { Gv
, Ev
}, 0 },
2209 { "cmovlS", { Gv
, Ev
}, 0 },
2210 { "cmovgeS", { Gv
, Ev
}, 0 },
2211 { "cmovleS", { Gv
, Ev
}, 0 },
2212 { "cmovgS", { Gv
, Ev
}, 0 },
2214 { MOD_TABLE (MOD_0F50
) },
2215 { PREFIX_TABLE (PREFIX_0F51
) },
2216 { PREFIX_TABLE (PREFIX_0F52
) },
2217 { PREFIX_TABLE (PREFIX_0F53
) },
2218 { "andpX", { XM
, EXx
}, PREFIX_OPCODE
},
2219 { "andnpX", { XM
, EXx
}, PREFIX_OPCODE
},
2220 { "orpX", { XM
, EXx
}, PREFIX_OPCODE
},
2221 { "xorpX", { XM
, EXx
}, PREFIX_OPCODE
},
2223 { PREFIX_TABLE (PREFIX_0F58
) },
2224 { PREFIX_TABLE (PREFIX_0F59
) },
2225 { PREFIX_TABLE (PREFIX_0F5A
) },
2226 { PREFIX_TABLE (PREFIX_0F5B
) },
2227 { PREFIX_TABLE (PREFIX_0F5C
) },
2228 { PREFIX_TABLE (PREFIX_0F5D
) },
2229 { PREFIX_TABLE (PREFIX_0F5E
) },
2230 { PREFIX_TABLE (PREFIX_0F5F
) },
2232 { PREFIX_TABLE (PREFIX_0F60
) },
2233 { PREFIX_TABLE (PREFIX_0F61
) },
2234 { PREFIX_TABLE (PREFIX_0F62
) },
2235 { "packsswb", { MX
, EM
}, PREFIX_OPCODE
},
2236 { "pcmpgtb", { MX
, EM
}, PREFIX_OPCODE
},
2237 { "pcmpgtw", { MX
, EM
}, PREFIX_OPCODE
},
2238 { "pcmpgtd", { MX
, EM
}, PREFIX_OPCODE
},
2239 { "packuswb", { MX
, EM
}, PREFIX_OPCODE
},
2241 { "punpckhbw", { MX
, EM
}, PREFIX_OPCODE
},
2242 { "punpckhwd", { MX
, EM
}, PREFIX_OPCODE
},
2243 { "punpckhdq", { MX
, EM
}, PREFIX_OPCODE
},
2244 { "packssdw", { MX
, EM
}, PREFIX_OPCODE
},
2245 { "punpcklqdq", { XM
, EXx
}, PREFIX_DATA
},
2246 { "punpckhqdq", { XM
, EXx
}, PREFIX_DATA
},
2247 { "movK", { MX
, Edq
}, PREFIX_OPCODE
},
2248 { PREFIX_TABLE (PREFIX_0F6F
) },
2250 { PREFIX_TABLE (PREFIX_0F70
) },
2251 { REG_TABLE (REG_0F71
) },
2252 { REG_TABLE (REG_0F72
) },
2253 { REG_TABLE (REG_0F73
) },
2254 { "pcmpeqb", { MX
, EM
}, PREFIX_OPCODE
},
2255 { "pcmpeqw", { MX
, EM
}, PREFIX_OPCODE
},
2256 { "pcmpeqd", { MX
, EM
}, PREFIX_OPCODE
},
2257 { "emms", { XX
}, PREFIX_OPCODE
},
2259 { PREFIX_TABLE (PREFIX_0F78
) },
2260 { PREFIX_TABLE (PREFIX_0F79
) },
2263 { PREFIX_TABLE (PREFIX_0F7C
) },
2264 { PREFIX_TABLE (PREFIX_0F7D
) },
2265 { PREFIX_TABLE (PREFIX_0F7E
) },
2266 { PREFIX_TABLE (PREFIX_0F7F
) },
2268 { "joH", { Jv
, BND
, cond_jump_flag
}, 0 },
2269 { "jnoH", { Jv
, BND
, cond_jump_flag
}, 0 },
2270 { "jbH", { Jv
, BND
, cond_jump_flag
}, 0 },
2271 { "jaeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2272 { "jeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2273 { "jneH", { Jv
, BND
, cond_jump_flag
}, 0 },
2274 { "jbeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2275 { "jaH", { Jv
, BND
, cond_jump_flag
}, 0 },
2277 { "jsH", { Jv
, BND
, cond_jump_flag
}, 0 },
2278 { "jnsH", { Jv
, BND
, cond_jump_flag
}, 0 },
2279 { "jpH", { Jv
, BND
, cond_jump_flag
}, 0 },
2280 { "jnpH", { Jv
, BND
, cond_jump_flag
}, 0 },
2281 { "jlH", { Jv
, BND
, cond_jump_flag
}, 0 },
2282 { "jgeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2283 { "jleH", { Jv
, BND
, cond_jump_flag
}, 0 },
2284 { "jgH", { Jv
, BND
, cond_jump_flag
}, 0 },
2286 { "seto", { Eb
}, 0 },
2287 { "setno", { Eb
}, 0 },
2288 { "setb", { Eb
}, 0 },
2289 { "setae", { Eb
}, 0 },
2290 { "sete", { Eb
}, 0 },
2291 { "setne", { Eb
}, 0 },
2292 { "setbe", { Eb
}, 0 },
2293 { "seta", { Eb
}, 0 },
2295 { "sets", { Eb
}, 0 },
2296 { "setns", { Eb
}, 0 },
2297 { "setp", { Eb
}, 0 },
2298 { "setnp", { Eb
}, 0 },
2299 { "setl", { Eb
}, 0 },
2300 { "setge", { Eb
}, 0 },
2301 { "setle", { Eb
}, 0 },
2302 { "setg", { Eb
}, 0 },
2304 { "pushP", { fs
}, 0 },
2305 { "popP", { fs
}, 0 },
2306 { "cpuid", { XX
}, 0 },
2307 { "btS", { Ev
, Gv
}, 0 },
2308 { "shldS", { Ev
, Gv
, Ib
}, 0 },
2309 { "shldS", { Ev
, Gv
, CL
}, 0 },
2310 { REG_TABLE (REG_0FA6
) },
2311 { REG_TABLE (REG_0FA7
) },
2313 { "pushP", { gs
}, 0 },
2314 { "popP", { gs
}, 0 },
2315 { "rsm", { XX
}, 0 },
2316 { "btsS", { Evh1
, Gv
}, 0 },
2317 { "shrdS", { Ev
, Gv
, Ib
}, 0 },
2318 { "shrdS", { Ev
, Gv
, CL
}, 0 },
2319 { REG_TABLE (REG_0FAE
) },
2320 { "imulS", { Gv
, Ev
}, 0 },
2322 { "cmpxchgB", { Ebh1
, Gb
}, 0 },
2323 { "cmpxchgS", { Evh1
, Gv
}, 0 },
2324 { MOD_TABLE (MOD_0FB2
) },
2325 { "btrS", { Evh1
, Gv
}, 0 },
2326 { MOD_TABLE (MOD_0FB4
) },
2327 { MOD_TABLE (MOD_0FB5
) },
2328 { "movz{bR|x}", { Gv
, Eb
}, 0 },
2329 { "movz{wR|x}", { Gv
, Ew
}, 0 }, /* yes, there really is movzww ! */
2331 { PREFIX_TABLE (PREFIX_0FB8
) },
2332 { "ud1S", { Gv
, Ev
}, 0 },
2333 { REG_TABLE (REG_0FBA
) },
2334 { "btcS", { Evh1
, Gv
}, 0 },
2335 { PREFIX_TABLE (PREFIX_0FBC
) },
2336 { PREFIX_TABLE (PREFIX_0FBD
) },
2337 { "movs{bR|x}", { Gv
, Eb
}, 0 },
2338 { "movs{wR|x}", { Gv
, Ew
}, 0 }, /* yes, there really is movsww ! */
2340 { "xaddB", { Ebh1
, Gb
}, 0 },
2341 { "xaddS", { Evh1
, Gv
}, 0 },
2342 { PREFIX_TABLE (PREFIX_0FC2
) },
2343 { MOD_TABLE (MOD_0FC3
) },
2344 { "pinsrw", { MX
, Edqw
, Ib
}, PREFIX_OPCODE
},
2345 { "pextrw", { Gdq
, MS
, Ib
}, PREFIX_OPCODE
},
2346 { "shufpX", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
2347 { REG_TABLE (REG_0FC7
) },
2349 { "bswap", { RMeAX
}, 0 },
2350 { "bswap", { RMeCX
}, 0 },
2351 { "bswap", { RMeDX
}, 0 },
2352 { "bswap", { RMeBX
}, 0 },
2353 { "bswap", { RMeSP
}, 0 },
2354 { "bswap", { RMeBP
}, 0 },
2355 { "bswap", { RMeSI
}, 0 },
2356 { "bswap", { RMeDI
}, 0 },
2358 { PREFIX_TABLE (PREFIX_0FD0
) },
2359 { "psrlw", { MX
, EM
}, PREFIX_OPCODE
},
2360 { "psrld", { MX
, EM
}, PREFIX_OPCODE
},
2361 { "psrlq", { MX
, EM
}, PREFIX_OPCODE
},
2362 { "paddq", { MX
, EM
}, PREFIX_OPCODE
},
2363 { "pmullw", { MX
, EM
}, PREFIX_OPCODE
},
2364 { PREFIX_TABLE (PREFIX_0FD6
) },
2365 { MOD_TABLE (MOD_0FD7
) },
2367 { "psubusb", { MX
, EM
}, PREFIX_OPCODE
},
2368 { "psubusw", { MX
, EM
}, PREFIX_OPCODE
},
2369 { "pminub", { MX
, EM
}, PREFIX_OPCODE
},
2370 { "pand", { MX
, EM
}, PREFIX_OPCODE
},
2371 { "paddusb", { MX
, EM
}, PREFIX_OPCODE
},
2372 { "paddusw", { MX
, EM
}, PREFIX_OPCODE
},
2373 { "pmaxub", { MX
, EM
}, PREFIX_OPCODE
},
2374 { "pandn", { MX
, EM
}, PREFIX_OPCODE
},
2376 { "pavgb", { MX
, EM
}, PREFIX_OPCODE
},
2377 { "psraw", { MX
, EM
}, PREFIX_OPCODE
},
2378 { "psrad", { MX
, EM
}, PREFIX_OPCODE
},
2379 { "pavgw", { MX
, EM
}, PREFIX_OPCODE
},
2380 { "pmulhuw", { MX
, EM
}, PREFIX_OPCODE
},
2381 { "pmulhw", { MX
, EM
}, PREFIX_OPCODE
},
2382 { PREFIX_TABLE (PREFIX_0FE6
) },
2383 { PREFIX_TABLE (PREFIX_0FE7
) },
2385 { "psubsb", { MX
, EM
}, PREFIX_OPCODE
},
2386 { "psubsw", { MX
, EM
}, PREFIX_OPCODE
},
2387 { "pminsw", { MX
, EM
}, PREFIX_OPCODE
},
2388 { "por", { MX
, EM
}, PREFIX_OPCODE
},
2389 { "paddsb", { MX
, EM
}, PREFIX_OPCODE
},
2390 { "paddsw", { MX
, EM
}, PREFIX_OPCODE
},
2391 { "pmaxsw", { MX
, EM
}, PREFIX_OPCODE
},
2392 { "pxor", { MX
, EM
}, PREFIX_OPCODE
},
2394 { PREFIX_TABLE (PREFIX_0FF0
) },
2395 { "psllw", { MX
, EM
}, PREFIX_OPCODE
},
2396 { "pslld", { MX
, EM
}, PREFIX_OPCODE
},
2397 { "psllq", { MX
, EM
}, PREFIX_OPCODE
},
2398 { "pmuludq", { MX
, EM
}, PREFIX_OPCODE
},
2399 { "pmaddwd", { MX
, EM
}, PREFIX_OPCODE
},
2400 { "psadbw", { MX
, EM
}, PREFIX_OPCODE
},
2401 { PREFIX_TABLE (PREFIX_0FF7
) },
2403 { "psubb", { MX
, EM
}, PREFIX_OPCODE
},
2404 { "psubw", { MX
, EM
}, PREFIX_OPCODE
},
2405 { "psubd", { MX
, EM
}, PREFIX_OPCODE
},
2406 { "psubq", { MX
, EM
}, PREFIX_OPCODE
},
2407 { "paddb", { MX
, EM
}, PREFIX_OPCODE
},
2408 { "paddw", { MX
, EM
}, PREFIX_OPCODE
},
2409 { "paddd", { MX
, EM
}, PREFIX_OPCODE
},
2410 { "ud0S", { Gv
, Ev
}, 0 },
2413 static const unsigned char onebyte_has_modrm
[256] = {
2414 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2415 /* ------------------------------- */
2416 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2417 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2418 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2419 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2420 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2421 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2422 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2423 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2424 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2425 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2426 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2427 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2428 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2429 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2430 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2431 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
2432 /* ------------------------------- */
2433 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2436 static const unsigned char twobyte_has_modrm
[256] = {
2437 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2438 /* ------------------------------- */
2439 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2440 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2441 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2442 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2443 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2444 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2445 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2446 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2447 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2448 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2449 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2450 /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2451 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2452 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2453 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2454 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 /* ff */
2455 /* ------------------------------- */
2456 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2459 static char obuf
[100];
2461 static char *mnemonicendp
;
2462 static char scratchbuf
[100];
2463 static unsigned char *start_codep
;
2464 static unsigned char *insn_codep
;
2465 static unsigned char *codep
;
2466 static unsigned char *end_codep
;
2467 static int last_lock_prefix
;
2468 static int last_repz_prefix
;
2469 static int last_repnz_prefix
;
2470 static int last_data_prefix
;
2471 static int last_addr_prefix
;
2472 static int last_rex_prefix
;
2473 static int last_seg_prefix
;
2474 static int fwait_prefix
;
2475 /* The active segment register prefix. */
2476 static int active_seg_prefix
;
2477 #define MAX_CODE_LENGTH 15
2478 /* We can up to 14 prefixes since the maximum instruction length is
2480 static int all_prefixes
[MAX_CODE_LENGTH
- 1];
2481 static disassemble_info
*the_info
;
2489 static unsigned char need_modrm
;
2499 int register_specifier
;
2506 int mask_register_specifier
;
2512 static unsigned char need_vex
;
2520 /* If we are accessing mod/rm/reg without need_modrm set, then the
2521 values are stale. Hitting this abort likely indicates that you
2522 need to update onebyte_has_modrm or twobyte_has_modrm. */
2523 #define MODRM_CHECK if (!need_modrm) abort ()
2525 static const char **names64
;
2526 static const char **names32
;
2527 static const char **names16
;
2528 static const char **names8
;
2529 static const char **names8rex
;
2530 static const char **names_seg
;
2531 static const char *index64
;
2532 static const char *index32
;
2533 static const char **index16
;
2534 static const char **names_bnd
;
2536 static const char *intel_names64
[] = {
2537 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2538 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2540 static const char *intel_names32
[] = {
2541 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2542 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2544 static const char *intel_names16
[] = {
2545 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2546 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2548 static const char *intel_names8
[] = {
2549 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2551 static const char *intel_names8rex
[] = {
2552 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2553 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2555 static const char *intel_names_seg
[] = {
2556 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2558 static const char *intel_index64
= "riz";
2559 static const char *intel_index32
= "eiz";
2560 static const char *intel_index16
[] = {
2561 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2564 static const char *att_names64
[] = {
2565 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2566 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2568 static const char *att_names32
[] = {
2569 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2570 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2572 static const char *att_names16
[] = {
2573 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2574 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2576 static const char *att_names8
[] = {
2577 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2579 static const char *att_names8rex
[] = {
2580 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2581 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2583 static const char *att_names_seg
[] = {
2584 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2586 static const char *att_index64
= "%riz";
2587 static const char *att_index32
= "%eiz";
2588 static const char *att_index16
[] = {
2589 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2592 static const char **names_mm
;
2593 static const char *intel_names_mm
[] = {
2594 "mm0", "mm1", "mm2", "mm3",
2595 "mm4", "mm5", "mm6", "mm7"
2597 static const char *att_names_mm
[] = {
2598 "%mm0", "%mm1", "%mm2", "%mm3",
2599 "%mm4", "%mm5", "%mm6", "%mm7"
2602 static const char *intel_names_bnd
[] = {
2603 "bnd0", "bnd1", "bnd2", "bnd3"
2606 static const char *att_names_bnd
[] = {
2607 "%bnd0", "%bnd1", "%bnd2", "%bnd3"
2610 static const char **names_xmm
;
2611 static const char *intel_names_xmm
[] = {
2612 "xmm0", "xmm1", "xmm2", "xmm3",
2613 "xmm4", "xmm5", "xmm6", "xmm7",
2614 "xmm8", "xmm9", "xmm10", "xmm11",
2615 "xmm12", "xmm13", "xmm14", "xmm15",
2616 "xmm16", "xmm17", "xmm18", "xmm19",
2617 "xmm20", "xmm21", "xmm22", "xmm23",
2618 "xmm24", "xmm25", "xmm26", "xmm27",
2619 "xmm28", "xmm29", "xmm30", "xmm31"
2621 static const char *att_names_xmm
[] = {
2622 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
2623 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
2624 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
2625 "%xmm12", "%xmm13", "%xmm14", "%xmm15",
2626 "%xmm16", "%xmm17", "%xmm18", "%xmm19",
2627 "%xmm20", "%xmm21", "%xmm22", "%xmm23",
2628 "%xmm24", "%xmm25", "%xmm26", "%xmm27",
2629 "%xmm28", "%xmm29", "%xmm30", "%xmm31"
2632 static const char **names_ymm
;
2633 static const char *intel_names_ymm
[] = {
2634 "ymm0", "ymm1", "ymm2", "ymm3",
2635 "ymm4", "ymm5", "ymm6", "ymm7",
2636 "ymm8", "ymm9", "ymm10", "ymm11",
2637 "ymm12", "ymm13", "ymm14", "ymm15",
2638 "ymm16", "ymm17", "ymm18", "ymm19",
2639 "ymm20", "ymm21", "ymm22", "ymm23",
2640 "ymm24", "ymm25", "ymm26", "ymm27",
2641 "ymm28", "ymm29", "ymm30", "ymm31"
2643 static const char *att_names_ymm
[] = {
2644 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
2645 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
2646 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
2647 "%ymm12", "%ymm13", "%ymm14", "%ymm15",
2648 "%ymm16", "%ymm17", "%ymm18", "%ymm19",
2649 "%ymm20", "%ymm21", "%ymm22", "%ymm23",
2650 "%ymm24", "%ymm25", "%ymm26", "%ymm27",
2651 "%ymm28", "%ymm29", "%ymm30", "%ymm31"
2654 static const char **names_zmm
;
2655 static const char *intel_names_zmm
[] = {
2656 "zmm0", "zmm1", "zmm2", "zmm3",
2657 "zmm4", "zmm5", "zmm6", "zmm7",
2658 "zmm8", "zmm9", "zmm10", "zmm11",
2659 "zmm12", "zmm13", "zmm14", "zmm15",
2660 "zmm16", "zmm17", "zmm18", "zmm19",
2661 "zmm20", "zmm21", "zmm22", "zmm23",
2662 "zmm24", "zmm25", "zmm26", "zmm27",
2663 "zmm28", "zmm29", "zmm30", "zmm31"
2665 static const char *att_names_zmm
[] = {
2666 "%zmm0", "%zmm1", "%zmm2", "%zmm3",
2667 "%zmm4", "%zmm5", "%zmm6", "%zmm7",
2668 "%zmm8", "%zmm9", "%zmm10", "%zmm11",
2669 "%zmm12", "%zmm13", "%zmm14", "%zmm15",
2670 "%zmm16", "%zmm17", "%zmm18", "%zmm19",
2671 "%zmm20", "%zmm21", "%zmm22", "%zmm23",
2672 "%zmm24", "%zmm25", "%zmm26", "%zmm27",
2673 "%zmm28", "%zmm29", "%zmm30", "%zmm31"
2676 static const char **names_tmm
;
2677 static const char *intel_names_tmm
[] = {
2678 "tmm0", "tmm1", "tmm2", "tmm3",
2679 "tmm4", "tmm5", "tmm6", "tmm7"
2681 static const char *att_names_tmm
[] = {
2682 "%tmm0", "%tmm1", "%tmm2", "%tmm3",
2683 "%tmm4", "%tmm5", "%tmm6", "%tmm7"
2686 static const char **names_mask
;
2687 static const char *intel_names_mask
[] = {
2688 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
2690 static const char *att_names_mask
[] = {
2691 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
2694 static const char *names_rounding
[] =
2702 static const struct dis386 reg_table
[][8] = {
2705 { "addA", { Ebh1
, Ib
}, 0 },
2706 { "orA", { Ebh1
, Ib
}, 0 },
2707 { "adcA", { Ebh1
, Ib
}, 0 },
2708 { "sbbA", { Ebh1
, Ib
}, 0 },
2709 { "andA", { Ebh1
, Ib
}, 0 },
2710 { "subA", { Ebh1
, Ib
}, 0 },
2711 { "xorA", { Ebh1
, Ib
}, 0 },
2712 { "cmpA", { Eb
, Ib
}, 0 },
2716 { "addQ", { Evh1
, Iv
}, 0 },
2717 { "orQ", { Evh1
, Iv
}, 0 },
2718 { "adcQ", { Evh1
, Iv
}, 0 },
2719 { "sbbQ", { Evh1
, Iv
}, 0 },
2720 { "andQ", { Evh1
, Iv
}, 0 },
2721 { "subQ", { Evh1
, Iv
}, 0 },
2722 { "xorQ", { Evh1
, Iv
}, 0 },
2723 { "cmpQ", { Ev
, Iv
}, 0 },
2727 { "addQ", { Evh1
, sIb
}, 0 },
2728 { "orQ", { Evh1
, sIb
}, 0 },
2729 { "adcQ", { Evh1
, sIb
}, 0 },
2730 { "sbbQ", { Evh1
, sIb
}, 0 },
2731 { "andQ", { Evh1
, sIb
}, 0 },
2732 { "subQ", { Evh1
, sIb
}, 0 },
2733 { "xorQ", { Evh1
, sIb
}, 0 },
2734 { "cmpQ", { Ev
, sIb
}, 0 },
2738 { "pop{P|}", { stackEv
}, 0 },
2739 { XOP_8F_TABLE (XOP_09
) },
2743 { XOP_8F_TABLE (XOP_09
) },
2747 { "rolA", { Eb
, Ib
}, 0 },
2748 { "rorA", { Eb
, Ib
}, 0 },
2749 { "rclA", { Eb
, Ib
}, 0 },
2750 { "rcrA", { Eb
, Ib
}, 0 },
2751 { "shlA", { Eb
, Ib
}, 0 },
2752 { "shrA", { Eb
, Ib
}, 0 },
2753 { "shlA", { Eb
, Ib
}, 0 },
2754 { "sarA", { Eb
, Ib
}, 0 },
2758 { "rolQ", { Ev
, Ib
}, 0 },
2759 { "rorQ", { Ev
, Ib
}, 0 },
2760 { "rclQ", { Ev
, Ib
}, 0 },
2761 { "rcrQ", { Ev
, Ib
}, 0 },
2762 { "shlQ", { Ev
, Ib
}, 0 },
2763 { "shrQ", { Ev
, Ib
}, 0 },
2764 { "shlQ", { Ev
, Ib
}, 0 },
2765 { "sarQ", { Ev
, Ib
}, 0 },
2769 { "movA", { Ebh3
, Ib
}, 0 },
2776 { MOD_TABLE (MOD_C6_REG_7
) },
2780 { "movQ", { Evh3
, Iv
}, 0 },
2787 { MOD_TABLE (MOD_C7_REG_7
) },
2791 { "rolA", { Eb
, I1
}, 0 },
2792 { "rorA", { Eb
, I1
}, 0 },
2793 { "rclA", { Eb
, I1
}, 0 },
2794 { "rcrA", { Eb
, I1
}, 0 },
2795 { "shlA", { Eb
, I1
}, 0 },
2796 { "shrA", { Eb
, I1
}, 0 },
2797 { "shlA", { Eb
, I1
}, 0 },
2798 { "sarA", { Eb
, I1
}, 0 },
2802 { "rolQ", { Ev
, I1
}, 0 },
2803 { "rorQ", { Ev
, I1
}, 0 },
2804 { "rclQ", { Ev
, I1
}, 0 },
2805 { "rcrQ", { Ev
, I1
}, 0 },
2806 { "shlQ", { Ev
, I1
}, 0 },
2807 { "shrQ", { Ev
, I1
}, 0 },
2808 { "shlQ", { Ev
, I1
}, 0 },
2809 { "sarQ", { Ev
, I1
}, 0 },
2813 { "rolA", { Eb
, CL
}, 0 },
2814 { "rorA", { Eb
, CL
}, 0 },
2815 { "rclA", { Eb
, CL
}, 0 },
2816 { "rcrA", { Eb
, CL
}, 0 },
2817 { "shlA", { Eb
, CL
}, 0 },
2818 { "shrA", { Eb
, CL
}, 0 },
2819 { "shlA", { Eb
, CL
}, 0 },
2820 { "sarA", { Eb
, CL
}, 0 },
2824 { "rolQ", { Ev
, CL
}, 0 },
2825 { "rorQ", { Ev
, CL
}, 0 },
2826 { "rclQ", { Ev
, CL
}, 0 },
2827 { "rcrQ", { Ev
, CL
}, 0 },
2828 { "shlQ", { Ev
, CL
}, 0 },
2829 { "shrQ", { Ev
, CL
}, 0 },
2830 { "shlQ", { Ev
, CL
}, 0 },
2831 { "sarQ", { Ev
, CL
}, 0 },
2835 { "testA", { Eb
, Ib
}, 0 },
2836 { "testA", { Eb
, Ib
}, 0 },
2837 { "notA", { Ebh1
}, 0 },
2838 { "negA", { Ebh1
}, 0 },
2839 { "mulA", { Eb
}, 0 }, /* Don't print the implicit %al register, */
2840 { "imulA", { Eb
}, 0 }, /* to distinguish these opcodes from other */
2841 { "divA", { Eb
}, 0 }, /* mul/imul opcodes. Do the same for div */
2842 { "idivA", { Eb
}, 0 }, /* and idiv for consistency. */
2846 { "testQ", { Ev
, Iv
}, 0 },
2847 { "testQ", { Ev
, Iv
}, 0 },
2848 { "notQ", { Evh1
}, 0 },
2849 { "negQ", { Evh1
}, 0 },
2850 { "mulQ", { Ev
}, 0 }, /* Don't print the implicit register. */
2851 { "imulQ", { Ev
}, 0 },
2852 { "divQ", { Ev
}, 0 },
2853 { "idivQ", { Ev
}, 0 },
2857 { "incA", { Ebh1
}, 0 },
2858 { "decA", { Ebh1
}, 0 },
2862 { "incQ", { Evh1
}, 0 },
2863 { "decQ", { Evh1
}, 0 },
2864 { "call{@|}", { NOTRACK
, indirEv
, BND
}, 0 },
2865 { MOD_TABLE (MOD_FF_REG_3
) },
2866 { "jmp{@|}", { NOTRACK
, indirEv
, BND
}, 0 },
2867 { MOD_TABLE (MOD_FF_REG_5
) },
2868 { "push{P|}", { stackEv
}, 0 },
2873 { "sldtD", { Sv
}, 0 },
2874 { "strD", { Sv
}, 0 },
2875 { "lldt", { Ew
}, 0 },
2876 { "ltr", { Ew
}, 0 },
2877 { "verr", { Ew
}, 0 },
2878 { "verw", { Ew
}, 0 },
2884 { MOD_TABLE (MOD_0F01_REG_0
) },
2885 { MOD_TABLE (MOD_0F01_REG_1
) },
2886 { MOD_TABLE (MOD_0F01_REG_2
) },
2887 { MOD_TABLE (MOD_0F01_REG_3
) },
2888 { "smswD", { Sv
}, 0 },
2889 { MOD_TABLE (MOD_0F01_REG_5
) },
2890 { "lmsw", { Ew
}, 0 },
2891 { MOD_TABLE (MOD_0F01_REG_7
) },
2895 { "prefetch", { Mb
}, 0 },
2896 { "prefetchw", { Mb
}, 0 },
2897 { "prefetchwt1", { Mb
}, 0 },
2898 { "prefetch", { Mb
}, 0 },
2899 { "prefetch", { Mb
}, 0 },
2900 { "prefetch", { Mb
}, 0 },
2901 { "prefetch", { Mb
}, 0 },
2902 { "prefetch", { Mb
}, 0 },
2906 { MOD_TABLE (MOD_0F18_REG_0
) },
2907 { MOD_TABLE (MOD_0F18_REG_1
) },
2908 { MOD_TABLE (MOD_0F18_REG_2
) },
2909 { MOD_TABLE (MOD_0F18_REG_3
) },
2910 { MOD_TABLE (MOD_0F18_REG_4
) },
2911 { MOD_TABLE (MOD_0F18_REG_5
) },
2912 { MOD_TABLE (MOD_0F18_REG_6
) },
2913 { MOD_TABLE (MOD_0F18_REG_7
) },
2915 /* REG_0F1C_P_0_MOD_0 */
2917 { "cldemote", { Mb
}, 0 },
2918 { "nopQ", { Ev
}, 0 },
2919 { "nopQ", { Ev
}, 0 },
2920 { "nopQ", { Ev
}, 0 },
2921 { "nopQ", { Ev
}, 0 },
2922 { "nopQ", { Ev
}, 0 },
2923 { "nopQ", { Ev
}, 0 },
2924 { "nopQ", { Ev
}, 0 },
2926 /* REG_0F1E_P_1_MOD_3 */
2928 { "nopQ", { Ev
}, 0 },
2929 { "rdsspK", { Edq
}, PREFIX_OPCODE
},
2930 { "nopQ", { Ev
}, 0 },
2931 { "nopQ", { Ev
}, 0 },
2932 { "nopQ", { Ev
}, 0 },
2933 { "nopQ", { Ev
}, 0 },
2934 { "nopQ", { Ev
}, 0 },
2935 { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7
) },
2937 /* REG_0F38D8_PREFIX_1 */
2939 { "aesencwide128kl", { M
}, 0 },
2940 { "aesdecwide128kl", { M
}, 0 },
2941 { "aesencwide256kl", { M
}, 0 },
2942 { "aesdecwide256kl", { M
}, 0 },
2944 /* REG_0F3A0F_PREFIX_1_MOD_3 */
2946 { RM_TABLE (RM_0F3A0F_P_1_MOD_3_REG_0
) },
2952 { MOD_TABLE (MOD_0F71_REG_2
) },
2954 { MOD_TABLE (MOD_0F71_REG_4
) },
2956 { MOD_TABLE (MOD_0F71_REG_6
) },
2962 { MOD_TABLE (MOD_0F72_REG_2
) },
2964 { MOD_TABLE (MOD_0F72_REG_4
) },
2966 { MOD_TABLE (MOD_0F72_REG_6
) },
2972 { MOD_TABLE (MOD_0F73_REG_2
) },
2973 { MOD_TABLE (MOD_0F73_REG_3
) },
2976 { MOD_TABLE (MOD_0F73_REG_6
) },
2977 { MOD_TABLE (MOD_0F73_REG_7
) },
2981 { "montmul", { { OP_0f07
, 0 } }, 0 },
2982 { "xsha1", { { OP_0f07
, 0 } }, 0 },
2983 { "xsha256", { { OP_0f07
, 0 } }, 0 },
2987 { "xstore-rng", { { OP_0f07
, 0 } }, 0 },
2988 { "xcrypt-ecb", { { OP_0f07
, 0 } }, 0 },
2989 { "xcrypt-cbc", { { OP_0f07
, 0 } }, 0 },
2990 { "xcrypt-ctr", { { OP_0f07
, 0 } }, 0 },
2991 { "xcrypt-cfb", { { OP_0f07
, 0 } }, 0 },
2992 { "xcrypt-ofb", { { OP_0f07
, 0 } }, 0 },
2996 { MOD_TABLE (MOD_0FAE_REG_0
) },
2997 { MOD_TABLE (MOD_0FAE_REG_1
) },
2998 { MOD_TABLE (MOD_0FAE_REG_2
) },
2999 { MOD_TABLE (MOD_0FAE_REG_3
) },
3000 { MOD_TABLE (MOD_0FAE_REG_4
) },
3001 { MOD_TABLE (MOD_0FAE_REG_5
) },
3002 { MOD_TABLE (MOD_0FAE_REG_6
) },
3003 { MOD_TABLE (MOD_0FAE_REG_7
) },
3011 { "btQ", { Ev
, Ib
}, 0 },
3012 { "btsQ", { Evh1
, Ib
}, 0 },
3013 { "btrQ", { Evh1
, Ib
}, 0 },
3014 { "btcQ", { Evh1
, Ib
}, 0 },
3019 { "cmpxchg8b", { { CMPXCHG8B_Fixup
, q_mode
} }, 0 },
3021 { MOD_TABLE (MOD_0FC7_REG_3
) },
3022 { MOD_TABLE (MOD_0FC7_REG_4
) },
3023 { MOD_TABLE (MOD_0FC7_REG_5
) },
3024 { MOD_TABLE (MOD_0FC7_REG_6
) },
3025 { MOD_TABLE (MOD_0FC7_REG_7
) },
3031 { MOD_TABLE (MOD_VEX_0F71_REG_2
) },
3033 { MOD_TABLE (MOD_VEX_0F71_REG_4
) },
3035 { MOD_TABLE (MOD_VEX_0F71_REG_6
) },
3041 { MOD_TABLE (MOD_VEX_0F72_REG_2
) },
3043 { MOD_TABLE (MOD_VEX_0F72_REG_4
) },
3045 { MOD_TABLE (MOD_VEX_0F72_REG_6
) },
3051 { MOD_TABLE (MOD_VEX_0F73_REG_2
) },
3052 { MOD_TABLE (MOD_VEX_0F73_REG_3
) },
3055 { MOD_TABLE (MOD_VEX_0F73_REG_6
) },
3056 { MOD_TABLE (MOD_VEX_0F73_REG_7
) },
3062 { MOD_TABLE (MOD_VEX_0FAE_REG_2
) },
3063 { MOD_TABLE (MOD_VEX_0FAE_REG_3
) },
3065 /* REG_VEX_0F3849_X86_64_P_0_W_0_M_1 */
3067 { RM_TABLE (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0
) },
3069 /* REG_VEX_0F38F3 */
3072 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1
) },
3073 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2
) },
3074 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3
) },
3076 /* REG_0FXOP_09_01_L_0 */
3079 { "blcfill", { VexGdq
, Edq
}, 0 },
3080 { "blsfill", { VexGdq
, Edq
}, 0 },
3081 { "blcs", { VexGdq
, Edq
}, 0 },
3082 { "tzmsk", { VexGdq
, Edq
}, 0 },
3083 { "blcic", { VexGdq
, Edq
}, 0 },
3084 { "blsic", { VexGdq
, Edq
}, 0 },
3085 { "t1mskc", { VexGdq
, Edq
}, 0 },
3087 /* REG_0FXOP_09_02_L_0 */
3090 { "blcmsk", { VexGdq
, Edq
}, 0 },
3095 { "blci", { VexGdq
, Edq
}, 0 },
3097 /* REG_0FXOP_09_12_M_1_L_0 */
3099 { "llwpcb", { Edq
}, 0 },
3100 { "slwpcb", { Edq
}, 0 },
3102 /* REG_0FXOP_0A_12_L_0 */
3104 { "lwpins", { VexGdq
, Ed
, Id
}, 0 },
3105 { "lwpval", { VexGdq
, Ed
, Id
}, 0 },
3108 #include "i386-dis-evex-reg.h"
3111 static const struct dis386 prefix_table
[][4] = {
3114 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} }, 0 },
3115 { "pause", { XX
}, 0 },
3116 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} }, 0 },
3117 { NULL
, { { NULL
, 0 } }, PREFIX_IGNORED
}
3120 /* PREFIX_0F01_REG_1_RM_4 */
3124 { "tdcall", { Skip_MODRM
}, 0 },
3128 /* PREFIX_0F01_REG_1_RM_5 */
3132 { X86_64_TABLE (X86_64_0F01_REG_1_RM_5_PREFIX_2
) },
3136 /* PREFIX_0F01_REG_1_RM_6 */
3140 { X86_64_TABLE (X86_64_0F01_REG_1_RM_6_PREFIX_2
) },
3144 /* PREFIX_0F01_REG_1_RM_7 */
3146 { "encls", { Skip_MODRM
}, 0 },
3148 { X86_64_TABLE (X86_64_0F01_REG_1_RM_7_PREFIX_2
) },
3152 /* PREFIX_0F01_REG_3_RM_1 */
3154 { "vmmcall", { Skip_MODRM
}, 0 },
3155 { "vmgexit", { Skip_MODRM
}, 0 },
3157 { "vmgexit", { Skip_MODRM
}, 0 },
3160 /* PREFIX_0F01_REG_5_MOD_0 */
3163 { "rstorssp", { Mq
}, PREFIX_OPCODE
},
3166 /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
3168 { "serialize", { Skip_MODRM
}, PREFIX_OPCODE
},
3169 { "setssbsy", { Skip_MODRM
}, PREFIX_OPCODE
},
3171 { "xsusldtrk", { Skip_MODRM
}, PREFIX_OPCODE
},
3174 /* PREFIX_0F01_REG_5_MOD_3_RM_1 */
3179 { "xresldtrk", { Skip_MODRM
}, PREFIX_OPCODE
},
3182 /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
3185 { "saveprevssp", { Skip_MODRM
}, PREFIX_OPCODE
},
3188 /* PREFIX_0F01_REG_5_MOD_3_RM_4 */
3191 { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1
) },
3194 /* PREFIX_0F01_REG_5_MOD_3_RM_5 */
3197 { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1
) },
3200 /* PREFIX_0F01_REG_5_MOD_3_RM_6 */
3202 { "rdpkru", { Skip_MODRM
}, 0 },
3203 { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1
) },
3206 /* PREFIX_0F01_REG_5_MOD_3_RM_7 */
3208 { "wrpkru", { Skip_MODRM
}, 0 },
3209 { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1
) },
3212 /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
3214 { "monitorx", { { OP_Monitor
, 0 } }, 0 },
3215 { "mcommit", { Skip_MODRM
}, 0 },
3218 /* PREFIX_0F01_REG_7_MOD_3_RM_6 */
3220 { "invlpgb", { Skip_MODRM
}, 0 },
3221 { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1
) },
3223 { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3
) },
3226 /* PREFIX_0F01_REG_7_MOD_3_RM_7 */
3228 { "tlbsync", { Skip_MODRM
}, 0 },
3229 { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1
) },
3231 { "pvalidate", { Skip_MODRM
}, 0 },
3236 { "wbinvd", { XX
}, 0 },
3237 { "wbnoinvd", { XX
}, 0 },
3242 { "movups", { XM
, EXx
}, PREFIX_OPCODE
},
3243 { "movss", { XM
, EXd
}, PREFIX_OPCODE
},
3244 { "movupd", { XM
, EXx
}, PREFIX_OPCODE
},
3245 { "movsd", { XM
, EXq
}, PREFIX_OPCODE
},
3250 { "movups", { EXxS
, XM
}, PREFIX_OPCODE
},
3251 { "movss", { EXdS
, XM
}, PREFIX_OPCODE
},
3252 { "movupd", { EXxS
, XM
}, PREFIX_OPCODE
},
3253 { "movsd", { EXqS
, XM
}, PREFIX_OPCODE
},
3258 { MOD_TABLE (MOD_0F12_PREFIX_0
) },
3259 { "movsldup", { XM
, EXx
}, PREFIX_OPCODE
},
3260 { MOD_TABLE (MOD_0F12_PREFIX_2
) },
3261 { "movddup", { XM
, EXq
}, PREFIX_OPCODE
},
3266 { MOD_TABLE (MOD_0F16_PREFIX_0
) },
3267 { "movshdup", { XM
, EXx
}, PREFIX_OPCODE
},
3268 { MOD_TABLE (MOD_0F16_PREFIX_2
) },
3273 { MOD_TABLE (MOD_0F1A_PREFIX_0
) },
3274 { "bndcl", { Gbnd
, Ev_bnd
}, 0 },
3275 { "bndmov", { Gbnd
, Ebnd
}, 0 },
3276 { "bndcu", { Gbnd
, Ev_bnd
}, 0 },
3281 { MOD_TABLE (MOD_0F1B_PREFIX_0
) },
3282 { MOD_TABLE (MOD_0F1B_PREFIX_1
) },
3283 { "bndmov", { EbndS
, Gbnd
}, 0 },
3284 { "bndcn", { Gbnd
, Ev_bnd
}, 0 },
3289 { MOD_TABLE (MOD_0F1C_PREFIX_0
) },
3290 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3291 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3292 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3297 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3298 { MOD_TABLE (MOD_0F1E_PREFIX_1
) },
3299 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3300 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3305 { "cvtpi2ps", { XM
, EMCq
}, PREFIX_OPCODE
},
3306 { "cvtsi2ss{%LQ|}", { XM
, Edq
}, PREFIX_OPCODE
},
3307 { "cvtpi2pd", { XM
, EMCq
}, PREFIX_OPCODE
},
3308 { "cvtsi2sd{%LQ|}", { XM
, Edq
}, 0 },
3313 { MOD_TABLE (MOD_0F2B_PREFIX_0
) },
3314 { MOD_TABLE (MOD_0F2B_PREFIX_1
) },
3315 { MOD_TABLE (MOD_0F2B_PREFIX_2
) },
3316 { MOD_TABLE (MOD_0F2B_PREFIX_3
) },
3321 { "cvttps2pi", { MXC
, EXq
}, PREFIX_OPCODE
},
3322 { "cvttss2si", { Gdq
, EXd
}, PREFIX_OPCODE
},
3323 { "cvttpd2pi", { MXC
, EXx
}, PREFIX_OPCODE
},
3324 { "cvttsd2si", { Gdq
, EXq
}, PREFIX_OPCODE
},
3329 { "cvtps2pi", { MXC
, EXq
}, PREFIX_OPCODE
},
3330 { "cvtss2si", { Gdq
, EXd
}, PREFIX_OPCODE
},
3331 { "cvtpd2pi", { MXC
, EXx
}, PREFIX_OPCODE
},
3332 { "cvtsd2si", { Gdq
, EXq
}, PREFIX_OPCODE
},
3337 { "ucomiss",{ XM
, EXd
}, 0 },
3339 { "ucomisd",{ XM
, EXq
}, 0 },
3344 { "comiss", { XM
, EXd
}, 0 },
3346 { "comisd", { XM
, EXq
}, 0 },
3351 { "sqrtps", { XM
, EXx
}, PREFIX_OPCODE
},
3352 { "sqrtss", { XM
, EXd
}, PREFIX_OPCODE
},
3353 { "sqrtpd", { XM
, EXx
}, PREFIX_OPCODE
},
3354 { "sqrtsd", { XM
, EXq
}, PREFIX_OPCODE
},
3359 { "rsqrtps",{ XM
, EXx
}, PREFIX_OPCODE
},
3360 { "rsqrtss",{ XM
, EXd
}, PREFIX_OPCODE
},
3365 { "rcpps", { XM
, EXx
}, PREFIX_OPCODE
},
3366 { "rcpss", { XM
, EXd
}, PREFIX_OPCODE
},
3371 { "addps", { XM
, EXx
}, PREFIX_OPCODE
},
3372 { "addss", { XM
, EXd
}, PREFIX_OPCODE
},
3373 { "addpd", { XM
, EXx
}, PREFIX_OPCODE
},
3374 { "addsd", { XM
, EXq
}, PREFIX_OPCODE
},
3379 { "mulps", { XM
, EXx
}, PREFIX_OPCODE
},
3380 { "mulss", { XM
, EXd
}, PREFIX_OPCODE
},
3381 { "mulpd", { XM
, EXx
}, PREFIX_OPCODE
},
3382 { "mulsd", { XM
, EXq
}, PREFIX_OPCODE
},
3387 { "cvtps2pd", { XM
, EXq
}, PREFIX_OPCODE
},
3388 { "cvtss2sd", { XM
, EXd
}, PREFIX_OPCODE
},
3389 { "cvtpd2ps", { XM
, EXx
}, PREFIX_OPCODE
},
3390 { "cvtsd2ss", { XM
, EXq
}, PREFIX_OPCODE
},
3395 { "cvtdq2ps", { XM
, EXx
}, PREFIX_OPCODE
},
3396 { "cvttps2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3397 { "cvtps2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3402 { "subps", { XM
, EXx
}, PREFIX_OPCODE
},
3403 { "subss", { XM
, EXd
}, PREFIX_OPCODE
},
3404 { "subpd", { XM
, EXx
}, PREFIX_OPCODE
},
3405 { "subsd", { XM
, EXq
}, PREFIX_OPCODE
},
3410 { "minps", { XM
, EXx
}, PREFIX_OPCODE
},
3411 { "minss", { XM
, EXd
}, PREFIX_OPCODE
},
3412 { "minpd", { XM
, EXx
}, PREFIX_OPCODE
},
3413 { "minsd", { XM
, EXq
}, PREFIX_OPCODE
},
3418 { "divps", { XM
, EXx
}, PREFIX_OPCODE
},
3419 { "divss", { XM
, EXd
}, PREFIX_OPCODE
},
3420 { "divpd", { XM
, EXx
}, PREFIX_OPCODE
},
3421 { "divsd", { XM
, EXq
}, PREFIX_OPCODE
},
3426 { "maxps", { XM
, EXx
}, PREFIX_OPCODE
},
3427 { "maxss", { XM
, EXd
}, PREFIX_OPCODE
},
3428 { "maxpd", { XM
, EXx
}, PREFIX_OPCODE
},
3429 { "maxsd", { XM
, EXq
}, PREFIX_OPCODE
},
3434 { "punpcklbw",{ MX
, EMd
}, PREFIX_OPCODE
},
3436 { "punpcklbw",{ MX
, EMx
}, PREFIX_OPCODE
},
3441 { "punpcklwd",{ MX
, EMd
}, PREFIX_OPCODE
},
3443 { "punpcklwd",{ MX
, EMx
}, PREFIX_OPCODE
},
3448 { "punpckldq",{ MX
, EMd
}, PREFIX_OPCODE
},
3450 { "punpckldq",{ MX
, EMx
}, PREFIX_OPCODE
},
3455 { "movq", { MX
, EM
}, PREFIX_OPCODE
},
3456 { "movdqu", { XM
, EXx
}, PREFIX_OPCODE
},
3457 { "movdqa", { XM
, EXx
}, PREFIX_OPCODE
},
3462 { "pshufw", { MX
, EM
, Ib
}, PREFIX_OPCODE
},
3463 { "pshufhw",{ XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3464 { "pshufd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3465 { "pshuflw",{ XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3470 {"vmread", { Em
, Gm
}, 0 },
3472 {"extrq", { XS
, Ib
, Ib
}, 0 },
3473 {"insertq", { XM
, XS
, Ib
, Ib
}, 0 },
3478 {"vmwrite", { Gm
, Em
}, 0 },
3480 {"extrq", { XM
, XS
}, 0 },
3481 {"insertq", { XM
, XS
}, 0 },
3488 { "haddpd", { XM
, EXx
}, PREFIX_OPCODE
},
3489 { "haddps", { XM
, EXx
}, PREFIX_OPCODE
},
3496 { "hsubpd", { XM
, EXx
}, PREFIX_OPCODE
},
3497 { "hsubps", { XM
, EXx
}, PREFIX_OPCODE
},
3502 { "movK", { Edq
, MX
}, PREFIX_OPCODE
},
3503 { "movq", { XM
, EXq
}, PREFIX_OPCODE
},
3504 { "movK", { Edq
, XM
}, PREFIX_OPCODE
},
3509 { "movq", { EMS
, MX
}, PREFIX_OPCODE
},
3510 { "movdqu", { EXxS
, XM
}, PREFIX_OPCODE
},
3511 { "movdqa", { EXxS
, XM
}, PREFIX_OPCODE
},
3514 /* PREFIX_0FAE_REG_0_MOD_3 */
3517 { "rdfsbase", { Ev
}, 0 },
3520 /* PREFIX_0FAE_REG_1_MOD_3 */
3523 { "rdgsbase", { Ev
}, 0 },
3526 /* PREFIX_0FAE_REG_2_MOD_3 */
3529 { "wrfsbase", { Ev
}, 0 },
3532 /* PREFIX_0FAE_REG_3_MOD_3 */
3535 { "wrgsbase", { Ev
}, 0 },
3538 /* PREFIX_0FAE_REG_4_MOD_0 */
3540 { "xsave", { FXSAVE
}, 0 },
3541 { "ptwrite{%LQ|}", { Edq
}, 0 },
3544 /* PREFIX_0FAE_REG_4_MOD_3 */
3547 { "ptwrite{%LQ|}", { Edq
}, 0 },
3550 /* PREFIX_0FAE_REG_5_MOD_3 */
3552 { "lfence", { Skip_MODRM
}, 0 },
3553 { "incsspK", { Edq
}, PREFIX_OPCODE
},
3556 /* PREFIX_0FAE_REG_6_MOD_0 */
3558 { "xsaveopt", { FXSAVE
}, PREFIX_OPCODE
},
3559 { "clrssbsy", { Mq
}, PREFIX_OPCODE
},
3560 { "clwb", { Mb
}, PREFIX_OPCODE
},
3563 /* PREFIX_0FAE_REG_6_MOD_3 */
3565 { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0
) },
3566 { "umonitor", { Eva
}, PREFIX_OPCODE
},
3567 { "tpause", { Edq
}, PREFIX_OPCODE
},
3568 { "umwait", { Edq
}, PREFIX_OPCODE
},
3571 /* PREFIX_0FAE_REG_7_MOD_0 */
3573 { "clflush", { Mb
}, 0 },
3575 { "clflushopt", { Mb
}, 0 },
3581 { "popcntS", { Gv
, Ev
}, 0 },
3586 { "bsfS", { Gv
, Ev
}, 0 },
3587 { "tzcntS", { Gv
, Ev
}, 0 },
3588 { "bsfS", { Gv
, Ev
}, 0 },
3593 { "bsrS", { Gv
, Ev
}, 0 },
3594 { "lzcntS", { Gv
, Ev
}, 0 },
3595 { "bsrS", { Gv
, Ev
}, 0 },
3600 { "cmpps", { XM
, EXx
, CMP
}, PREFIX_OPCODE
},
3601 { "cmpss", { XM
, EXd
, CMP
}, PREFIX_OPCODE
},
3602 { "cmppd", { XM
, EXx
, CMP
}, PREFIX_OPCODE
},
3603 { "cmpsd", { XM
, EXq
, CMP
}, PREFIX_OPCODE
},
3606 /* PREFIX_0FC7_REG_6_MOD_0 */
3608 { "vmptrld",{ Mq
}, 0 },
3609 { "vmxon", { Mq
}, 0 },
3610 { "vmclear",{ Mq
}, 0 },
3613 /* PREFIX_0FC7_REG_6_MOD_3 */
3615 { "rdrand", { Ev
}, 0 },
3616 { X86_64_TABLE (X86_64_0FC7_REG_6_MOD_3_PREFIX_1
) },
3617 { "rdrand", { Ev
}, 0 }
3620 /* PREFIX_0FC7_REG_7_MOD_3 */
3622 { "rdseed", { Ev
}, 0 },
3623 { "rdpid", { Em
}, 0 },
3624 { "rdseed", { Ev
}, 0 },
3631 { "addsubpd", { XM
, EXx
}, 0 },
3632 { "addsubps", { XM
, EXx
}, 0 },
3638 { "movq2dq",{ XM
, MS
}, 0 },
3639 { "movq", { EXqS
, XM
}, 0 },
3640 { "movdq2q",{ MX
, XS
}, 0 },
3646 { "cvtdq2pd", { XM
, EXq
}, PREFIX_OPCODE
},
3647 { "cvttpd2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3648 { "cvtpd2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3653 { "movntq", { Mq
, MX
}, PREFIX_OPCODE
},
3655 { MOD_TABLE (MOD_0FE7_PREFIX_2
) },
3663 { MOD_TABLE (MOD_0FF0_PREFIX_3
) },
3668 { "maskmovq", { MX
, MS
}, PREFIX_OPCODE
},
3670 { "maskmovdqu", { XM
, XS
}, PREFIX_OPCODE
},
3676 { REG_TABLE (REG_0F38D8_PREFIX_1
) },
3682 { MOD_TABLE (MOD_0F38DC_PREFIX_1
) },
3683 { "aesenc", { XM
, EXx
}, 0 },
3689 { MOD_TABLE (MOD_0F38DD_PREFIX_1
) },
3690 { "aesenclast", { XM
, EXx
}, 0 },
3696 { MOD_TABLE (MOD_0F38DE_PREFIX_1
) },
3697 { "aesdec", { XM
, EXx
}, 0 },
3703 { MOD_TABLE (MOD_0F38DF_PREFIX_1
) },
3704 { "aesdeclast", { XM
, EXx
}, 0 },
3709 { "movbeS", { Gv
, Mv
}, PREFIX_OPCODE
},
3711 { "movbeS", { Gv
, Mv
}, PREFIX_OPCODE
},
3712 { "crc32A", { Gdq
, Eb
}, PREFIX_OPCODE
},
3717 { "movbeS", { Mv
, Gv
}, PREFIX_OPCODE
},
3719 { "movbeS", { Mv
, Gv
}, PREFIX_OPCODE
},
3720 { "crc32Q", { Gdq
, Ev
}, PREFIX_OPCODE
},
3725 { MOD_TABLE (MOD_0F38F6_PREFIX_0
) },
3726 { "adoxS", { Gdq
, Edq
}, PREFIX_OPCODE
},
3727 { "adcxS", { Gdq
, Edq
}, PREFIX_OPCODE
},
3734 { MOD_TABLE (MOD_0F38F8_PREFIX_1
) },
3735 { MOD_TABLE (MOD_0F38F8_PREFIX_2
) },
3736 { MOD_TABLE (MOD_0F38F8_PREFIX_3
) },
3741 { MOD_TABLE (MOD_0F38FA_PREFIX_1
) },
3747 { MOD_TABLE (MOD_0F38FB_PREFIX_1
) },
3753 { MOD_TABLE (MOD_0F3A0F_PREFIX_1
)},
3756 /* PREFIX_VEX_0F10 */
3758 { "vmovups", { XM
, EXx
}, 0 },
3759 { "vmovss", { XMScalar
, VexScalarR
, EXxmm_md
}, 0 },
3760 { "vmovupd", { XM
, EXx
}, 0 },
3761 { "vmovsd", { XMScalar
, VexScalarR
, EXxmm_mq
}, 0 },
3764 /* PREFIX_VEX_0F11 */
3766 { "vmovups", { EXxS
, XM
}, 0 },
3767 { "vmovss", { EXdS
, VexScalarR
, XMScalar
}, 0 },
3768 { "vmovupd", { EXxS
, XM
}, 0 },
3769 { "vmovsd", { EXqS
, VexScalarR
, XMScalar
}, 0 },
3772 /* PREFIX_VEX_0F12 */
3774 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0
) },
3775 { "vmovsldup", { XM
, EXx
}, 0 },
3776 { MOD_TABLE (MOD_VEX_0F12_PREFIX_2
) },
3777 { "vmovddup", { XM
, EXymmq
}, 0 },
3780 /* PREFIX_VEX_0F16 */
3782 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0
) },
3783 { "vmovshdup", { XM
, EXx
}, 0 },
3784 { MOD_TABLE (MOD_VEX_0F16_PREFIX_2
) },
3787 /* PREFIX_VEX_0F2A */
3790 { "vcvtsi2ss{%LQ|}", { XMScalar
, VexScalar
, Edq
}, 0 },
3792 { "vcvtsi2sd{%LQ|}", { XMScalar
, VexScalar
, Edq
}, 0 },
3795 /* PREFIX_VEX_0F2C */
3798 { "vcvttss2si", { Gdq
, EXxmm_md
, EXxEVexS
}, 0 },
3800 { "vcvttsd2si", { Gdq
, EXxmm_mq
, EXxEVexS
}, 0 },
3803 /* PREFIX_VEX_0F2D */
3806 { "vcvtss2si", { Gdq
, EXxmm_md
, EXxEVexR
}, 0 },
3808 { "vcvtsd2si", { Gdq
, EXxmm_mq
, EXxEVexR
}, 0 },
3811 /* PREFIX_VEX_0F2E */
3813 { "vucomisX", { XMScalar
, EXxmm_md
, EXxEVexS
}, PREFIX_OPCODE
},
3815 { "vucomisX", { XMScalar
, EXxmm_mq
, EXxEVexS
}, PREFIX_OPCODE
},
3818 /* PREFIX_VEX_0F2F */
3820 { "vcomisX", { XMScalar
, EXxmm_md
, EXxEVexS
}, PREFIX_OPCODE
},
3822 { "vcomisX", { XMScalar
, EXxmm_mq
, EXxEVexS
}, PREFIX_OPCODE
},
3825 /* PREFIX_VEX_0F41 */
3827 { VEX_LEN_TABLE (VEX_LEN_0F41_P_0
) },
3829 { VEX_LEN_TABLE (VEX_LEN_0F41_P_2
) },
3832 /* PREFIX_VEX_0F42 */
3834 { VEX_LEN_TABLE (VEX_LEN_0F42_P_0
) },
3836 { VEX_LEN_TABLE (VEX_LEN_0F42_P_2
) },
3839 /* PREFIX_VEX_0F44 */
3841 { VEX_LEN_TABLE (VEX_LEN_0F44_P_0
) },
3843 { VEX_LEN_TABLE (VEX_LEN_0F44_P_2
) },
3846 /* PREFIX_VEX_0F45 */
3848 { VEX_LEN_TABLE (VEX_LEN_0F45_P_0
) },
3850 { VEX_LEN_TABLE (VEX_LEN_0F45_P_2
) },
3853 /* PREFIX_VEX_0F46 */
3855 { VEX_LEN_TABLE (VEX_LEN_0F46_P_0
) },
3857 { VEX_LEN_TABLE (VEX_LEN_0F46_P_2
) },
3860 /* PREFIX_VEX_0F47 */
3862 { VEX_LEN_TABLE (VEX_LEN_0F47_P_0
) },
3864 { VEX_LEN_TABLE (VEX_LEN_0F47_P_2
) },
3867 /* PREFIX_VEX_0F4A */
3869 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0
) },
3871 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2
) },
3874 /* PREFIX_VEX_0F4B */
3876 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0
) },
3878 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2
) },
3881 /* PREFIX_VEX_0F51 */
3883 { "vsqrtps", { XM
, EXx
}, 0 },
3884 { "vsqrtss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
3885 { "vsqrtpd", { XM
, EXx
}, 0 },
3886 { "vsqrtsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
3889 /* PREFIX_VEX_0F52 */
3891 { "vrsqrtps", { XM
, EXx
}, 0 },
3892 { "vrsqrtss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
3895 /* PREFIX_VEX_0F53 */
3897 { "vrcpps", { XM
, EXx
}, 0 },
3898 { "vrcpss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
3901 /* PREFIX_VEX_0F58 */
3903 { "vaddps", { XM
, Vex
, EXx
}, 0 },
3904 { "vaddss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
3905 { "vaddpd", { XM
, Vex
, EXx
}, 0 },
3906 { "vaddsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
3909 /* PREFIX_VEX_0F59 */
3911 { "vmulps", { XM
, Vex
, EXx
}, 0 },
3912 { "vmulss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
3913 { "vmulpd", { XM
, Vex
, EXx
}, 0 },
3914 { "vmulsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
3917 /* PREFIX_VEX_0F5A */
3919 { "vcvtps2pd", { XM
, EXxmmq
}, 0 },
3920 { "vcvtss2sd", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
3921 { "vcvtpd2ps%XY",{ XMM
, EXx
}, 0 },
3922 { "vcvtsd2ss", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
3925 /* PREFIX_VEX_0F5B */
3927 { "vcvtdq2ps", { XM
, EXx
}, 0 },
3928 { "vcvttps2dq", { XM
, EXx
}, 0 },
3929 { "vcvtps2dq", { XM
, EXx
}, 0 },
3932 /* PREFIX_VEX_0F5C */
3934 { "vsubps", { XM
, Vex
, EXx
}, 0 },
3935 { "vsubss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
3936 { "vsubpd", { XM
, Vex
, EXx
}, 0 },
3937 { "vsubsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
3940 /* PREFIX_VEX_0F5D */
3942 { "vminps", { XM
, Vex
, EXx
}, 0 },
3943 { "vminss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
3944 { "vminpd", { XM
, Vex
, EXx
}, 0 },
3945 { "vminsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
3948 /* PREFIX_VEX_0F5E */
3950 { "vdivps", { XM
, Vex
, EXx
}, 0 },
3951 { "vdivss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
3952 { "vdivpd", { XM
, Vex
, EXx
}, 0 },
3953 { "vdivsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
3956 /* PREFIX_VEX_0F5F */
3958 { "vmaxps", { XM
, Vex
, EXx
}, 0 },
3959 { "vmaxss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
3960 { "vmaxpd", { XM
, Vex
, EXx
}, 0 },
3961 { "vmaxsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
3964 /* PREFIX_VEX_0F6F */
3967 { "vmovdqu", { XM
, EXx
}, 0 },
3968 { "vmovdqa", { XM
, EXx
}, 0 },
3971 /* PREFIX_VEX_0F70 */
3974 { "vpshufhw", { XM
, EXx
, Ib
}, 0 },
3975 { "vpshufd", { XM
, EXx
, Ib
}, 0 },
3976 { "vpshuflw", { XM
, EXx
, Ib
}, 0 },
3979 /* PREFIX_VEX_0F7C */
3983 { "vhaddpd", { XM
, Vex
, EXx
}, 0 },
3984 { "vhaddps", { XM
, Vex
, EXx
}, 0 },
3987 /* PREFIX_VEX_0F7D */
3991 { "vhsubpd", { XM
, Vex
, EXx
}, 0 },
3992 { "vhsubps", { XM
, Vex
, EXx
}, 0 },
3995 /* PREFIX_VEX_0F7E */
3998 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1
) },
3999 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2
) },
4002 /* PREFIX_VEX_0F7F */
4005 { "vmovdqu", { EXxS
, XM
}, 0 },
4006 { "vmovdqa", { EXxS
, XM
}, 0 },
4009 /* PREFIX_VEX_0F90 */
4011 { VEX_LEN_TABLE (VEX_LEN_0F90_P_0
) },
4013 { VEX_LEN_TABLE (VEX_LEN_0F90_P_2
) },
4016 /* PREFIX_VEX_0F91 */
4018 { VEX_LEN_TABLE (VEX_LEN_0F91_P_0
) },
4020 { VEX_LEN_TABLE (VEX_LEN_0F91_P_2
) },
4023 /* PREFIX_VEX_0F92 */
4025 { VEX_LEN_TABLE (VEX_LEN_0F92_P_0
) },
4027 { VEX_LEN_TABLE (VEX_LEN_0F92_P_2
) },
4028 { VEX_LEN_TABLE (VEX_LEN_0F92_P_3
) },
4031 /* PREFIX_VEX_0F93 */
4033 { VEX_LEN_TABLE (VEX_LEN_0F93_P_0
) },
4035 { VEX_LEN_TABLE (VEX_LEN_0F93_P_2
) },
4036 { VEX_LEN_TABLE (VEX_LEN_0F93_P_3
) },
4039 /* PREFIX_VEX_0F98 */
4041 { VEX_LEN_TABLE (VEX_LEN_0F98_P_0
) },
4043 { VEX_LEN_TABLE (VEX_LEN_0F98_P_2
) },
4046 /* PREFIX_VEX_0F99 */
4048 { VEX_LEN_TABLE (VEX_LEN_0F99_P_0
) },
4050 { VEX_LEN_TABLE (VEX_LEN_0F99_P_2
) },
4053 /* PREFIX_VEX_0FC2 */
4055 { "vcmpps", { XM
, Vex
, EXx
, CMP
}, 0 },
4056 { "vcmpss", { XMScalar
, VexScalar
, EXxmm_md
, CMP
}, 0 },
4057 { "vcmppd", { XM
, Vex
, EXx
, CMP
}, 0 },
4058 { "vcmpsd", { XMScalar
, VexScalar
, EXxmm_mq
, CMP
}, 0 },
4061 /* PREFIX_VEX_0FD0 */
4065 { "vaddsubpd", { XM
, Vex
, EXx
}, 0 },
4066 { "vaddsubps", { XM
, Vex
, EXx
}, 0 },
4069 /* PREFIX_VEX_0FE6 */
4072 { "vcvtdq2pd", { XM
, EXxmmq
}, 0 },
4073 { "vcvttpd2dq%XY", { XMM
, EXx
}, 0 },
4074 { "vcvtpd2dq%XY", { XMM
, EXx
}, 0 },
4077 /* PREFIX_VEX_0FF0 */
4082 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3
) },
4085 /* PREFIX_VEX_0F3849_X86_64 */
4087 { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_0
) },
4089 { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_2
) },
4090 { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_3
) },
4093 /* PREFIX_VEX_0F384B_X86_64 */
4096 { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_1
) },
4097 { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_2
) },
4098 { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_3
) },
4101 /* PREFIX_VEX_0F385C_X86_64 */
4104 { VEX_W_TABLE (VEX_W_0F385C_X86_64_P_1
) },
4108 /* PREFIX_VEX_0F385E_X86_64 */
4110 { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_0
) },
4111 { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_1
) },
4112 { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_2
) },
4113 { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_3
) },
4116 /* PREFIX_VEX_0F38F5 */
4118 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0
) },
4119 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1
) },
4121 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3
) },
4124 /* PREFIX_VEX_0F38F6 */
4129 { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3
) },
4132 /* PREFIX_VEX_0F38F7 */
4134 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0
) },
4135 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1
) },
4136 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2
) },
4137 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3
) },
4140 /* PREFIX_VEX_0F3AF0 */
4145 { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3
) },
4148 #include "i386-dis-evex-prefix.h"
4151 static const struct dis386 x86_64_table
[][2] = {
4154 { "pushP", { es
}, 0 },
4159 { "popP", { es
}, 0 },
4164 { "pushP", { cs
}, 0 },
4169 { "pushP", { ss
}, 0 },
4174 { "popP", { ss
}, 0 },
4179 { "pushP", { ds
}, 0 },
4184 { "popP", { ds
}, 0 },
4189 { "daa", { XX
}, 0 },
4194 { "das", { XX
}, 0 },
4199 { "aaa", { XX
}, 0 },
4204 { "aas", { XX
}, 0 },
4209 { "pushaP", { XX
}, 0 },
4214 { "popaP", { XX
}, 0 },
4219 { MOD_TABLE (MOD_62_32BIT
) },
4220 { EVEX_TABLE (EVEX_0F
) },
4225 { "arpl", { Ew
, Gw
}, 0 },
4226 { "movs", { { OP_G
, movsxd_mode
}, { MOVSXD_Fixup
, movsxd_mode
} }, 0 },
4231 { "ins{R|}", { Yzr
, indirDX
}, 0 },
4232 { "ins{G|}", { Yzr
, indirDX
}, 0 },
4237 { "outs{R|}", { indirDXr
, Xz
}, 0 },
4238 { "outs{G|}", { indirDXr
, Xz
}, 0 },
4243 /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */
4244 { REG_TABLE (REG_80
) },
4249 { "{l|}call{P|}", { Ap
}, 0 },
4254 { "retP", { Iw
, BND
}, 0 },
4255 { "ret@", { Iw
, BND
}, 0 },
4260 { "retP", { BND
}, 0 },
4261 { "ret@", { BND
}, 0 },
4266 { MOD_TABLE (MOD_C4_32BIT
) },
4267 { VEX_C4_TABLE (VEX_0F
) },
4272 { MOD_TABLE (MOD_C5_32BIT
) },
4273 { VEX_C5_TABLE (VEX_0F
) },
4278 { "into", { XX
}, 0 },
4283 { "aam", { Ib
}, 0 },
4288 { "aad", { Ib
}, 0 },
4293 { "callP", { Jv
, BND
}, 0 },
4294 { "call@", { Jv
, BND
}, 0 }
4299 { "jmpP", { Jv
, BND
}, 0 },
4300 { "jmp@", { Jv
, BND
}, 0 }
4305 { "{l|}jmp{P|}", { Ap
}, 0 },
4308 /* X86_64_0F01_REG_0 */
4310 { "sgdt{Q|Q}", { M
}, 0 },
4311 { "sgdt", { M
}, 0 },
4314 /* X86_64_0F01_REG_1 */
4316 { "sidt{Q|Q}", { M
}, 0 },
4317 { "sidt", { M
}, 0 },
4320 /* X86_64_0F01_REG_1_RM_5_PREFIX_2 */
4323 { "seamret", { Skip_MODRM
}, 0 },
4326 /* X86_64_0F01_REG_1_RM_6_PREFIX_2 */
4329 { "seamops", { Skip_MODRM
}, 0 },
4332 /* X86_64_0F01_REG_1_RM_7_PREFIX_2 */
4335 { "seamcall", { Skip_MODRM
}, 0 },
4338 /* X86_64_0F01_REG_2 */
4340 { "lgdt{Q|Q}", { M
}, 0 },
4341 { "lgdt", { M
}, 0 },
4344 /* X86_64_0F01_REG_3 */
4346 { "lidt{Q|Q}", { M
}, 0 },
4347 { "lidt", { M
}, 0 },
4352 { "movZ", { Em
, Td
}, 0 },
4357 { "movZ", { Td
, Em
}, 0 },
4360 /* X86_64_VEX_0F3849 */
4363 { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64
) },
4366 /* X86_64_VEX_0F384B */
4369 { PREFIX_TABLE (PREFIX_VEX_0F384B_X86_64
) },
4372 /* X86_64_VEX_0F385C */
4375 { PREFIX_TABLE (PREFIX_VEX_0F385C_X86_64
) },
4378 /* X86_64_VEX_0F385E */
4381 { PREFIX_TABLE (PREFIX_VEX_0F385E_X86_64
) },
4384 /* X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1 */
4387 { "uiret", { Skip_MODRM
}, 0 },
4390 /* X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1 */
4393 { "testui", { Skip_MODRM
}, 0 },
4396 /* X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1 */
4399 { "clui", { Skip_MODRM
}, 0 },
4402 /* X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1 */
4405 { "stui", { Skip_MODRM
}, 0 },
4408 /* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1 */
4411 { "rmpadjust", { Skip_MODRM
}, 0 },
4414 /* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3 */
4417 { "rmpupdate", { Skip_MODRM
}, 0 },
4420 /* X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1 */
4423 { "psmash", { Skip_MODRM
}, 0 },
4426 /* X86_64_0FC7_REG_6_MOD_3_PREFIX_1 */
4429 { "senduipi", { Eq
}, 0 },
4433 static const struct dis386 three_byte_table
[][256] = {
4435 /* THREE_BYTE_0F38 */
4438 { "pshufb", { MX
, EM
}, PREFIX_OPCODE
},
4439 { "phaddw", { MX
, EM
}, PREFIX_OPCODE
},
4440 { "phaddd", { MX
, EM
}, PREFIX_OPCODE
},
4441 { "phaddsw", { MX
, EM
}, PREFIX_OPCODE
},
4442 { "pmaddubsw", { MX
, EM
}, PREFIX_OPCODE
},
4443 { "phsubw", { MX
, EM
}, PREFIX_OPCODE
},
4444 { "phsubd", { MX
, EM
}, PREFIX_OPCODE
},
4445 { "phsubsw", { MX
, EM
}, PREFIX_OPCODE
},
4447 { "psignb", { MX
, EM
}, PREFIX_OPCODE
},
4448 { "psignw", { MX
, EM
}, PREFIX_OPCODE
},
4449 { "psignd", { MX
, EM
}, PREFIX_OPCODE
},
4450 { "pmulhrsw", { MX
, EM
}, PREFIX_OPCODE
},
4456 { "pblendvb", { XM
, EXx
, XMM0
}, PREFIX_DATA
},
4460 { "blendvps", { XM
, EXx
, XMM0
}, PREFIX_DATA
},
4461 { "blendvpd", { XM
, EXx
, XMM0
}, PREFIX_DATA
},
4463 { "ptest", { XM
, EXx
}, PREFIX_DATA
},
4469 { "pabsb", { MX
, EM
}, PREFIX_OPCODE
},
4470 { "pabsw", { MX
, EM
}, PREFIX_OPCODE
},
4471 { "pabsd", { MX
, EM
}, PREFIX_OPCODE
},
4474 { "pmovsxbw", { XM
, EXq
}, PREFIX_DATA
},
4475 { "pmovsxbd", { XM
, EXd
}, PREFIX_DATA
},
4476 { "pmovsxbq", { XM
, EXw
}, PREFIX_DATA
},
4477 { "pmovsxwd", { XM
, EXq
}, PREFIX_DATA
},
4478 { "pmovsxwq", { XM
, EXd
}, PREFIX_DATA
},
4479 { "pmovsxdq", { XM
, EXq
}, PREFIX_DATA
},
4483 { "pmuldq", { XM
, EXx
}, PREFIX_DATA
},
4484 { "pcmpeqq", { XM
, EXx
}, PREFIX_DATA
},
4485 { MOD_TABLE (MOD_0F382A
) },
4486 { "packusdw", { XM
, EXx
}, PREFIX_DATA
},
4492 { "pmovzxbw", { XM
, EXq
}, PREFIX_DATA
},
4493 { "pmovzxbd", { XM
, EXd
}, PREFIX_DATA
},
4494 { "pmovzxbq", { XM
, EXw
}, PREFIX_DATA
},
4495 { "pmovzxwd", { XM
, EXq
}, PREFIX_DATA
},
4496 { "pmovzxwq", { XM
, EXd
}, PREFIX_DATA
},
4497 { "pmovzxdq", { XM
, EXq
}, PREFIX_DATA
},
4499 { "pcmpgtq", { XM
, EXx
}, PREFIX_DATA
},
4501 { "pminsb", { XM
, EXx
}, PREFIX_DATA
},
4502 { "pminsd", { XM
, EXx
}, PREFIX_DATA
},
4503 { "pminuw", { XM
, EXx
}, PREFIX_DATA
},
4504 { "pminud", { XM
, EXx
}, PREFIX_DATA
},
4505 { "pmaxsb", { XM
, EXx
}, PREFIX_DATA
},
4506 { "pmaxsd", { XM
, EXx
}, PREFIX_DATA
},
4507 { "pmaxuw", { XM
, EXx
}, PREFIX_DATA
},
4508 { "pmaxud", { XM
, EXx
}, PREFIX_DATA
},
4510 { "pmulld", { XM
, EXx
}, PREFIX_DATA
},
4511 { "phminposuw", { XM
, EXx
}, PREFIX_DATA
},
4582 { "invept", { Gm
, Mo
}, PREFIX_DATA
},
4583 { "invvpid", { Gm
, Mo
}, PREFIX_DATA
},
4584 { "invpcid", { Gm
, M
}, PREFIX_DATA
},
4663 { "sha1nexte", { XM
, EXxmm
}, PREFIX_OPCODE
},
4664 { "sha1msg1", { XM
, EXxmm
}, PREFIX_OPCODE
},
4665 { "sha1msg2", { XM
, EXxmm
}, PREFIX_OPCODE
},
4666 { "sha256rnds2", { XM
, EXxmm
, XMM0
}, PREFIX_OPCODE
},
4667 { "sha256msg1", { XM
, EXxmm
}, PREFIX_OPCODE
},
4668 { "sha256msg2", { XM
, EXxmm
}, PREFIX_OPCODE
},
4670 { "gf2p8mulb", { XM
, EXxmm
}, PREFIX_DATA
},
4681 { PREFIX_TABLE (PREFIX_0F38D8
) },
4684 { "aesimc", { XM
, EXx
}, PREFIX_DATA
},
4685 { PREFIX_TABLE (PREFIX_0F38DC
) },
4686 { PREFIX_TABLE (PREFIX_0F38DD
) },
4687 { PREFIX_TABLE (PREFIX_0F38DE
) },
4688 { PREFIX_TABLE (PREFIX_0F38DF
) },
4708 { PREFIX_TABLE (PREFIX_0F38F0
) },
4709 { PREFIX_TABLE (PREFIX_0F38F1
) },
4713 { MOD_TABLE (MOD_0F38F5
) },
4714 { PREFIX_TABLE (PREFIX_0F38F6
) },
4717 { PREFIX_TABLE (PREFIX_0F38F8
) },
4718 { MOD_TABLE (MOD_0F38F9
) },
4719 { PREFIX_TABLE (PREFIX_0F38FA
) },
4720 { PREFIX_TABLE (PREFIX_0F38FB
) },
4726 /* THREE_BYTE_0F3A */
4738 { "roundps", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4739 { "roundpd", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4740 { "roundss", { XM
, EXd
, Ib
}, PREFIX_DATA
},
4741 { "roundsd", { XM
, EXq
, Ib
}, PREFIX_DATA
},
4742 { "blendps", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4743 { "blendpd", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4744 { "pblendw", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4745 { "palignr", { MX
, EM
, Ib
}, PREFIX_OPCODE
},
4751 { "pextrb", { Edqb
, XM
, Ib
}, PREFIX_DATA
},
4752 { "pextrw", { Edqw
, XM
, Ib
}, PREFIX_DATA
},
4753 { "pextrK", { Edq
, XM
, Ib
}, PREFIX_DATA
},
4754 { "extractps", { Edqd
, XM
, Ib
}, PREFIX_DATA
},
4765 { "pinsrb", { XM
, Edqb
, Ib
}, PREFIX_DATA
},
4766 { "insertps", { XM
, EXd
, Ib
}, PREFIX_DATA
},
4767 { "pinsrK", { XM
, Edq
, Ib
}, PREFIX_DATA
},
4801 { "dpps", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4802 { "dppd", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4803 { "mpsadbw", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4805 { "pclmulqdq", { XM
, EXx
, PCLMUL
}, PREFIX_DATA
},
4837 { "pcmpestrm!%LQ", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4838 { "pcmpestri!%LQ", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4839 { "pcmpistrm", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4840 { "pcmpistri", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4958 { "sha1rnds4", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4960 { "gf2p8affineqb", { XM
, EXxmm
, Ib
}, PREFIX_DATA
},
4961 { "gf2p8affineinvqb", { XM
, EXxmm
, Ib
}, PREFIX_DATA
},
4979 { "aeskeygenassist", { XM
, EXx
, Ib
}, PREFIX_DATA
},
4999 { PREFIX_TABLE (PREFIX_0F3A0F
) },
5019 static const struct dis386 xop_table
[][256] = {
5172 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_85
) },
5173 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_86
) },
5174 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_87
) },
5182 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8E
) },
5183 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8F
) },
5190 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_95
) },
5191 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_96
) },
5192 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_97
) },
5200 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9E
) },
5201 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9F
) },
5205 { "vpcmov", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
5206 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A3
) },
5209 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A6
) },
5227 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_B6
) },
5239 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C0
) },
5240 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C1
) },
5241 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C2
) },
5242 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C3
) },
5252 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC
) },
5253 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD
) },
5254 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE
) },
5255 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF
) },
5288 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC
) },
5289 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED
) },
5290 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE
) },
5291 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF
) },
5315 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_01
) },
5316 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_02
) },
5334 { MOD_TABLE (MOD_VEX_0FXOP_09_12
) },
5458 { VEX_W_TABLE (VEX_W_0FXOP_09_80
) },
5459 { VEX_W_TABLE (VEX_W_0FXOP_09_81
) },
5460 { VEX_W_TABLE (VEX_W_0FXOP_09_82
) },
5461 { VEX_W_TABLE (VEX_W_0FXOP_09_83
) },
5476 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_90
) },
5477 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_91
) },
5478 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_92
) },
5479 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_93
) },
5480 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_94
) },
5481 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_95
) },
5482 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_96
) },
5483 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_97
) },
5485 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_98
) },
5486 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_99
) },
5487 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9A
) },
5488 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9B
) },
5531 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C1
) },
5532 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C2
) },
5533 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C3
) },
5536 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C6
) },
5537 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C7
) },
5542 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_CB
) },
5549 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D1
) },
5550 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D2
) },
5551 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D3
) },
5554 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D6
) },
5555 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D7
) },
5560 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_DB
) },
5567 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E1
) },
5568 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E2
) },
5569 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E3
) },
5623 { "bextrS", { Gdq
, Edq
, Id
}, 0 },
5625 { VEX_LEN_TABLE (VEX_LEN_0FXOP_0A_12
) },
5895 static const struct dis386 vex_table
[][256] = {
5917 { PREFIX_TABLE (PREFIX_VEX_0F10
) },
5918 { PREFIX_TABLE (PREFIX_VEX_0F11
) },
5919 { PREFIX_TABLE (PREFIX_VEX_0F12
) },
5920 { MOD_TABLE (MOD_VEX_0F13
) },
5921 { "vunpcklpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
5922 { "vunpckhpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
5923 { PREFIX_TABLE (PREFIX_VEX_0F16
) },
5924 { MOD_TABLE (MOD_VEX_0F17
) },
5944 { "vmovapX", { XM
, EXx
}, PREFIX_OPCODE
},
5945 { "vmovapX", { EXxS
, XM
}, PREFIX_OPCODE
},
5946 { PREFIX_TABLE (PREFIX_VEX_0F2A
) },
5947 { MOD_TABLE (MOD_VEX_0F2B
) },
5948 { PREFIX_TABLE (PREFIX_VEX_0F2C
) },
5949 { PREFIX_TABLE (PREFIX_VEX_0F2D
) },
5950 { PREFIX_TABLE (PREFIX_VEX_0F2E
) },
5951 { PREFIX_TABLE (PREFIX_VEX_0F2F
) },
5972 { PREFIX_TABLE (PREFIX_VEX_0F41
) },
5973 { PREFIX_TABLE (PREFIX_VEX_0F42
) },
5975 { PREFIX_TABLE (PREFIX_VEX_0F44
) },
5976 { PREFIX_TABLE (PREFIX_VEX_0F45
) },
5977 { PREFIX_TABLE (PREFIX_VEX_0F46
) },
5978 { PREFIX_TABLE (PREFIX_VEX_0F47
) },
5982 { PREFIX_TABLE (PREFIX_VEX_0F4A
) },
5983 { PREFIX_TABLE (PREFIX_VEX_0F4B
) },
5989 { MOD_TABLE (MOD_VEX_0F50
) },
5990 { PREFIX_TABLE (PREFIX_VEX_0F51
) },
5991 { PREFIX_TABLE (PREFIX_VEX_0F52
) },
5992 { PREFIX_TABLE (PREFIX_VEX_0F53
) },
5993 { "vandpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
5994 { "vandnpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
5995 { "vorpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
5996 { "vxorpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
5998 { PREFIX_TABLE (PREFIX_VEX_0F58
) },
5999 { PREFIX_TABLE (PREFIX_VEX_0F59
) },
6000 { PREFIX_TABLE (PREFIX_VEX_0F5A
) },
6001 { PREFIX_TABLE (PREFIX_VEX_0F5B
) },
6002 { PREFIX_TABLE (PREFIX_VEX_0F5C
) },
6003 { PREFIX_TABLE (PREFIX_VEX_0F5D
) },
6004 { PREFIX_TABLE (PREFIX_VEX_0F5E
) },
6005 { PREFIX_TABLE (PREFIX_VEX_0F5F
) },
6007 { "vpunpcklbw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6008 { "vpunpcklwd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6009 { "vpunpckldq", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6010 { "vpacksswb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6011 { "vpcmpgtb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6012 { "vpcmpgtw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6013 { "vpcmpgtd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6014 { "vpackuswb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6016 { "vpunpckhbw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6017 { "vpunpckhwd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6018 { "vpunpckhdq", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6019 { "vpackssdw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6020 { "vpunpcklqdq", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6021 { "vpunpckhqdq", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6022 { VEX_LEN_TABLE (VEX_LEN_0F6E
) },
6023 { PREFIX_TABLE (PREFIX_VEX_0F6F
) },
6025 { PREFIX_TABLE (PREFIX_VEX_0F70
) },
6026 { REG_TABLE (REG_VEX_0F71
) },
6027 { REG_TABLE (REG_VEX_0F72
) },
6028 { REG_TABLE (REG_VEX_0F73
) },
6029 { "vpcmpeqb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6030 { "vpcmpeqw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6031 { "vpcmpeqd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6032 { VEX_LEN_TABLE (VEX_LEN_0F77
) },
6038 { PREFIX_TABLE (PREFIX_VEX_0F7C
) },
6039 { PREFIX_TABLE (PREFIX_VEX_0F7D
) },
6040 { PREFIX_TABLE (PREFIX_VEX_0F7E
) },
6041 { PREFIX_TABLE (PREFIX_VEX_0F7F
) },
6061 { PREFIX_TABLE (PREFIX_VEX_0F90
) },
6062 { PREFIX_TABLE (PREFIX_VEX_0F91
) },
6063 { PREFIX_TABLE (PREFIX_VEX_0F92
) },
6064 { PREFIX_TABLE (PREFIX_VEX_0F93
) },
6070 { PREFIX_TABLE (PREFIX_VEX_0F98
) },
6071 { PREFIX_TABLE (PREFIX_VEX_0F99
) },
6094 { REG_TABLE (REG_VEX_0FAE
) },
6117 { PREFIX_TABLE (PREFIX_VEX_0FC2
) },
6119 { VEX_LEN_TABLE (VEX_LEN_0FC4
) },
6120 { VEX_LEN_TABLE (VEX_LEN_0FC5
) },
6121 { "vshufpX", { XM
, Vex
, EXx
, Ib
}, PREFIX_OPCODE
},
6133 { PREFIX_TABLE (PREFIX_VEX_0FD0
) },
6134 { "vpsrlw", { XM
, Vex
, EXxmm
}, PREFIX_DATA
},
6135 { "vpsrld", { XM
, Vex
, EXxmm
}, PREFIX_DATA
},
6136 { "vpsrlq", { XM
, Vex
, EXxmm
}, PREFIX_DATA
},
6137 { "vpaddq", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6138 { "vpmullw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6139 { VEX_LEN_TABLE (VEX_LEN_0FD6
) },
6140 { MOD_TABLE (MOD_VEX_0FD7
) },
6142 { "vpsubusb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6143 { "vpsubusw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6144 { "vpminub", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6145 { "vpand", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6146 { "vpaddusb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6147 { "vpaddusw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6148 { "vpmaxub", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6149 { "vpandn", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6151 { "vpavgb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6152 { "vpsraw", { XM
, Vex
, EXxmm
}, PREFIX_DATA
},
6153 { "vpsrad", { XM
, Vex
, EXxmm
}, PREFIX_DATA
},
6154 { "vpavgw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6155 { "vpmulhuw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6156 { "vpmulhw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6157 { PREFIX_TABLE (PREFIX_VEX_0FE6
) },
6158 { MOD_TABLE (MOD_VEX_0FE7
) },
6160 { "vpsubsb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6161 { "vpsubsw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6162 { "vpminsw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6163 { "vpor", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6164 { "vpaddsb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6165 { "vpaddsw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6166 { "vpmaxsw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6167 { "vpxor", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6169 { PREFIX_TABLE (PREFIX_VEX_0FF0
) },
6170 { "vpsllw", { XM
, Vex
, EXxmm
}, PREFIX_DATA
},
6171 { "vpslld", { XM
, Vex
, EXxmm
}, PREFIX_DATA
},
6172 { "vpsllq", { XM
, Vex
, EXxmm
}, PREFIX_DATA
},
6173 { "vpmuludq", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6174 { "vpmaddwd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6175 { "vpsadbw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6176 { VEX_LEN_TABLE (VEX_LEN_0FF7
) },
6178 { "vpsubb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6179 { "vpsubw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6180 { "vpsubd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6181 { "vpsubq", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6182 { "vpaddb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6183 { "vpaddw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6184 { "vpaddd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6190 { "vpshufb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6191 { "vphaddw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6192 { "vphaddd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6193 { "vphaddsw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6194 { "vpmaddubsw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6195 { "vphsubw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6196 { "vphsubd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6197 { "vphsubsw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6199 { "vpsignb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6200 { "vpsignw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6201 { "vpsignd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6202 { "vpmulhrsw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6203 { VEX_W_TABLE (VEX_W_0F380C
) },
6204 { VEX_W_TABLE (VEX_W_0F380D
) },
6205 { VEX_W_TABLE (VEX_W_0F380E
) },
6206 { VEX_W_TABLE (VEX_W_0F380F
) },
6211 { VEX_W_TABLE (VEX_W_0F3813
) },
6214 { VEX_LEN_TABLE (VEX_LEN_0F3816
) },
6215 { "vptest", { XM
, EXx
}, PREFIX_DATA
},
6217 { VEX_W_TABLE (VEX_W_0F3818
) },
6218 { VEX_LEN_TABLE (VEX_LEN_0F3819
) },
6219 { MOD_TABLE (MOD_VEX_0F381A
) },
6221 { "vpabsb", { XM
, EXx
}, PREFIX_DATA
},
6222 { "vpabsw", { XM
, EXx
}, PREFIX_DATA
},
6223 { "vpabsd", { XM
, EXx
}, PREFIX_DATA
},
6226 { "vpmovsxbw", { XM
, EXxmmq
}, PREFIX_DATA
},
6227 { "vpmovsxbd", { XM
, EXxmmqd
}, PREFIX_DATA
},
6228 { "vpmovsxbq", { XM
, EXxmmdw
}, PREFIX_DATA
},
6229 { "vpmovsxwd", { XM
, EXxmmq
}, PREFIX_DATA
},
6230 { "vpmovsxwq", { XM
, EXxmmqd
}, PREFIX_DATA
},
6231 { "vpmovsxdq", { XM
, EXxmmq
}, PREFIX_DATA
},
6235 { "vpmuldq", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6236 { "vpcmpeqq", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6237 { MOD_TABLE (MOD_VEX_0F382A
) },
6238 { "vpackusdw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6239 { MOD_TABLE (MOD_VEX_0F382C
) },
6240 { MOD_TABLE (MOD_VEX_0F382D
) },
6241 { MOD_TABLE (MOD_VEX_0F382E
) },
6242 { MOD_TABLE (MOD_VEX_0F382F
) },
6244 { "vpmovzxbw", { XM
, EXxmmq
}, PREFIX_DATA
},
6245 { "vpmovzxbd", { XM
, EXxmmqd
}, PREFIX_DATA
},
6246 { "vpmovzxbq", { XM
, EXxmmdw
}, PREFIX_DATA
},
6247 { "vpmovzxwd", { XM
, EXxmmq
}, PREFIX_DATA
},
6248 { "vpmovzxwq", { XM
, EXxmmqd
}, PREFIX_DATA
},
6249 { "vpmovzxdq", { XM
, EXxmmq
}, PREFIX_DATA
},
6250 { VEX_LEN_TABLE (VEX_LEN_0F3836
) },
6251 { "vpcmpgtq", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6253 { "vpminsb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6254 { "vpminsd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6255 { "vpminuw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6256 { "vpminud", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6257 { "vpmaxsb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6258 { "vpmaxsd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6259 { "vpmaxuw", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6260 { "vpmaxud", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6262 { "vpmulld", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6263 { VEX_LEN_TABLE (VEX_LEN_0F3841
) },
6267 { "vpsrlv%DQ", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6268 { VEX_W_TABLE (VEX_W_0F3846
) },
6269 { "vpsllv%DQ", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6272 { X86_64_TABLE (X86_64_VEX_0F3849
) },
6274 { X86_64_TABLE (X86_64_VEX_0F384B
) },
6280 { VEX_W_TABLE (VEX_W_0F3850
) },
6281 { VEX_W_TABLE (VEX_W_0F3851
) },
6282 { VEX_W_TABLE (VEX_W_0F3852
) },
6283 { VEX_W_TABLE (VEX_W_0F3853
) },
6289 { VEX_W_TABLE (VEX_W_0F3858
) },
6290 { VEX_W_TABLE (VEX_W_0F3859
) },
6291 { MOD_TABLE (MOD_VEX_0F385A
) },
6293 { X86_64_TABLE (X86_64_VEX_0F385C
) },
6295 { X86_64_TABLE (X86_64_VEX_0F385E
) },
6325 { VEX_W_TABLE (VEX_W_0F3878
) },
6326 { VEX_W_TABLE (VEX_W_0F3879
) },
6347 { MOD_TABLE (MOD_VEX_0F388C
) },
6349 { MOD_TABLE (MOD_VEX_0F388E
) },
6352 { "vpgatherd%DQ", { XM
, MVexVSIBDWpX
, Vex
}, PREFIX_DATA
},
6353 { "vpgatherq%DQ", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
}, PREFIX_DATA
},
6354 { "vgatherdp%XW", { XM
, MVexVSIBDWpX
, Vex
}, PREFIX_DATA
},
6355 { "vgatherqp%XW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
}, PREFIX_DATA
},
6358 { "vfmaddsub132p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6359 { "vfmsubadd132p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6361 { "vfmadd132p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6362 { "vfmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, PREFIX_DATA
},
6363 { "vfmsub132p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6364 { "vfmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, PREFIX_DATA
},
6365 { "vfnmadd132p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6366 { "vfnmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, PREFIX_DATA
},
6367 { "vfnmsub132p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6368 { "vfnmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, PREFIX_DATA
},
6376 { "vfmaddsub213p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6377 { "vfmsubadd213p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6379 { "vfmadd213p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6380 { "vfmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, PREFIX_DATA
},
6381 { "vfmsub213p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6382 { "vfmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, PREFIX_DATA
},
6383 { "vfnmadd213p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6384 { "vfnmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, PREFIX_DATA
},
6385 { "vfnmsub213p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6386 { "vfnmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, PREFIX_DATA
},
6394 { "vfmaddsub231p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6395 { "vfmsubadd231p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6397 { "vfmadd231p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6398 { "vfmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, PREFIX_DATA
},
6399 { "vfmsub231p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6400 { "vfmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, PREFIX_DATA
},
6401 { "vfnmadd231p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6402 { "vfnmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, PREFIX_DATA
},
6403 { "vfnmsub231p%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6404 { "vfnmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, PREFIX_DATA
},
6422 { VEX_W_TABLE (VEX_W_0F38CF
) },
6436 { VEX_LEN_TABLE (VEX_LEN_0F38DB
) },
6437 { "vaesenc", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6438 { "vaesenclast", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6439 { "vaesdec", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6440 { "vaesdeclast", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6462 { VEX_LEN_TABLE (VEX_LEN_0F38F2
) },
6463 { REG_TABLE (REG_VEX_0F38F3
) },
6465 { PREFIX_TABLE (PREFIX_VEX_0F38F5
) },
6466 { PREFIX_TABLE (PREFIX_VEX_0F38F6
) },
6467 { PREFIX_TABLE (PREFIX_VEX_0F38F7
) },
6481 { VEX_LEN_TABLE (VEX_LEN_0F3A00
) },
6482 { VEX_LEN_TABLE (VEX_LEN_0F3A01
) },
6483 { VEX_W_TABLE (VEX_W_0F3A02
) },
6485 { VEX_W_TABLE (VEX_W_0F3A04
) },
6486 { VEX_W_TABLE (VEX_W_0F3A05
) },
6487 { VEX_LEN_TABLE (VEX_LEN_0F3A06
) },
6490 { "vroundps", { XM
, EXx
, Ib
}, PREFIX_DATA
},
6491 { "vroundpd", { XM
, EXx
, Ib
}, PREFIX_DATA
},
6492 { "vroundss", { XMScalar
, VexScalar
, EXxmm_md
, Ib
}, PREFIX_DATA
},
6493 { "vroundsd", { XMScalar
, VexScalar
, EXxmm_mq
, Ib
}, PREFIX_DATA
},
6494 { "vblendps", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
6495 { "vblendpd", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
6496 { "vpblendw", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
6497 { "vpalignr", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
6503 { VEX_LEN_TABLE (VEX_LEN_0F3A14
) },
6504 { VEX_LEN_TABLE (VEX_LEN_0F3A15
) },
6505 { VEX_LEN_TABLE (VEX_LEN_0F3A16
) },
6506 { VEX_LEN_TABLE (VEX_LEN_0F3A17
) },
6508 { VEX_LEN_TABLE (VEX_LEN_0F3A18
) },
6509 { VEX_LEN_TABLE (VEX_LEN_0F3A19
) },
6513 { VEX_W_TABLE (VEX_W_0F3A1D
) },
6517 { VEX_LEN_TABLE (VEX_LEN_0F3A20
) },
6518 { VEX_LEN_TABLE (VEX_LEN_0F3A21
) },
6519 { VEX_LEN_TABLE (VEX_LEN_0F3A22
) },
6535 { VEX_LEN_TABLE (VEX_LEN_0F3A30
) },
6536 { VEX_LEN_TABLE (VEX_LEN_0F3A31
) },
6537 { VEX_LEN_TABLE (VEX_LEN_0F3A32
) },
6538 { VEX_LEN_TABLE (VEX_LEN_0F3A33
) },
6544 { VEX_LEN_TABLE (VEX_LEN_0F3A38
) },
6545 { VEX_LEN_TABLE (VEX_LEN_0F3A39
) },
6553 { "vdpps", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
6554 { VEX_LEN_TABLE (VEX_LEN_0F3A41
) },
6555 { "vmpsadbw", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
6557 { "vpclmulqdq", { XM
, Vex
, EXx
, PCLMUL
}, PREFIX_DATA
},
6559 { VEX_LEN_TABLE (VEX_LEN_0F3A46
) },
6562 { "vpermil2ps", { XM
, Vex
, EXx
, XMVexI4
, VexI4
}, PREFIX_DATA
},
6563 { "vpermil2pd", { XM
, Vex
, EXx
, XMVexI4
, VexI4
}, PREFIX_DATA
},
6564 { VEX_W_TABLE (VEX_W_0F3A4A
) },
6565 { VEX_W_TABLE (VEX_W_0F3A4B
) },
6566 { VEX_W_TABLE (VEX_W_0F3A4C
) },
6584 { "vfmaddsubps", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6585 { "vfmaddsubpd", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6586 { "vfmsubaddps", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6587 { "vfmsubaddpd", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6589 { VEX_LEN_TABLE (VEX_LEN_0F3A60
) },
6590 { VEX_LEN_TABLE (VEX_LEN_0F3A61
) },
6591 { VEX_LEN_TABLE (VEX_LEN_0F3A62
) },
6592 { VEX_LEN_TABLE (VEX_LEN_0F3A63
) },
6598 { "vfmaddps", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6599 { "vfmaddpd", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6600 { "vfmaddss", { XMScalar
, VexScalar
, EXxmm_md
, XMVexScalarI4
}, PREFIX_DATA
},
6601 { "vfmaddsd", { XMScalar
, VexScalar
, EXxmm_mq
, XMVexScalarI4
}, PREFIX_DATA
},
6602 { "vfmsubps", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6603 { "vfmsubpd", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6604 { "vfmsubss", { XMScalar
, VexScalar
, EXxmm_md
, XMVexScalarI4
}, PREFIX_DATA
},
6605 { "vfmsubsd", { XMScalar
, VexScalar
, EXxmm_mq
, XMVexScalarI4
}, PREFIX_DATA
},
6616 { "vfnmaddps", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6617 { "vfnmaddpd", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6618 { "vfnmaddss", { XMScalar
, VexScalar
, EXxmm_md
, XMVexScalarI4
}, PREFIX_DATA
},
6619 { "vfnmaddsd", { XMScalar
, VexScalar
, EXxmm_mq
, XMVexScalarI4
}, PREFIX_DATA
},
6620 { "vfnmsubps", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6621 { "vfnmsubpd", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
6622 { "vfnmsubss", { XMScalar
, VexScalar
, EXxmm_md
, XMVexScalarI4
}, PREFIX_DATA
},
6623 { "vfnmsubsd", { XMScalar
, VexScalar
, EXxmm_mq
, XMVexScalarI4
}, PREFIX_DATA
},
6712 { VEX_W_TABLE (VEX_W_0F3ACE
) },
6713 { VEX_W_TABLE (VEX_W_0F3ACF
) },
6731 { VEX_LEN_TABLE (VEX_LEN_0F3ADF
) },
6751 { PREFIX_TABLE (PREFIX_VEX_0F3AF0
) },
6771 #include "i386-dis-evex.h"
6773 static const struct dis386 vex_len_table
[][2] = {
6774 /* VEX_LEN_0F12_P_0_M_0 / VEX_LEN_0F12_P_2_M_0 */
6776 { "vmovlpX", { XM
, Vex
, EXq
}, 0 },
6779 /* VEX_LEN_0F12_P_0_M_1 */
6781 { "vmovhlps", { XM
, Vex
, EXq
}, 0 },
6784 /* VEX_LEN_0F13_M_0 */
6786 { "vmovlpX", { EXq
, XM
}, PREFIX_OPCODE
},
6789 /* VEX_LEN_0F16_P_0_M_0 / VEX_LEN_0F16_P_2_M_0 */
6791 { "vmovhpX", { XM
, Vex
, EXq
}, 0 },
6794 /* VEX_LEN_0F16_P_0_M_1 */
6796 { "vmovlhps", { XM
, Vex
, EXq
}, 0 },
6799 /* VEX_LEN_0F17_M_0 */
6801 { "vmovhpX", { EXq
, XM
}, PREFIX_OPCODE
},
6804 /* VEX_LEN_0F41_P_0 */
6807 { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1
) },
6809 /* VEX_LEN_0F41_P_2 */
6812 { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1
) },
6814 /* VEX_LEN_0F42_P_0 */
6817 { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1
) },
6819 /* VEX_LEN_0F42_P_2 */
6822 { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1
) },
6824 /* VEX_LEN_0F44_P_0 */
6826 { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0
) },
6828 /* VEX_LEN_0F44_P_2 */
6830 { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0
) },
6832 /* VEX_LEN_0F45_P_0 */
6835 { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1
) },
6837 /* VEX_LEN_0F45_P_2 */
6840 { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1
) },
6842 /* VEX_LEN_0F46_P_0 */
6845 { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1
) },
6847 /* VEX_LEN_0F46_P_2 */
6850 { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1
) },
6852 /* VEX_LEN_0F47_P_0 */
6855 { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1
) },
6857 /* VEX_LEN_0F47_P_2 */
6860 { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1
) },
6862 /* VEX_LEN_0F4A_P_0 */
6865 { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1
) },
6867 /* VEX_LEN_0F4A_P_2 */
6870 { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1
) },
6872 /* VEX_LEN_0F4B_P_0 */
6875 { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1
) },
6877 /* VEX_LEN_0F4B_P_2 */
6880 { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1
) },
6885 { "vmovK", { XMScalar
, Edq
}, PREFIX_DATA
},
6890 { "vzeroupper", { XX
}, 0 },
6891 { "vzeroall", { XX
}, 0 },
6894 /* VEX_LEN_0F7E_P_1 */
6896 { "vmovq", { XMScalar
, EXxmm_mq
}, 0 },
6899 /* VEX_LEN_0F7E_P_2 */
6901 { "vmovK", { Edq
, XMScalar
}, 0 },
6904 /* VEX_LEN_0F90_P_0 */
6906 { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0
) },
6909 /* VEX_LEN_0F90_P_2 */
6911 { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0
) },
6914 /* VEX_LEN_0F91_P_0 */
6916 { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0
) },
6919 /* VEX_LEN_0F91_P_2 */
6921 { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0
) },
6924 /* VEX_LEN_0F92_P_0 */
6926 { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0
) },
6929 /* VEX_LEN_0F92_P_2 */
6931 { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0
) },
6934 /* VEX_LEN_0F92_P_3 */
6936 { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0
) },
6939 /* VEX_LEN_0F93_P_0 */
6941 { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0
) },
6944 /* VEX_LEN_0F93_P_2 */
6946 { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0
) },
6949 /* VEX_LEN_0F93_P_3 */
6951 { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0
) },
6954 /* VEX_LEN_0F98_P_0 */
6956 { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0
) },
6959 /* VEX_LEN_0F98_P_2 */
6961 { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0
) },
6964 /* VEX_LEN_0F99_P_0 */
6966 { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0
) },
6969 /* VEX_LEN_0F99_P_2 */
6971 { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0
) },
6974 /* VEX_LEN_0FAE_R_2_M_0 */
6976 { "vldmxcsr", { Md
}, 0 },
6979 /* VEX_LEN_0FAE_R_3_M_0 */
6981 { "vstmxcsr", { Md
}, 0 },
6986 { "vpinsrw", { XM
, Vex
, Edqw
, Ib
}, PREFIX_DATA
},
6991 { "vpextrw", { Gdq
, XS
, Ib
}, PREFIX_DATA
},
6996 { "vmovq", { EXqS
, XMScalar
}, PREFIX_DATA
},
7001 { "vmaskmovdqu", { XM
, XS
}, PREFIX_DATA
},
7004 /* VEX_LEN_0F3816 */
7007 { VEX_W_TABLE (VEX_W_0F3816_L_1
) },
7010 /* VEX_LEN_0F3819 */
7013 { VEX_W_TABLE (VEX_W_0F3819_L_1
) },
7016 /* VEX_LEN_0F381A_M_0 */
7019 { VEX_W_TABLE (VEX_W_0F381A_M_0_L_1
) },
7022 /* VEX_LEN_0F3836 */
7025 { VEX_W_TABLE (VEX_W_0F3836
) },
7028 /* VEX_LEN_0F3841 */
7030 { "vphminposuw", { XM
, EXx
}, PREFIX_DATA
},
7033 /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_0 */
7035 { "ldtilecfg", { M
}, 0 },
7038 /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0 */
7040 { "tilerelease", { Skip_MODRM
}, 0 },
7043 /* VEX_LEN_0F3849_X86_64_P_2_W_0_M_0 */
7045 { "sttilecfg", { M
}, 0 },
7048 /* VEX_LEN_0F3849_X86_64_P_3_W_0_M_0 */
7050 { "tilezero", { TMM
, Skip_MODRM
}, 0 },
7053 /* VEX_LEN_0F384B_X86_64_P_1_W_0_M_0 */
7055 { "tilestored", { MVexSIBMEM
, TMM
}, 0 },
7057 /* VEX_LEN_0F384B_X86_64_P_2_W_0_M_0 */
7059 { "tileloaddt1", { TMM
, MVexSIBMEM
}, 0 },
7062 /* VEX_LEN_0F384B_X86_64_P_3_W_0_M_0 */
7064 { "tileloadd", { TMM
, MVexSIBMEM
}, 0 },
7067 /* VEX_LEN_0F385A_M_0 */
7070 { VEX_W_TABLE (VEX_W_0F385A_M_0_L_0
) },
7073 /* VEX_LEN_0F385C_X86_64_P_1_W_0_M_0 */
7075 { "tdpbf16ps", { TMM
, EXtmm
, VexTmm
}, 0 },
7078 /* VEX_LEN_0F385E_X86_64_P_0_W_0_M_0 */
7080 { "tdpbuud", {TMM
, EXtmm
, VexTmm
}, 0 },
7083 /* VEX_LEN_0F385E_X86_64_P_1_W_0_M_0 */
7085 { "tdpbsud", {TMM
, EXtmm
, VexTmm
}, 0 },
7088 /* VEX_LEN_0F385E_X86_64_P_2_W_0_M_0 */
7090 { "tdpbusd", {TMM
, EXtmm
, VexTmm
}, 0 },
7093 /* VEX_LEN_0F385E_X86_64_P_3_W_0_M_0 */
7095 { "tdpbssd", {TMM
, EXtmm
, VexTmm
}, 0 },
7098 /* VEX_LEN_0F38DB */
7100 { "vaesimc", { XM
, EXx
}, PREFIX_DATA
},
7103 /* VEX_LEN_0F38F2 */
7105 { "andnS", { Gdq
, VexGdq
, Edq
}, PREFIX_OPCODE
},
7108 /* VEX_LEN_0F38F3_R_1 */
7110 { "blsrS", { VexGdq
, Edq
}, PREFIX_OPCODE
},
7113 /* VEX_LEN_0F38F3_R_2 */
7115 { "blsmskS", { VexGdq
, Edq
}, PREFIX_OPCODE
},
7118 /* VEX_LEN_0F38F3_R_3 */
7120 { "blsiS", { VexGdq
, Edq
}, PREFIX_OPCODE
},
7123 /* VEX_LEN_0F38F5_P_0 */
7125 { "bzhiS", { Gdq
, Edq
, VexGdq
}, 0 },
7128 /* VEX_LEN_0F38F5_P_1 */
7130 { "pextS", { Gdq
, VexGdq
, Edq
}, 0 },
7133 /* VEX_LEN_0F38F5_P_3 */
7135 { "pdepS", { Gdq
, VexGdq
, Edq
}, 0 },
7138 /* VEX_LEN_0F38F6_P_3 */
7140 { "mulxS", { Gdq
, VexGdq
, Edq
}, 0 },
7143 /* VEX_LEN_0F38F7_P_0 */
7145 { "bextrS", { Gdq
, Edq
, VexGdq
}, 0 },
7148 /* VEX_LEN_0F38F7_P_1 */
7150 { "sarxS", { Gdq
, Edq
, VexGdq
}, 0 },
7153 /* VEX_LEN_0F38F7_P_2 */
7155 { "shlxS", { Gdq
, Edq
, VexGdq
}, 0 },
7158 /* VEX_LEN_0F38F7_P_3 */
7160 { "shrxS", { Gdq
, Edq
, VexGdq
}, 0 },
7163 /* VEX_LEN_0F3A00 */
7166 { VEX_W_TABLE (VEX_W_0F3A00_L_1
) },
7169 /* VEX_LEN_0F3A01 */
7172 { VEX_W_TABLE (VEX_W_0F3A01_L_1
) },
7175 /* VEX_LEN_0F3A06 */
7178 { VEX_W_TABLE (VEX_W_0F3A06_L_1
) },
7181 /* VEX_LEN_0F3A14 */
7183 { "vpextrb", { Edqb
, XM
, Ib
}, PREFIX_DATA
},
7186 /* VEX_LEN_0F3A15 */
7188 { "vpextrw", { Edqw
, XM
, Ib
}, PREFIX_DATA
},
7191 /* VEX_LEN_0F3A16 */
7193 { "vpextrK", { Edq
, XM
, Ib
}, PREFIX_DATA
},
7196 /* VEX_LEN_0F3A17 */
7198 { "vextractps", { Edqd
, XM
, Ib
}, PREFIX_DATA
},
7201 /* VEX_LEN_0F3A18 */
7204 { VEX_W_TABLE (VEX_W_0F3A18_L_1
) },
7207 /* VEX_LEN_0F3A19 */
7210 { VEX_W_TABLE (VEX_W_0F3A19_L_1
) },
7213 /* VEX_LEN_0F3A20 */
7215 { "vpinsrb", { XM
, Vex
, Edqb
, Ib
}, PREFIX_DATA
},
7218 /* VEX_LEN_0F3A21 */
7220 { "vinsertps", { XM
, Vex
, EXd
, Ib
}, PREFIX_DATA
},
7223 /* VEX_LEN_0F3A22 */
7225 { "vpinsrK", { XM
, Vex
, Edq
, Ib
}, PREFIX_DATA
},
7228 /* VEX_LEN_0F3A30 */
7230 { MOD_TABLE (MOD_VEX_0F3A30_L_0
) },
7233 /* VEX_LEN_0F3A31 */
7235 { MOD_TABLE (MOD_VEX_0F3A31_L_0
) },
7238 /* VEX_LEN_0F3A32 */
7240 { MOD_TABLE (MOD_VEX_0F3A32_L_0
) },
7243 /* VEX_LEN_0F3A33 */
7245 { MOD_TABLE (MOD_VEX_0F3A33_L_0
) },
7248 /* VEX_LEN_0F3A38 */
7251 { VEX_W_TABLE (VEX_W_0F3A38_L_1
) },
7254 /* VEX_LEN_0F3A39 */
7257 { VEX_W_TABLE (VEX_W_0F3A39_L_1
) },
7260 /* VEX_LEN_0F3A41 */
7262 { "vdppd", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
7265 /* VEX_LEN_0F3A46 */
7268 { VEX_W_TABLE (VEX_W_0F3A46_L_1
) },
7271 /* VEX_LEN_0F3A60 */
7273 { "vpcmpestrm!%LQ", { XM
, EXx
, Ib
}, PREFIX_DATA
},
7276 /* VEX_LEN_0F3A61 */
7278 { "vpcmpestri!%LQ", { XM
, EXx
, Ib
}, PREFIX_DATA
},
7281 /* VEX_LEN_0F3A62 */
7283 { "vpcmpistrm", { XM
, EXx
, Ib
}, PREFIX_DATA
},
7286 /* VEX_LEN_0F3A63 */
7288 { "vpcmpistri", { XM
, EXx
, Ib
}, PREFIX_DATA
},
7291 /* VEX_LEN_0F3ADF */
7293 { "vaeskeygenassist", { XM
, EXx
, Ib
}, PREFIX_DATA
},
7296 /* VEX_LEN_0F3AF0_P_3 */
7298 { "rorxS", { Gdq
, Edq
, Ib
}, 0 },
7301 /* VEX_LEN_0FXOP_08_85 */
7303 { VEX_W_TABLE (VEX_W_0FXOP_08_85_L_0
) },
7306 /* VEX_LEN_0FXOP_08_86 */
7308 { VEX_W_TABLE (VEX_W_0FXOP_08_86_L_0
) },
7311 /* VEX_LEN_0FXOP_08_87 */
7313 { VEX_W_TABLE (VEX_W_0FXOP_08_87_L_0
) },
7316 /* VEX_LEN_0FXOP_08_8E */
7318 { VEX_W_TABLE (VEX_W_0FXOP_08_8E_L_0
) },
7321 /* VEX_LEN_0FXOP_08_8F */
7323 { VEX_W_TABLE (VEX_W_0FXOP_08_8F_L_0
) },
7326 /* VEX_LEN_0FXOP_08_95 */
7328 { VEX_W_TABLE (VEX_W_0FXOP_08_95_L_0
) },
7331 /* VEX_LEN_0FXOP_08_96 */
7333 { VEX_W_TABLE (VEX_W_0FXOP_08_96_L_0
) },
7336 /* VEX_LEN_0FXOP_08_97 */
7338 { VEX_W_TABLE (VEX_W_0FXOP_08_97_L_0
) },
7341 /* VEX_LEN_0FXOP_08_9E */
7343 { VEX_W_TABLE (VEX_W_0FXOP_08_9E_L_0
) },
7346 /* VEX_LEN_0FXOP_08_9F */
7348 { VEX_W_TABLE (VEX_W_0FXOP_08_9F_L_0
) },
7351 /* VEX_LEN_0FXOP_08_A3 */
7353 { "vpperm", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7356 /* VEX_LEN_0FXOP_08_A6 */
7358 { VEX_W_TABLE (VEX_W_0FXOP_08_A6_L_0
) },
7361 /* VEX_LEN_0FXOP_08_B6 */
7363 { VEX_W_TABLE (VEX_W_0FXOP_08_B6_L_0
) },
7366 /* VEX_LEN_0FXOP_08_C0 */
7368 { VEX_W_TABLE (VEX_W_0FXOP_08_C0_L_0
) },
7371 /* VEX_LEN_0FXOP_08_C1 */
7373 { VEX_W_TABLE (VEX_W_0FXOP_08_C1_L_0
) },
7376 /* VEX_LEN_0FXOP_08_C2 */
7378 { VEX_W_TABLE (VEX_W_0FXOP_08_C2_L_0
) },
7381 /* VEX_LEN_0FXOP_08_C3 */
7383 { VEX_W_TABLE (VEX_W_0FXOP_08_C3_L_0
) },
7386 /* VEX_LEN_0FXOP_08_CC */
7388 { VEX_W_TABLE (VEX_W_0FXOP_08_CC_L_0
) },
7391 /* VEX_LEN_0FXOP_08_CD */
7393 { VEX_W_TABLE (VEX_W_0FXOP_08_CD_L_0
) },
7396 /* VEX_LEN_0FXOP_08_CE */
7398 { VEX_W_TABLE (VEX_W_0FXOP_08_CE_L_0
) },
7401 /* VEX_LEN_0FXOP_08_CF */
7403 { VEX_W_TABLE (VEX_W_0FXOP_08_CF_L_0
) },
7406 /* VEX_LEN_0FXOP_08_EC */
7408 { VEX_W_TABLE (VEX_W_0FXOP_08_EC_L_0
) },
7411 /* VEX_LEN_0FXOP_08_ED */
7413 { VEX_W_TABLE (VEX_W_0FXOP_08_ED_L_0
) },
7416 /* VEX_LEN_0FXOP_08_EE */
7418 { VEX_W_TABLE (VEX_W_0FXOP_08_EE_L_0
) },
7421 /* VEX_LEN_0FXOP_08_EF */
7423 { VEX_W_TABLE (VEX_W_0FXOP_08_EF_L_0
) },
7426 /* VEX_LEN_0FXOP_09_01 */
7428 { REG_TABLE (REG_0FXOP_09_01_L_0
) },
7431 /* VEX_LEN_0FXOP_09_02 */
7433 { REG_TABLE (REG_0FXOP_09_02_L_0
) },
7436 /* VEX_LEN_0FXOP_09_12_M_1 */
7438 { REG_TABLE (REG_0FXOP_09_12_M_1_L_0
) },
7441 /* VEX_LEN_0FXOP_09_82_W_0 */
7443 { "vfrczss", { XM
, EXd
}, 0 },
7446 /* VEX_LEN_0FXOP_09_83_W_0 */
7448 { "vfrczsd", { XM
, EXq
}, 0 },
7451 /* VEX_LEN_0FXOP_09_90 */
7453 { "vprotb", { XM
, EXx
, VexW
}, 0 },
7456 /* VEX_LEN_0FXOP_09_91 */
7458 { "vprotw", { XM
, EXx
, VexW
}, 0 },
7461 /* VEX_LEN_0FXOP_09_92 */
7463 { "vprotd", { XM
, EXx
, VexW
}, 0 },
7466 /* VEX_LEN_0FXOP_09_93 */
7468 { "vprotq", { XM
, EXx
, VexW
}, 0 },
7471 /* VEX_LEN_0FXOP_09_94 */
7473 { "vpshlb", { XM
, EXx
, VexW
}, 0 },
7476 /* VEX_LEN_0FXOP_09_95 */
7478 { "vpshlw", { XM
, EXx
, VexW
}, 0 },
7481 /* VEX_LEN_0FXOP_09_96 */
7483 { "vpshld", { XM
, EXx
, VexW
}, 0 },
7486 /* VEX_LEN_0FXOP_09_97 */
7488 { "vpshlq", { XM
, EXx
, VexW
}, 0 },
7491 /* VEX_LEN_0FXOP_09_98 */
7493 { "vpshab", { XM
, EXx
, VexW
}, 0 },
7496 /* VEX_LEN_0FXOP_09_99 */
7498 { "vpshaw", { XM
, EXx
, VexW
}, 0 },
7501 /* VEX_LEN_0FXOP_09_9A */
7503 { "vpshad", { XM
, EXx
, VexW
}, 0 },
7506 /* VEX_LEN_0FXOP_09_9B */
7508 { "vpshaq", { XM
, EXx
, VexW
}, 0 },
7511 /* VEX_LEN_0FXOP_09_C1 */
7513 { VEX_W_TABLE (VEX_W_0FXOP_09_C1_L_0
) },
7516 /* VEX_LEN_0FXOP_09_C2 */
7518 { VEX_W_TABLE (VEX_W_0FXOP_09_C2_L_0
) },
7521 /* VEX_LEN_0FXOP_09_C3 */
7523 { VEX_W_TABLE (VEX_W_0FXOP_09_C3_L_0
) },
7526 /* VEX_LEN_0FXOP_09_C6 */
7528 { VEX_W_TABLE (VEX_W_0FXOP_09_C6_L_0
) },
7531 /* VEX_LEN_0FXOP_09_C7 */
7533 { VEX_W_TABLE (VEX_W_0FXOP_09_C7_L_0
) },
7536 /* VEX_LEN_0FXOP_09_CB */
7538 { VEX_W_TABLE (VEX_W_0FXOP_09_CB_L_0
) },
7541 /* VEX_LEN_0FXOP_09_D1 */
7543 { VEX_W_TABLE (VEX_W_0FXOP_09_D1_L_0
) },
7546 /* VEX_LEN_0FXOP_09_D2 */
7548 { VEX_W_TABLE (VEX_W_0FXOP_09_D2_L_0
) },
7551 /* VEX_LEN_0FXOP_09_D3 */
7553 { VEX_W_TABLE (VEX_W_0FXOP_09_D3_L_0
) },
7556 /* VEX_LEN_0FXOP_09_D6 */
7558 { VEX_W_TABLE (VEX_W_0FXOP_09_D6_L_0
) },
7561 /* VEX_LEN_0FXOP_09_D7 */
7563 { VEX_W_TABLE (VEX_W_0FXOP_09_D7_L_0
) },
7566 /* VEX_LEN_0FXOP_09_DB */
7568 { VEX_W_TABLE (VEX_W_0FXOP_09_DB_L_0
) },
7571 /* VEX_LEN_0FXOP_09_E1 */
7573 { VEX_W_TABLE (VEX_W_0FXOP_09_E1_L_0
) },
7576 /* VEX_LEN_0FXOP_09_E2 */
7578 { VEX_W_TABLE (VEX_W_0FXOP_09_E2_L_0
) },
7581 /* VEX_LEN_0FXOP_09_E3 */
7583 { VEX_W_TABLE (VEX_W_0FXOP_09_E3_L_0
) },
7586 /* VEX_LEN_0FXOP_0A_12 */
7588 { REG_TABLE (REG_0FXOP_0A_12_L_0
) },
7592 #include "i386-dis-evex-len.h"
7594 static const struct dis386 vex_w_table
[][2] = {
7596 /* VEX_W_0F41_P_0_LEN_1 */
7597 { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1
) },
7598 { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1
) },
7601 /* VEX_W_0F41_P_2_LEN_1 */
7602 { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1
) },
7603 { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1
) }
7606 /* VEX_W_0F42_P_0_LEN_1 */
7607 { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1
) },
7608 { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1
) },
7611 /* VEX_W_0F42_P_2_LEN_1 */
7612 { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1
) },
7613 { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1
) },
7616 /* VEX_W_0F44_P_0_LEN_0 */
7617 { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1
) },
7618 { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1
) },
7621 /* VEX_W_0F44_P_2_LEN_0 */
7622 { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1
) },
7623 { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1
) },
7626 /* VEX_W_0F45_P_0_LEN_1 */
7627 { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1
) },
7628 { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1
) },
7631 /* VEX_W_0F45_P_2_LEN_1 */
7632 { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1
) },
7633 { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1
) },
7636 /* VEX_W_0F46_P_0_LEN_1 */
7637 { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1
) },
7638 { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1
) },
7641 /* VEX_W_0F46_P_2_LEN_1 */
7642 { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1
) },
7643 { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1
) },
7646 /* VEX_W_0F47_P_0_LEN_1 */
7647 { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1
) },
7648 { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1
) },
7651 /* VEX_W_0F47_P_2_LEN_1 */
7652 { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1
) },
7653 { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1
) },
7656 /* VEX_W_0F4A_P_0_LEN_1 */
7657 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1
) },
7658 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1
) },
7661 /* VEX_W_0F4A_P_2_LEN_1 */
7662 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1
) },
7663 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1
) },
7666 /* VEX_W_0F4B_P_0_LEN_1 */
7667 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1
) },
7668 { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1
) },
7671 /* VEX_W_0F4B_P_2_LEN_1 */
7672 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1
) },
7675 /* VEX_W_0F90_P_0_LEN_0 */
7676 { "kmovw", { MaskG
, MaskE
}, 0 },
7677 { "kmovq", { MaskG
, MaskE
}, 0 },
7680 /* VEX_W_0F90_P_2_LEN_0 */
7681 { "kmovb", { MaskG
, MaskBDE
}, 0 },
7682 { "kmovd", { MaskG
, MaskBDE
}, 0 },
7685 /* VEX_W_0F91_P_0_LEN_0 */
7686 { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0
) },
7687 { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0
) },
7690 /* VEX_W_0F91_P_2_LEN_0 */
7691 { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0
) },
7692 { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0
) },
7695 /* VEX_W_0F92_P_0_LEN_0 */
7696 { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0
) },
7699 /* VEX_W_0F92_P_2_LEN_0 */
7700 { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0
) },
7703 /* VEX_W_0F93_P_0_LEN_0 */
7704 { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0
) },
7707 /* VEX_W_0F93_P_2_LEN_0 */
7708 { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0
) },
7711 /* VEX_W_0F98_P_0_LEN_0 */
7712 { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0
) },
7713 { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0
) },
7716 /* VEX_W_0F98_P_2_LEN_0 */
7717 { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0
) },
7718 { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0
) },
7721 /* VEX_W_0F99_P_0_LEN_0 */
7722 { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0
) },
7723 { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0
) },
7726 /* VEX_W_0F99_P_2_LEN_0 */
7727 { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0
) },
7728 { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0
) },
7732 { "vpermilps", { XM
, Vex
, EXx
}, PREFIX_DATA
},
7736 { "vpermilpd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
7740 { "vtestps", { XM
, EXx
}, PREFIX_DATA
},
7744 { "vtestpd", { XM
, EXx
}, PREFIX_DATA
},
7748 { "vcvtph2ps", { XM
, EXxmmq
}, PREFIX_DATA
},
7751 /* VEX_W_0F3816_L_1 */
7752 { "vpermps", { XM
, Vex
, EXx
}, PREFIX_DATA
},
7756 { "vbroadcastss", { XM
, EXxmm_md
}, PREFIX_DATA
},
7759 /* VEX_W_0F3819_L_1 */
7760 { "vbroadcastsd", { XM
, EXxmm_mq
}, PREFIX_DATA
},
7763 /* VEX_W_0F381A_M_0_L_1 */
7764 { "vbroadcastf128", { XM
, Mxmm
}, PREFIX_DATA
},
7767 /* VEX_W_0F382C_M_0 */
7768 { "vmaskmovps", { XM
, Vex
, Mx
}, PREFIX_DATA
},
7771 /* VEX_W_0F382D_M_0 */
7772 { "vmaskmovpd", { XM
, Vex
, Mx
}, PREFIX_DATA
},
7775 /* VEX_W_0F382E_M_0 */
7776 { "vmaskmovps", { Mx
, Vex
, XM
}, PREFIX_DATA
},
7779 /* VEX_W_0F382F_M_0 */
7780 { "vmaskmovpd", { Mx
, Vex
, XM
}, PREFIX_DATA
},
7784 { "vpermd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
7788 { "vpsravd", { XM
, Vex
, EXx
}, PREFIX_DATA
},
7791 /* VEX_W_0F3849_X86_64_P_0 */
7792 { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_0_W_0
) },
7795 /* VEX_W_0F3849_X86_64_P_2 */
7796 { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_2_W_0
) },
7799 /* VEX_W_0F3849_X86_64_P_3 */
7800 { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_3_W_0
) },
7803 /* VEX_W_0F384B_X86_64_P_1 */
7804 { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_1_W_0
) },
7807 /* VEX_W_0F384B_X86_64_P_2 */
7808 { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_2_W_0
) },
7811 /* VEX_W_0F384B_X86_64_P_3 */
7812 { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_3_W_0
) },
7816 { "%XV vpdpbusd", { XM
, Vex
, EXx
}, 0 },
7820 { "%XV vpdpbusds", { XM
, Vex
, EXx
}, 0 },
7824 { "%XV vpdpwssd", { XM
, Vex
, EXx
}, 0 },
7828 { "%XV vpdpwssds", { XM
, Vex
, EXx
}, 0 },
7832 { "vpbroadcastd", { XM
, EXxmm_md
}, PREFIX_DATA
},
7836 { "vpbroadcastq", { XM
, EXxmm_mq
}, PREFIX_DATA
},
7839 /* VEX_W_0F385A_M_0_L_0 */
7840 { "vbroadcasti128", { XM
, Mxmm
}, PREFIX_DATA
},
7843 /* VEX_W_0F385C_X86_64_P_1 */
7844 { MOD_TABLE (MOD_VEX_0F385C_X86_64_P_1_W_0
) },
7847 /* VEX_W_0F385E_X86_64_P_0 */
7848 { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_0_W_0
) },
7851 /* VEX_W_0F385E_X86_64_P_1 */
7852 { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_1_W_0
) },
7855 /* VEX_W_0F385E_X86_64_P_2 */
7856 { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_2_W_0
) },
7859 /* VEX_W_0F385E_X86_64_P_3 */
7860 { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_3_W_0
) },
7864 { "vpbroadcastb", { XM
, EXxmm_mb
}, PREFIX_DATA
},
7868 { "vpbroadcastw", { XM
, EXxmm_mw
}, PREFIX_DATA
},
7872 { "vgf2p8mulb", { XM
, Vex
, EXx
}, PREFIX_DATA
},
7875 /* VEX_W_0F3A00_L_1 */
7877 { "vpermq", { XM
, EXx
, Ib
}, PREFIX_DATA
},
7880 /* VEX_W_0F3A01_L_1 */
7882 { "vpermpd", { XM
, EXx
, Ib
}, PREFIX_DATA
},
7886 { "vpblendd", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
7890 { "vpermilps", { XM
, EXx
, Ib
}, PREFIX_DATA
},
7894 { "vpermilpd", { XM
, EXx
, Ib
}, PREFIX_DATA
},
7897 /* VEX_W_0F3A06_L_1 */
7898 { "vperm2f128", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
7901 /* VEX_W_0F3A18_L_1 */
7902 { "vinsertf128", { XM
, Vex
, EXxmm
, Ib
}, PREFIX_DATA
},
7905 /* VEX_W_0F3A19_L_1 */
7906 { "vextractf128", { EXxmm
, XM
, Ib
}, PREFIX_DATA
},
7910 { "vcvtps2ph", { EXxmmq
, XM
, EXxEVexS
, Ib
}, PREFIX_DATA
},
7913 /* VEX_W_0F3A38_L_1 */
7914 { "vinserti128", { XM
, Vex
, EXxmm
, Ib
}, PREFIX_DATA
},
7917 /* VEX_W_0F3A39_L_1 */
7918 { "vextracti128", { EXxmm
, XM
, Ib
}, PREFIX_DATA
},
7921 /* VEX_W_0F3A46_L_1 */
7922 { "vperm2i128", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
7926 { "vblendvps", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
7930 { "vblendvpd", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
7934 { "vpblendvb", { XM
, Vex
, EXx
, XMVexI4
}, PREFIX_DATA
},
7939 { "vgf2p8affineqb", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
7944 { "vgf2p8affineinvqb", { XM
, Vex
, EXx
, Ib
}, PREFIX_DATA
},
7946 /* VEX_W_0FXOP_08_85_L_0 */
7948 { "vpmacssww", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7950 /* VEX_W_0FXOP_08_86_L_0 */
7952 { "vpmacsswd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7954 /* VEX_W_0FXOP_08_87_L_0 */
7956 { "vpmacssdql", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7958 /* VEX_W_0FXOP_08_8E_L_0 */
7960 { "vpmacssdd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7962 /* VEX_W_0FXOP_08_8F_L_0 */
7964 { "vpmacssdqh", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7966 /* VEX_W_0FXOP_08_95_L_0 */
7968 { "vpmacsww", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7970 /* VEX_W_0FXOP_08_96_L_0 */
7972 { "vpmacswd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7974 /* VEX_W_0FXOP_08_97_L_0 */
7976 { "vpmacsdql", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7978 /* VEX_W_0FXOP_08_9E_L_0 */
7980 { "vpmacsdd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7982 /* VEX_W_0FXOP_08_9F_L_0 */
7984 { "vpmacsdqh", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7986 /* VEX_W_0FXOP_08_A6_L_0 */
7988 { "vpmadcsswd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7990 /* VEX_W_0FXOP_08_B6_L_0 */
7992 { "vpmadcswd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
7994 /* VEX_W_0FXOP_08_C0_L_0 */
7996 { "vprotb", { XM
, EXx
, Ib
}, 0 },
7998 /* VEX_W_0FXOP_08_C1_L_0 */
8000 { "vprotw", { XM
, EXx
, Ib
}, 0 },
8002 /* VEX_W_0FXOP_08_C2_L_0 */
8004 { "vprotd", { XM
, EXx
, Ib
}, 0 },
8006 /* VEX_W_0FXOP_08_C3_L_0 */
8008 { "vprotq", { XM
, EXx
, Ib
}, 0 },
8010 /* VEX_W_0FXOP_08_CC_L_0 */
8012 { "vpcomb", { XM
, Vex
, EXx
, VPCOM
}, 0 },
8014 /* VEX_W_0FXOP_08_CD_L_0 */
8016 { "vpcomw", { XM
, Vex
, EXx
, VPCOM
}, 0 },
8018 /* VEX_W_0FXOP_08_CE_L_0 */
8020 { "vpcomd", { XM
, Vex
, EXx
, VPCOM
}, 0 },
8022 /* VEX_W_0FXOP_08_CF_L_0 */
8024 { "vpcomq", { XM
, Vex
, EXx
, VPCOM
}, 0 },
8026 /* VEX_W_0FXOP_08_EC_L_0 */
8028 { "vpcomub", { XM
, Vex
, EXx
, VPCOM
}, 0 },
8030 /* VEX_W_0FXOP_08_ED_L_0 */
8032 { "vpcomuw", { XM
, Vex
, EXx
, VPCOM
}, 0 },
8034 /* VEX_W_0FXOP_08_EE_L_0 */
8036 { "vpcomud", { XM
, Vex
, EXx
, VPCOM
}, 0 },
8038 /* VEX_W_0FXOP_08_EF_L_0 */
8040 { "vpcomuq", { XM
, Vex
, EXx
, VPCOM
}, 0 },
8042 /* VEX_W_0FXOP_09_80 */
8044 { "vfrczps", { XM
, EXx
}, 0 },
8046 /* VEX_W_0FXOP_09_81 */
8048 { "vfrczpd", { XM
, EXx
}, 0 },
8050 /* VEX_W_0FXOP_09_82 */
8052 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_82_W_0
) },
8054 /* VEX_W_0FXOP_09_83 */
8056 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_83_W_0
) },
8058 /* VEX_W_0FXOP_09_C1_L_0 */
8060 { "vphaddbw", { XM
, EXxmm
}, 0 },
8062 /* VEX_W_0FXOP_09_C2_L_0 */
8064 { "vphaddbd", { XM
, EXxmm
}, 0 },
8066 /* VEX_W_0FXOP_09_C3_L_0 */
8068 { "vphaddbq", { XM
, EXxmm
}, 0 },
8070 /* VEX_W_0FXOP_09_C6_L_0 */
8072 { "vphaddwd", { XM
, EXxmm
}, 0 },
8074 /* VEX_W_0FXOP_09_C7_L_0 */
8076 { "vphaddwq", { XM
, EXxmm
}, 0 },
8078 /* VEX_W_0FXOP_09_CB_L_0 */
8080 { "vphadddq", { XM
, EXxmm
}, 0 },
8082 /* VEX_W_0FXOP_09_D1_L_0 */
8084 { "vphaddubw", { XM
, EXxmm
}, 0 },
8086 /* VEX_W_0FXOP_09_D2_L_0 */
8088 { "vphaddubd", { XM
, EXxmm
}, 0 },
8090 /* VEX_W_0FXOP_09_D3_L_0 */
8092 { "vphaddubq", { XM
, EXxmm
}, 0 },
8094 /* VEX_W_0FXOP_09_D6_L_0 */
8096 { "vphadduwd", { XM
, EXxmm
}, 0 },
8098 /* VEX_W_0FXOP_09_D7_L_0 */
8100 { "vphadduwq", { XM
, EXxmm
}, 0 },
8102 /* VEX_W_0FXOP_09_DB_L_0 */
8104 { "vphaddudq", { XM
, EXxmm
}, 0 },
8106 /* VEX_W_0FXOP_09_E1_L_0 */
8108 { "vphsubbw", { XM
, EXxmm
}, 0 },
8110 /* VEX_W_0FXOP_09_E2_L_0 */
8112 { "vphsubwd", { XM
, EXxmm
}, 0 },
8114 /* VEX_W_0FXOP_09_E3_L_0 */
8116 { "vphsubdq", { XM
, EXxmm
}, 0 },
8119 #include "i386-dis-evex-w.h"
8122 static const struct dis386 mod_table
[][2] = {
8125 { "leaS", { Gv
, M
}, 0 },
8130 { RM_TABLE (RM_C6_REG_7
) },
8135 { RM_TABLE (RM_C7_REG_7
) },
8139 { "{l|}call^", { indirEp
}, 0 },
8143 { "{l|}jmp^", { indirEp
}, 0 },
8146 /* MOD_0F01_REG_0 */
8147 { X86_64_TABLE (X86_64_0F01_REG_0
) },
8148 { RM_TABLE (RM_0F01_REG_0
) },
8151 /* MOD_0F01_REG_1 */
8152 { X86_64_TABLE (X86_64_0F01_REG_1
) },
8153 { RM_TABLE (RM_0F01_REG_1
) },
8156 /* MOD_0F01_REG_2 */
8157 { X86_64_TABLE (X86_64_0F01_REG_2
) },
8158 { RM_TABLE (RM_0F01_REG_2
) },
8161 /* MOD_0F01_REG_3 */
8162 { X86_64_TABLE (X86_64_0F01_REG_3
) },
8163 { RM_TABLE (RM_0F01_REG_3
) },
8166 /* MOD_0F01_REG_5 */
8167 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0
) },
8168 { RM_TABLE (RM_0F01_REG_5_MOD_3
) },
8171 /* MOD_0F01_REG_7 */
8172 { "invlpg", { Mb
}, 0 },
8173 { RM_TABLE (RM_0F01_REG_7_MOD_3
) },
8176 /* MOD_0F12_PREFIX_0 */
8177 { "movlpX", { XM
, EXq
}, 0 },
8178 { "movhlps", { XM
, EXq
}, 0 },
8181 /* MOD_0F12_PREFIX_2 */
8182 { "movlpX", { XM
, EXq
}, 0 },
8186 { "movlpX", { EXq
, XM
}, PREFIX_OPCODE
},
8189 /* MOD_0F16_PREFIX_0 */
8190 { "movhpX", { XM
, EXq
}, 0 },
8191 { "movlhps", { XM
, EXq
}, 0 },
8194 /* MOD_0F16_PREFIX_2 */
8195 { "movhpX", { XM
, EXq
}, 0 },
8199 { "movhpX", { EXq
, XM
}, PREFIX_OPCODE
},
8202 /* MOD_0F18_REG_0 */
8203 { "prefetchnta", { Mb
}, 0 },
8206 /* MOD_0F18_REG_1 */
8207 { "prefetcht0", { Mb
}, 0 },
8210 /* MOD_0F18_REG_2 */
8211 { "prefetcht1", { Mb
}, 0 },
8214 /* MOD_0F18_REG_3 */
8215 { "prefetcht2", { Mb
}, 0 },
8218 /* MOD_0F18_REG_4 */
8219 { "nop/reserved", { Mb
}, 0 },
8222 /* MOD_0F18_REG_5 */
8223 { "nop/reserved", { Mb
}, 0 },
8226 /* MOD_0F18_REG_6 */
8227 { "nop/reserved", { Mb
}, 0 },
8230 /* MOD_0F18_REG_7 */
8231 { "nop/reserved", { Mb
}, 0 },
8234 /* MOD_0F1A_PREFIX_0 */
8235 { "bndldx", { Gbnd
, Mv_bnd
}, 0 },
8236 { "nopQ", { Ev
}, 0 },
8239 /* MOD_0F1B_PREFIX_0 */
8240 { "bndstx", { Mv_bnd
, Gbnd
}, 0 },
8241 { "nopQ", { Ev
}, 0 },
8244 /* MOD_0F1B_PREFIX_1 */
8245 { "bndmk", { Gbnd
, Mv_bnd
}, 0 },
8246 { "nopQ", { Ev
}, 0 },
8249 /* MOD_0F1C_PREFIX_0 */
8250 { REG_TABLE (REG_0F1C_P_0_MOD_0
) },
8251 { "nopQ", { Ev
}, 0 },
8254 /* MOD_0F1E_PREFIX_1 */
8255 { "nopQ", { Ev
}, 0 },
8256 { REG_TABLE (REG_0F1E_P_1_MOD_3
) },
8259 /* MOD_0F2B_PREFIX_0 */
8260 {"movntps", { Mx
, XM
}, PREFIX_OPCODE
},
8263 /* MOD_0F2B_PREFIX_1 */
8264 {"movntss", { Md
, XM
}, PREFIX_OPCODE
},
8267 /* MOD_0F2B_PREFIX_2 */
8268 {"movntpd", { Mx
, XM
}, PREFIX_OPCODE
},
8271 /* MOD_0F2B_PREFIX_3 */
8272 {"movntsd", { Mq
, XM
}, PREFIX_OPCODE
},
8277 { "movmskpX", { Gdq
, XS
}, PREFIX_OPCODE
},
8280 /* MOD_0F71_REG_2 */
8282 { "psrlw", { MS
, Ib
}, PREFIX_OPCODE
},
8285 /* MOD_0F71_REG_4 */
8287 { "psraw", { MS
, Ib
}, PREFIX_OPCODE
},
8290 /* MOD_0F71_REG_6 */
8292 { "psllw", { MS
, Ib
}, PREFIX_OPCODE
},
8295 /* MOD_0F72_REG_2 */
8297 { "psrld", { MS
, Ib
}, PREFIX_OPCODE
},
8300 /* MOD_0F72_REG_4 */
8302 { "psrad", { MS
, Ib
}, PREFIX_OPCODE
},
8305 /* MOD_0F72_REG_6 */
8307 { "pslld", { MS
, Ib
}, PREFIX_OPCODE
},
8310 /* MOD_0F73_REG_2 */
8312 { "psrlq", { MS
, Ib
}, PREFIX_OPCODE
},
8315 /* MOD_0F73_REG_3 */
8317 { "psrldq", { XS
, Ib
}, PREFIX_DATA
},
8320 /* MOD_0F73_REG_6 */
8322 { "psllq", { MS
, Ib
}, PREFIX_OPCODE
},
8325 /* MOD_0F73_REG_7 */
8327 { "pslldq", { XS
, Ib
}, PREFIX_DATA
},
8330 /* MOD_0FAE_REG_0 */
8331 { "fxsave", { FXSAVE
}, 0 },
8332 { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3
) },
8335 /* MOD_0FAE_REG_1 */
8336 { "fxrstor", { FXSAVE
}, 0 },
8337 { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3
) },
8340 /* MOD_0FAE_REG_2 */
8341 { "ldmxcsr", { Md
}, 0 },
8342 { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3
) },
8345 /* MOD_0FAE_REG_3 */
8346 { "stmxcsr", { Md
}, 0 },
8347 { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3
) },
8350 /* MOD_0FAE_REG_4 */
8351 { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0
) },
8352 { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3
) },
8355 /* MOD_0FAE_REG_5 */
8356 { "xrstor", { FXSAVE
}, PREFIX_OPCODE
},
8357 { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3
) },
8360 /* MOD_0FAE_REG_6 */
8361 { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0
) },
8362 { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3
) },
8365 /* MOD_0FAE_REG_7 */
8366 { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0
) },
8367 { RM_TABLE (RM_0FAE_REG_7_MOD_3
) },
8371 { "lssS", { Gv
, Mp
}, 0 },
8375 { "lfsS", { Gv
, Mp
}, 0 },
8379 { "lgsS", { Gv
, Mp
}, 0 },
8383 { "movntiS", { Edq
, Gdq
}, PREFIX_OPCODE
},
8386 /* MOD_0FC7_REG_3 */
8387 { "xrstors", { FXSAVE
}, 0 },
8390 /* MOD_0FC7_REG_4 */
8391 { "xsavec", { FXSAVE
}, 0 },
8394 /* MOD_0FC7_REG_5 */
8395 { "xsaves", { FXSAVE
}, 0 },
8398 /* MOD_0FC7_REG_6 */
8399 { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0
) },
8400 { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3
) }
8403 /* MOD_0FC7_REG_7 */
8404 { "vmptrst", { Mq
}, 0 },
8405 { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3
) }
8410 { "pmovmskb", { Gdq
, MS
}, 0 },
8413 /* MOD_0FE7_PREFIX_2 */
8414 { "movntdq", { Mx
, XM
}, 0 },
8417 /* MOD_0FF0_PREFIX_3 */
8418 { "lddqu", { XM
, M
}, 0 },
8422 { "movntdqa", { XM
, Mx
}, PREFIX_DATA
},
8425 /* MOD_0F38DC_PREFIX_1 */
8426 { "aesenc128kl", { XM
, M
}, 0 },
8427 { "loadiwkey", { XM
, EXx
}, 0 },
8430 /* MOD_0F38DD_PREFIX_1 */
8431 { "aesdec128kl", { XM
, M
}, 0 },
8434 /* MOD_0F38DE_PREFIX_1 */
8435 { "aesenc256kl", { XM
, M
}, 0 },
8438 /* MOD_0F38DF_PREFIX_1 */
8439 { "aesdec256kl", { XM
, M
}, 0 },
8443 { "wrussK", { M
, Gdq
}, PREFIX_DATA
},
8446 /* MOD_0F38F6_PREFIX_0 */
8447 { "wrssK", { M
, Gdq
}, PREFIX_OPCODE
},
8450 /* MOD_0F38F8_PREFIX_1 */
8451 { "enqcmds", { Gva
, M
}, PREFIX_OPCODE
},
8454 /* MOD_0F38F8_PREFIX_2 */
8455 { "movdir64b", { Gva
, M
}, PREFIX_OPCODE
},
8458 /* MOD_0F38F8_PREFIX_3 */
8459 { "enqcmd", { Gva
, M
}, PREFIX_OPCODE
},
8463 { "movdiri", { Edq
, Gdq
}, PREFIX_OPCODE
},
8466 /* MOD_0F38FA_PREFIX_1 */
8468 { "encodekey128", { Gd
, Ed
}, 0 },
8471 /* MOD_0F38FB_PREFIX_1 */
8473 { "encodekey256", { Gd
, Ed
}, 0 },
8476 /* MOD_0F3A0F_PREFIX_1 */
8478 { REG_TABLE (REG_0F3A0F_PREFIX_1_MOD_3
) },
8482 { "bound{S|}", { Gv
, Ma
}, 0 },
8483 { EVEX_TABLE (EVEX_0F
) },
8487 { "lesS", { Gv
, Mp
}, 0 },
8488 { VEX_C4_TABLE (VEX_0F
) },
8492 { "ldsS", { Gv
, Mp
}, 0 },
8493 { VEX_C5_TABLE (VEX_0F
) },
8496 /* MOD_VEX_0F12_PREFIX_0 */
8497 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0
) },
8498 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1
) },
8501 /* MOD_VEX_0F12_PREFIX_2 */
8502 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2_M_0
) },
8506 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0
) },
8509 /* MOD_VEX_0F16_PREFIX_0 */
8510 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0
) },
8511 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1
) },
8514 /* MOD_VEX_0F16_PREFIX_2 */
8515 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2_M_0
) },
8519 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0
) },
8523 { "vmovntpX", { Mx
, XM
}, PREFIX_OPCODE
},
8526 /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
8528 { "kandw", { MaskG
, MaskVex
, MaskE
}, 0 },
8531 /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
8533 { "kandq", { MaskG
, MaskVex
, MaskE
}, 0 },
8536 /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
8538 { "kandb", { MaskG
, MaskVex
, MaskE
}, 0 },
8541 /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
8543 { "kandd", { MaskG
, MaskVex
, MaskE
}, 0 },
8546 /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
8548 { "kandnw", { MaskG
, MaskVex
, MaskE
}, 0 },
8551 /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
8553 { "kandnq", { MaskG
, MaskVex
, MaskE
}, 0 },
8556 /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
8558 { "kandnb", { MaskG
, MaskVex
, MaskE
}, 0 },
8561 /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
8563 { "kandnd", { MaskG
, MaskVex
, MaskE
}, 0 },
8566 /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
8568 { "knotw", { MaskG
, MaskE
}, 0 },
8571 /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
8573 { "knotq", { MaskG
, MaskE
}, 0 },
8576 /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
8578 { "knotb", { MaskG
, MaskE
}, 0 },
8581 /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
8583 { "knotd", { MaskG
, MaskE
}, 0 },
8586 /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
8588 { "korw", { MaskG
, MaskVex
, MaskE
}, 0 },
8591 /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
8593 { "korq", { MaskG
, MaskVex
, MaskE
}, 0 },
8596 /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
8598 { "korb", { MaskG
, MaskVex
, MaskE
}, 0 },
8601 /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
8603 { "kord", { MaskG
, MaskVex
, MaskE
}, 0 },
8606 /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
8608 { "kxnorw", { MaskG
, MaskVex
, MaskE
}, 0 },
8611 /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
8613 { "kxnorq", { MaskG
, MaskVex
, MaskE
}, 0 },
8616 /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
8618 { "kxnorb", { MaskG
, MaskVex
, MaskE
}, 0 },
8621 /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
8623 { "kxnord", { MaskG
, MaskVex
, MaskE
}, 0 },
8626 /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
8628 { "kxorw", { MaskG
, MaskVex
, MaskE
}, 0 },
8631 /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
8633 { "kxorq", { MaskG
, MaskVex
, MaskE
}, 0 },
8636 /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
8638 { "kxorb", { MaskG
, MaskVex
, MaskE
}, 0 },
8641 /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
8643 { "kxord", { MaskG
, MaskVex
, MaskE
}, 0 },
8646 /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
8648 { "kaddw", { MaskG
, MaskVex
, MaskE
}, 0 },
8651 /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
8653 { "kaddq", { MaskG
, MaskVex
, MaskE
}, 0 },
8656 /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
8658 { "kaddb", { MaskG
, MaskVex
, MaskE
}, 0 },
8661 /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
8663 { "kaddd", { MaskG
, MaskVex
, MaskE
}, 0 },
8666 /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
8668 { "kunpckwd", { MaskG
, MaskVex
, MaskE
}, 0 },
8671 /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
8673 { "kunpckdq", { MaskG
, MaskVex
, MaskE
}, 0 },
8676 /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
8678 { "kunpckbw", { MaskG
, MaskVex
, MaskE
}, 0 },
8683 { "vmovmskpX", { Gdq
, XS
}, PREFIX_OPCODE
},
8686 /* MOD_VEX_0F71_REG_2 */
8688 { "vpsrlw", { Vex
, XS
, Ib
}, PREFIX_DATA
},
8691 /* MOD_VEX_0F71_REG_4 */
8693 { "vpsraw", { Vex
, XS
, Ib
}, PREFIX_DATA
},
8696 /* MOD_VEX_0F71_REG_6 */
8698 { "vpsllw", { Vex
, XS
, Ib
}, PREFIX_DATA
},
8701 /* MOD_VEX_0F72_REG_2 */
8703 { "vpsrld", { Vex
, XS
, Ib
}, PREFIX_DATA
},
8706 /* MOD_VEX_0F72_REG_4 */
8708 { "vpsrad", { Vex
, XS
, Ib
}, PREFIX_DATA
},
8711 /* MOD_VEX_0F72_REG_6 */
8713 { "vpslld", { Vex
, XS
, Ib
}, PREFIX_DATA
},
8716 /* MOD_VEX_0F73_REG_2 */
8718 { "vpsrlq", { Vex
, XS
, Ib
}, PREFIX_DATA
},
8721 /* MOD_VEX_0F73_REG_3 */
8723 { "vpsrldq", { Vex
, XS
, Ib
}, PREFIX_DATA
},
8726 /* MOD_VEX_0F73_REG_6 */
8728 { "vpsllq", { Vex
, XS
, Ib
}, PREFIX_DATA
},
8731 /* MOD_VEX_0F73_REG_7 */
8733 { "vpslldq", { Vex
, XS
, Ib
}, PREFIX_DATA
},
8736 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
8737 { "kmovw", { Ew
, MaskG
}, 0 },
8741 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
8742 { "kmovq", { Eq
, MaskG
}, 0 },
8746 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
8747 { "kmovb", { Eb
, MaskG
}, 0 },
8751 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
8752 { "kmovd", { Ed
, MaskG
}, 0 },
8756 /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
8758 { "kmovw", { MaskG
, Edq
}, 0 },
8761 /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
8763 { "kmovb", { MaskG
, Edq
}, 0 },
8766 /* MOD_VEX_0F92_P_3_LEN_0 */
8768 { "kmovK", { MaskG
, Edq
}, 0 },
8771 /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
8773 { "kmovw", { Gdq
, MaskE
}, 0 },
8776 /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
8778 { "kmovb", { Gdq
, MaskE
}, 0 },
8781 /* MOD_VEX_0F93_P_3_LEN_0 */
8783 { "kmovK", { Gdq
, MaskE
}, 0 },
8786 /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
8788 { "kortestw", { MaskG
, MaskE
}, 0 },
8791 /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
8793 { "kortestq", { MaskG
, MaskE
}, 0 },
8796 /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
8798 { "kortestb", { MaskG
, MaskE
}, 0 },
8801 /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
8803 { "kortestd", { MaskG
, MaskE
}, 0 },
8806 /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
8808 { "ktestw", { MaskG
, MaskE
}, 0 },
8811 /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
8813 { "ktestq", { MaskG
, MaskE
}, 0 },
8816 /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
8818 { "ktestb", { MaskG
, MaskE
}, 0 },
8821 /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
8823 { "ktestd", { MaskG
, MaskE
}, 0 },
8826 /* MOD_VEX_0FAE_REG_2 */
8827 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0
) },
8830 /* MOD_VEX_0FAE_REG_3 */
8831 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0
) },
8836 { "vpmovmskb", { Gdq
, XS
}, PREFIX_DATA
},
8840 { "vmovntdq", { Mx
, XM
}, PREFIX_DATA
},
8843 /* MOD_VEX_0FF0_PREFIX_3 */
8844 { "vlddqu", { XM
, M
}, 0 },
8847 /* MOD_VEX_0F381A */
8848 { VEX_LEN_TABLE (VEX_LEN_0F381A_M_0
) },
8851 /* MOD_VEX_0F382A */
8852 { "vmovntdqa", { XM
, Mx
}, PREFIX_DATA
},
8855 /* MOD_VEX_0F382C */
8856 { VEX_W_TABLE (VEX_W_0F382C_M_0
) },
8859 /* MOD_VEX_0F382D */
8860 { VEX_W_TABLE (VEX_W_0F382D_M_0
) },
8863 /* MOD_VEX_0F382E */
8864 { VEX_W_TABLE (VEX_W_0F382E_M_0
) },
8867 /* MOD_VEX_0F382F */
8868 { VEX_W_TABLE (VEX_W_0F382F_M_0
) },
8871 /* MOD_VEX_0F3849_X86_64_P_0_W_0 */
8872 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0
) },
8873 { REG_TABLE (REG_VEX_0F3849_X86_64_P_0_W_0_M_1
) },
8876 /* MOD_VEX_0F3849_X86_64_P_2_W_0 */
8877 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0
) },
8880 /* MOD_VEX_0F3849_X86_64_P_3_W_0 */
8882 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0
) },
8885 /* MOD_VEX_0F384B_X86_64_P_1_W_0 */
8886 { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0
) },
8889 /* MOD_VEX_0F384B_X86_64_P_2_W_0 */
8890 { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0
) },
8893 /* MOD_VEX_0F384B_X86_64_P_3_W_0 */
8894 { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0
) },
8897 /* MOD_VEX_0F385A */
8898 { VEX_LEN_TABLE (VEX_LEN_0F385A_M_0
) },
8901 /* MOD_VEX_0F385C_X86_64_P_1_W_0 */
8903 { VEX_LEN_TABLE (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0
) },
8906 /* MOD_VEX_0F385E_X86_64_P_0_W_0 */
8908 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0
) },
8911 /* MOD_VEX_0F385E_X86_64_P_1_W_0 */
8913 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0
) },
8916 /* MOD_VEX_0F385E_X86_64_P_2_W_0 */
8918 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0
) },
8921 /* MOD_VEX_0F385E_X86_64_P_3_W_0 */
8923 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0
) },
8926 /* MOD_VEX_0F388C */
8927 { "vpmaskmov%DQ", { XM
, Vex
, Mx
}, PREFIX_DATA
},
8930 /* MOD_VEX_0F388E */
8931 { "vpmaskmov%DQ", { Mx
, Vex
, XM
}, PREFIX_DATA
},
8934 /* MOD_VEX_0F3A30_L_0 */
8936 { "kshiftr%BW", { MaskG
, MaskE
, Ib
}, PREFIX_DATA
},
8939 /* MOD_VEX_0F3A31_L_0 */
8941 { "kshiftr%DQ", { MaskG
, MaskE
, Ib
}, PREFIX_DATA
},
8944 /* MOD_VEX_0F3A32_L_0 */
8946 { "kshiftl%BW", { MaskG
, MaskE
, Ib
}, PREFIX_DATA
},
8949 /* MOD_VEX_0F3A33_L_0 */
8951 { "kshiftl%DQ", { MaskG
, MaskE
, Ib
}, PREFIX_DATA
},
8954 /* MOD_VEX_0FXOP_09_12 */
8956 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_12_M_1
) },
8959 #include "i386-dis-evex-mod.h"
8962 static const struct dis386 rm_table
[][8] = {
8965 { "xabort", { Skip_MODRM
, Ib
}, 0 },
8969 { "xbeginT", { Skip_MODRM
, Jdqw
}, 0 },
8973 { "enclv", { Skip_MODRM
}, 0 },
8974 { "vmcall", { Skip_MODRM
}, 0 },
8975 { "vmlaunch", { Skip_MODRM
}, 0 },
8976 { "vmresume", { Skip_MODRM
}, 0 },
8977 { "vmxoff", { Skip_MODRM
}, 0 },
8978 { "pconfig", { Skip_MODRM
}, 0 },
8982 { "monitor", { { OP_Monitor
, 0 } }, 0 },
8983 { "mwait", { { OP_Mwait
, 0 } }, 0 },
8984 { "clac", { Skip_MODRM
}, 0 },
8985 { "stac", { Skip_MODRM
}, 0 },
8986 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_4
) },
8987 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_5
) },
8988 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_6
) },
8989 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_7
) },
8993 { "xgetbv", { Skip_MODRM
}, 0 },
8994 { "xsetbv", { Skip_MODRM
}, 0 },
8997 { "vmfunc", { Skip_MODRM
}, 0 },
8998 { "xend", { Skip_MODRM
}, 0 },
8999 { "xtest", { Skip_MODRM
}, 0 },
9000 { "enclu", { Skip_MODRM
}, 0 },
9004 { "vmrun", { Skip_MODRM
}, 0 },
9005 { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1
) },
9006 { "vmload", { Skip_MODRM
}, 0 },
9007 { "vmsave", { Skip_MODRM
}, 0 },
9008 { "stgi", { Skip_MODRM
}, 0 },
9009 { "clgi", { Skip_MODRM
}, 0 },
9010 { "skinit", { Skip_MODRM
}, 0 },
9011 { "invlpga", { Skip_MODRM
}, 0 },
9014 /* RM_0F01_REG_5_MOD_3 */
9015 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0
) },
9016 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1
) },
9017 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2
) },
9019 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_4
) },
9020 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_5
) },
9021 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_6
) },
9022 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_7
) },
9025 /* RM_0F01_REG_7_MOD_3 */
9026 { "swapgs", { Skip_MODRM
}, 0 },
9027 { "rdtscp", { Skip_MODRM
}, 0 },
9028 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2
) },
9029 { "mwaitx", { { OP_Mwait
, eBX_reg
} }, PREFIX_OPCODE
},
9030 { "clzero", { Skip_MODRM
}, 0 },
9031 { "rdpru", { Skip_MODRM
}, 0 },
9032 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_6
) },
9033 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_7
) },
9036 /* RM_0F1E_P_1_MOD_3_REG_7 */
9037 { "nopQ", { Ev
}, 0 },
9038 { "nopQ", { Ev
}, 0 },
9039 { "endbr64", { Skip_MODRM
}, PREFIX_OPCODE
},
9040 { "endbr32", { Skip_MODRM
}, PREFIX_OPCODE
},
9041 { "nopQ", { Ev
}, 0 },
9042 { "nopQ", { Ev
}, 0 },
9043 { "nopQ", { Ev
}, 0 },
9044 { "nopQ", { Ev
}, 0 },
9047 /* RM_0F3A0F_P_1_MOD_3_REG_0 */
9048 { "hreset", { Skip_MODRM
, Ib
}, 0 },
9051 /* RM_0FAE_REG_6_MOD_3 */
9052 { "mfence", { Skip_MODRM
}, 0 },
9055 /* RM_0FAE_REG_7_MOD_3 */
9056 { "sfence", { Skip_MODRM
}, 0 },
9060 /* RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0 */
9061 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0
) },
9065 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
9067 /* We use the high bit to indicate different name for the same
9069 #define REP_PREFIX (0xf3 | 0x100)
9070 #define XACQUIRE_PREFIX (0xf2 | 0x200)
9071 #define XRELEASE_PREFIX (0xf3 | 0x400)
9072 #define BND_PREFIX (0xf2 | 0x400)
9073 #define NOTRACK_PREFIX (0x3e | 0x100)
9075 /* Remember if the current op is a jump instruction. */
9076 static bfd_boolean op_is_jump
= FALSE
;
9081 int newrex
, i
, length
;
9086 last_lock_prefix
= -1;
9087 last_repz_prefix
= -1;
9088 last_repnz_prefix
= -1;
9089 last_data_prefix
= -1;
9090 last_addr_prefix
= -1;
9091 last_rex_prefix
= -1;
9092 last_seg_prefix
= -1;
9094 active_seg_prefix
= 0;
9095 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
9096 all_prefixes
[i
] = 0;
9099 /* The maximum instruction length is 15bytes. */
9100 while (length
< MAX_CODE_LENGTH
- 1)
9102 FETCH_DATA (the_info
, codep
+ 1);
9106 /* REX prefixes family. */
9123 if (address_mode
== mode_64bit
)
9127 last_rex_prefix
= i
;
9130 prefixes
|= PREFIX_REPZ
;
9131 last_repz_prefix
= i
;
9134 prefixes
|= PREFIX_REPNZ
;
9135 last_repnz_prefix
= i
;
9138 prefixes
|= PREFIX_LOCK
;
9139 last_lock_prefix
= i
;
9142 prefixes
|= PREFIX_CS
;
9143 last_seg_prefix
= i
;
9145 if (address_mode
!= mode_64bit
)
9146 active_seg_prefix
= PREFIX_CS
;
9150 prefixes
|= PREFIX_SS
;
9151 last_seg_prefix
= i
;
9153 if (address_mode
!= mode_64bit
)
9154 active_seg_prefix
= PREFIX_SS
;
9158 prefixes
|= PREFIX_DS
;
9159 last_seg_prefix
= i
;
9161 if (address_mode
!= mode_64bit
)
9162 active_seg_prefix
= PREFIX_DS
;
9166 prefixes
|= PREFIX_ES
;
9167 last_seg_prefix
= i
;
9169 if (address_mode
!= mode_64bit
)
9170 active_seg_prefix
= PREFIX_ES
;
9174 prefixes
|= PREFIX_FS
;
9175 last_seg_prefix
= i
;
9176 active_seg_prefix
= PREFIX_FS
;
9179 prefixes
|= PREFIX_GS
;
9180 last_seg_prefix
= i
;
9181 active_seg_prefix
= PREFIX_GS
;
9184 prefixes
|= PREFIX_DATA
;
9185 last_data_prefix
= i
;
9188 prefixes
|= PREFIX_ADDR
;
9189 last_addr_prefix
= i
;
9192 /* fwait is really an instruction. If there are prefixes
9193 before the fwait, they belong to the fwait, *not* to the
9194 following instruction. */
9196 if (prefixes
|| rex
)
9198 prefixes
|= PREFIX_FWAIT
;
9200 /* This ensures that the previous REX prefixes are noticed
9201 as unused prefixes, as in the return case below. */
9205 prefixes
= PREFIX_FWAIT
;
9210 /* Rex is ignored when followed by another prefix. */
9216 if (*codep
!= FWAIT_OPCODE
)
9217 all_prefixes
[i
++] = *codep
;
9225 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
9229 prefix_name (int pref
, int sizeflag
)
9231 static const char *rexes
[16] =
9236 "rex.XB", /* 0x43 */
9238 "rex.RB", /* 0x45 */
9239 "rex.RX", /* 0x46 */
9240 "rex.RXB", /* 0x47 */
9242 "rex.WB", /* 0x49 */
9243 "rex.WX", /* 0x4a */
9244 "rex.WXB", /* 0x4b */
9245 "rex.WR", /* 0x4c */
9246 "rex.WRB", /* 0x4d */
9247 "rex.WRX", /* 0x4e */
9248 "rex.WRXB", /* 0x4f */
9253 /* REX prefixes family. */
9270 return rexes
[pref
- 0x40];
9290 return (sizeflag
& DFLAG
) ? "data16" : "data32";
9292 if (address_mode
== mode_64bit
)
9293 return (sizeflag
& AFLAG
) ? "addr32" : "addr64";
9295 return (sizeflag
& AFLAG
) ? "addr16" : "addr32";
9300 case XACQUIRE_PREFIX
:
9302 case XRELEASE_PREFIX
:
9306 case NOTRACK_PREFIX
:
9313 static char op_out
[MAX_OPERANDS
][100];
9314 static int op_ad
, op_index
[MAX_OPERANDS
];
9315 static int two_source_ops
;
9316 static bfd_vma op_address
[MAX_OPERANDS
];
9317 static bfd_vma op_riprel
[MAX_OPERANDS
];
9318 static bfd_vma start_pc
;
9321 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
9322 * (see topic "Redundant prefixes" in the "Differences from 8086"
9323 * section of the "Virtual 8086 Mode" chapter.)
9324 * 'pc' should be the address of this instruction, it will
9325 * be used to print the target address if this is a relative jump or call
9326 * The function returns the length of this instruction in bytes.
9329 static char intel_syntax
;
9330 static char intel_mnemonic
= !SYSV386_COMPAT
;
9331 static char open_char
;
9332 static char close_char
;
9333 static char separator_char
;
9334 static char scale_char
;
9342 static enum x86_64_isa isa64
;
9344 /* Here for backwards compatibility. When gdb stops using
9345 print_insn_i386_att and print_insn_i386_intel these functions can
9346 disappear, and print_insn_i386 be merged into print_insn. */
9348 print_insn_i386_att (bfd_vma pc
, disassemble_info
*info
)
9352 return print_insn (pc
, info
);
9356 print_insn_i386_intel (bfd_vma pc
, disassemble_info
*info
)
9360 return print_insn (pc
, info
);
9364 print_insn_i386 (bfd_vma pc
, disassemble_info
*info
)
9368 return print_insn (pc
, info
);
9372 print_i386_disassembler_options (FILE *stream
)
9374 fprintf (stream
, _("\n\
9375 The following i386/x86-64 specific disassembler options are supported for use\n\
9376 with the -M switch (multiple options should be separated by commas):\n"));
9378 fprintf (stream
, _(" x86-64 Disassemble in 64bit mode\n"));
9379 fprintf (stream
, _(" i386 Disassemble in 32bit mode\n"));
9380 fprintf (stream
, _(" i8086 Disassemble in 16bit mode\n"));
9381 fprintf (stream
, _(" att Display instruction in AT&T syntax\n"));
9382 fprintf (stream
, _(" intel Display instruction in Intel syntax\n"));
9383 fprintf (stream
, _(" att-mnemonic\n"
9384 " Display instruction in AT&T mnemonic\n"));
9385 fprintf (stream
, _(" intel-mnemonic\n"
9386 " Display instruction in Intel mnemonic\n"));
9387 fprintf (stream
, _(" addr64 Assume 64bit address size\n"));
9388 fprintf (stream
, _(" addr32 Assume 32bit address size\n"));
9389 fprintf (stream
, _(" addr16 Assume 16bit address size\n"));
9390 fprintf (stream
, _(" data32 Assume 32bit data size\n"));
9391 fprintf (stream
, _(" data16 Assume 16bit data size\n"));
9392 fprintf (stream
, _(" suffix Always display instruction suffix in AT&T syntax\n"));
9393 fprintf (stream
, _(" amd64 Display instruction in AMD64 ISA\n"));
9394 fprintf (stream
, _(" intel64 Display instruction in Intel64 ISA\n"));
9398 static const struct dis386 bad_opcode
= { "(bad)", { XX
}, 0 };
9400 /* Get a pointer to struct dis386 with a valid name. */
9402 static const struct dis386
*
9403 get_valid_dis386 (const struct dis386
*dp
, disassemble_info
*info
)
9405 int vindex
, vex_table_index
;
9407 if (dp
->name
!= NULL
)
9410 switch (dp
->op
[0].bytemode
)
9413 dp
= ®_table
[dp
->op
[1].bytemode
][modrm
.reg
];
9417 vindex
= modrm
.mod
== 0x3 ? 1 : 0;
9418 dp
= &mod_table
[dp
->op
[1].bytemode
][vindex
];
9422 dp
= &rm_table
[dp
->op
[1].bytemode
][modrm
.rm
];
9425 case USE_PREFIX_TABLE
:
9428 /* The prefix in VEX is implicit. */
9434 case REPE_PREFIX_OPCODE
:
9437 case DATA_PREFIX_OPCODE
:
9440 case REPNE_PREFIX_OPCODE
:
9450 int last_prefix
= -1;
9453 /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
9454 When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
9456 if ((prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0)
9458 if (last_repz_prefix
> last_repnz_prefix
)
9461 prefix
= PREFIX_REPZ
;
9462 last_prefix
= last_repz_prefix
;
9467 prefix
= PREFIX_REPNZ
;
9468 last_prefix
= last_repnz_prefix
;
9471 /* Check if prefix should be ignored. */
9472 if ((((prefix_table
[dp
->op
[1].bytemode
][vindex
].prefix_requirement
9473 & PREFIX_IGNORED
) >> PREFIX_IGNORED_SHIFT
)
9478 if (vindex
== 0 && (prefixes
& PREFIX_DATA
) != 0)
9481 prefix
= PREFIX_DATA
;
9482 last_prefix
= last_data_prefix
;
9487 used_prefixes
|= prefix
;
9488 all_prefixes
[last_prefix
] = 0;
9491 dp
= &prefix_table
[dp
->op
[1].bytemode
][vindex
];
9494 case USE_X86_64_TABLE
:
9495 vindex
= address_mode
== mode_64bit
? 1 : 0;
9496 dp
= &x86_64_table
[dp
->op
[1].bytemode
][vindex
];
9499 case USE_3BYTE_TABLE
:
9500 FETCH_DATA (info
, codep
+ 2);
9502 dp
= &three_byte_table
[dp
->op
[1].bytemode
][vindex
];
9504 modrm
.mod
= (*codep
>> 6) & 3;
9505 modrm
.reg
= (*codep
>> 3) & 7;
9506 modrm
.rm
= *codep
& 7;
9509 case USE_VEX_LEN_TABLE
:
9526 dp
= &vex_len_table
[dp
->op
[1].bytemode
][vindex
];
9529 case USE_EVEX_LEN_TABLE
:
9549 dp
= &evex_len_table
[dp
->op
[1].bytemode
][vindex
];
9552 case USE_XOP_8F_TABLE
:
9553 FETCH_DATA (info
, codep
+ 3);
9554 rex
= ~(*codep
>> 5) & 0x7;
9556 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
9557 switch ((*codep
& 0x1f))
9563 vex_table_index
= XOP_08
;
9566 vex_table_index
= XOP_09
;
9569 vex_table_index
= XOP_0A
;
9573 vex
.w
= *codep
& 0x80;
9574 if (vex
.w
&& address_mode
== mode_64bit
)
9577 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
9578 if (address_mode
!= mode_64bit
)
9580 /* In 16/32-bit mode REX_B is silently ignored. */
9584 vex
.length
= (*codep
& 0x4) ? 256 : 128;
9585 switch ((*codep
& 0x3))
9590 vex
.prefix
= DATA_PREFIX_OPCODE
;
9593 vex
.prefix
= REPE_PREFIX_OPCODE
;
9596 vex
.prefix
= REPNE_PREFIX_OPCODE
;
9602 dp
= &xop_table
[vex_table_index
][vindex
];
9605 FETCH_DATA (info
, codep
+ 1);
9606 modrm
.mod
= (*codep
>> 6) & 3;
9607 modrm
.reg
= (*codep
>> 3) & 7;
9608 modrm
.rm
= *codep
& 7;
9610 /* No XOP encoding so far allows for a non-zero embedded prefix. Avoid
9611 having to decode the bits for every otherwise valid encoding. */
9616 case USE_VEX_C4_TABLE
:
9618 FETCH_DATA (info
, codep
+ 3);
9619 rex
= ~(*codep
>> 5) & 0x7;
9620 switch ((*codep
& 0x1f))
9626 vex_table_index
= VEX_0F
;
9629 vex_table_index
= VEX_0F38
;
9632 vex_table_index
= VEX_0F3A
;
9636 vex
.w
= *codep
& 0x80;
9637 if (address_mode
== mode_64bit
)
9644 /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
9645 is ignored, other REX bits are 0 and the highest bit in
9646 VEX.vvvv is also ignored (but we mustn't clear it here). */
9649 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
9650 vex
.length
= (*codep
& 0x4) ? 256 : 128;
9651 switch ((*codep
& 0x3))
9656 vex
.prefix
= DATA_PREFIX_OPCODE
;
9659 vex
.prefix
= REPE_PREFIX_OPCODE
;
9662 vex
.prefix
= REPNE_PREFIX_OPCODE
;
9668 dp
= &vex_table
[vex_table_index
][vindex
];
9670 /* There is no MODRM byte for VEX0F 77. */
9671 if (vex_table_index
!= VEX_0F
|| vindex
!= 0x77)
9673 FETCH_DATA (info
, codep
+ 1);
9674 modrm
.mod
= (*codep
>> 6) & 3;
9675 modrm
.reg
= (*codep
>> 3) & 7;
9676 modrm
.rm
= *codep
& 7;
9680 case USE_VEX_C5_TABLE
:
9682 FETCH_DATA (info
, codep
+ 2);
9683 rex
= (*codep
& 0x80) ? 0 : REX_R
;
9685 /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
9687 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
9688 vex
.length
= (*codep
& 0x4) ? 256 : 128;
9689 switch ((*codep
& 0x3))
9694 vex
.prefix
= DATA_PREFIX_OPCODE
;
9697 vex
.prefix
= REPE_PREFIX_OPCODE
;
9700 vex
.prefix
= REPNE_PREFIX_OPCODE
;
9706 dp
= &vex_table
[dp
->op
[1].bytemode
][vindex
];
9708 /* There is no MODRM byte for VEX 77. */
9711 FETCH_DATA (info
, codep
+ 1);
9712 modrm
.mod
= (*codep
>> 6) & 3;
9713 modrm
.reg
= (*codep
>> 3) & 7;
9714 modrm
.rm
= *codep
& 7;
9718 case USE_VEX_W_TABLE
:
9722 dp
= &vex_w_table
[dp
->op
[1].bytemode
][vex
.w
? 1 : 0];
9725 case USE_EVEX_TABLE
:
9729 FETCH_DATA (info
, codep
+ 4);
9730 /* The first byte after 0x62. */
9731 rex
= ~(*codep
>> 5) & 0x7;
9732 vex
.r
= *codep
& 0x10;
9733 switch ((*codep
& 0xf))
9738 vex_table_index
= EVEX_0F
;
9741 vex_table_index
= EVEX_0F38
;
9744 vex_table_index
= EVEX_0F3A
;
9748 /* The second byte after 0x62. */
9750 vex
.w
= *codep
& 0x80;
9751 if (vex
.w
&& address_mode
== mode_64bit
)
9754 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
9757 if (!(*codep
& 0x4))
9760 switch ((*codep
& 0x3))
9765 vex
.prefix
= DATA_PREFIX_OPCODE
;
9768 vex
.prefix
= REPE_PREFIX_OPCODE
;
9771 vex
.prefix
= REPNE_PREFIX_OPCODE
;
9775 /* The third byte after 0x62. */
9778 /* Remember the static rounding bits. */
9779 vex
.ll
= (*codep
>> 5) & 3;
9780 vex
.b
= (*codep
& 0x10) != 0;
9782 vex
.v
= *codep
& 0x8;
9783 vex
.mask_register_specifier
= *codep
& 0x7;
9784 vex
.zeroing
= *codep
& 0x80;
9786 if (address_mode
!= mode_64bit
)
9788 /* In 16/32-bit mode silently ignore following bits. */
9797 dp
= &evex_table
[vex_table_index
][vindex
];
9799 FETCH_DATA (info
, codep
+ 1);
9800 modrm
.mod
= (*codep
>> 6) & 3;
9801 modrm
.reg
= (*codep
>> 3) & 7;
9802 modrm
.rm
= *codep
& 7;
9804 /* Set vector length. */
9805 if (modrm
.mod
== 3 && vex
.b
)
9834 if (dp
->name
!= NULL
)
9837 return get_valid_dis386 (dp
, info
);
9841 get_sib (disassemble_info
*info
, int sizeflag
)
9843 /* If modrm.mod == 3, operand must be register. */
9845 && ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
9849 FETCH_DATA (info
, codep
+ 2);
9850 sib
.index
= (codep
[1] >> 3) & 7;
9851 sib
.scale
= (codep
[1] >> 6) & 3;
9852 sib
.base
= codep
[1] & 7;
9857 print_insn (bfd_vma pc
, disassemble_info
*info
)
9859 const struct dis386
*dp
;
9861 char *op_txt
[MAX_OPERANDS
];
9863 int sizeflag
, orig_sizeflag
;
9865 struct dis_private priv
;
9868 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
9869 if ((info
->mach
& bfd_mach_i386_i386
) != 0)
9870 address_mode
= mode_32bit
;
9871 else if (info
->mach
== bfd_mach_i386_i8086
)
9873 address_mode
= mode_16bit
;
9874 priv
.orig_sizeflag
= 0;
9877 address_mode
= mode_64bit
;
9879 if (intel_syntax
== (char) -1)
9880 intel_syntax
= (info
->mach
& bfd_mach_i386_intel_syntax
) != 0;
9882 for (p
= info
->disassembler_options
; p
!= NULL
; )
9884 if (CONST_STRNEQ (p
, "amd64"))
9886 else if (CONST_STRNEQ (p
, "intel64"))
9888 else if (CONST_STRNEQ (p
, "x86-64"))
9890 address_mode
= mode_64bit
;
9891 priv
.orig_sizeflag
|= AFLAG
| DFLAG
;
9893 else if (CONST_STRNEQ (p
, "i386"))
9895 address_mode
= mode_32bit
;
9896 priv
.orig_sizeflag
|= AFLAG
| DFLAG
;
9898 else if (CONST_STRNEQ (p
, "i8086"))
9900 address_mode
= mode_16bit
;
9901 priv
.orig_sizeflag
&= ~(AFLAG
| DFLAG
);
9903 else if (CONST_STRNEQ (p
, "intel"))
9906 if (CONST_STRNEQ (p
+ 5, "-mnemonic"))
9909 else if (CONST_STRNEQ (p
, "att"))
9912 if (CONST_STRNEQ (p
+ 3, "-mnemonic"))
9915 else if (CONST_STRNEQ (p
, "addr"))
9917 if (address_mode
== mode_64bit
)
9919 if (p
[4] == '3' && p
[5] == '2')
9920 priv
.orig_sizeflag
&= ~AFLAG
;
9921 else if (p
[4] == '6' && p
[5] == '4')
9922 priv
.orig_sizeflag
|= AFLAG
;
9926 if (p
[4] == '1' && p
[5] == '6')
9927 priv
.orig_sizeflag
&= ~AFLAG
;
9928 else if (p
[4] == '3' && p
[5] == '2')
9929 priv
.orig_sizeflag
|= AFLAG
;
9932 else if (CONST_STRNEQ (p
, "data"))
9934 if (p
[4] == '1' && p
[5] == '6')
9935 priv
.orig_sizeflag
&= ~DFLAG
;
9936 else if (p
[4] == '3' && p
[5] == '2')
9937 priv
.orig_sizeflag
|= DFLAG
;
9939 else if (CONST_STRNEQ (p
, "suffix"))
9940 priv
.orig_sizeflag
|= SUFFIX_ALWAYS
;
9942 p
= strchr (p
, ',');
9947 if (address_mode
== mode_64bit
&& sizeof (bfd_vma
) < 8)
9949 (*info
->fprintf_func
) (info
->stream
,
9950 _("64-bit address is disabled"));
9956 names64
= intel_names64
;
9957 names32
= intel_names32
;
9958 names16
= intel_names16
;
9959 names8
= intel_names8
;
9960 names8rex
= intel_names8rex
;
9961 names_seg
= intel_names_seg
;
9962 names_mm
= intel_names_mm
;
9963 names_bnd
= intel_names_bnd
;
9964 names_xmm
= intel_names_xmm
;
9965 names_ymm
= intel_names_ymm
;
9966 names_zmm
= intel_names_zmm
;
9967 names_tmm
= intel_names_tmm
;
9968 index64
= intel_index64
;
9969 index32
= intel_index32
;
9970 names_mask
= intel_names_mask
;
9971 index16
= intel_index16
;
9974 separator_char
= '+';
9979 names64
= att_names64
;
9980 names32
= att_names32
;
9981 names16
= att_names16
;
9982 names8
= att_names8
;
9983 names8rex
= att_names8rex
;
9984 names_seg
= att_names_seg
;
9985 names_mm
= att_names_mm
;
9986 names_bnd
= att_names_bnd
;
9987 names_xmm
= att_names_xmm
;
9988 names_ymm
= att_names_ymm
;
9989 names_zmm
= att_names_zmm
;
9990 names_tmm
= att_names_tmm
;
9991 index64
= att_index64
;
9992 index32
= att_index32
;
9993 names_mask
= att_names_mask
;
9994 index16
= att_index16
;
9997 separator_char
= ',';
10001 /* The output looks better if we put 7 bytes on a line, since that
10002 puts most long word instructions on a single line. Use 8 bytes
10004 if ((info
->mach
& bfd_mach_l1om
) != 0)
10005 info
->bytes_per_line
= 8;
10007 info
->bytes_per_line
= 7;
10009 info
->private_data
= &priv
;
10010 priv
.max_fetched
= priv
.the_buffer
;
10011 priv
.insn_start
= pc
;
10014 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
10022 start_codep
= priv
.the_buffer
;
10023 codep
= priv
.the_buffer
;
10025 if (OPCODES_SIGSETJMP (priv
.bailout
) != 0)
10029 /* Getting here means we tried for data but didn't get it. That
10030 means we have an incomplete instruction of some sort. Just
10031 print the first byte as a prefix or a .byte pseudo-op. */
10032 if (codep
> priv
.the_buffer
)
10034 name
= prefix_name (priv
.the_buffer
[0], priv
.orig_sizeflag
);
10036 (*info
->fprintf_func
) (info
->stream
, "%s", name
);
10039 /* Just print the first byte as a .byte instruction. */
10040 (*info
->fprintf_func
) (info
->stream
, ".byte 0x%x",
10041 (unsigned int) priv
.the_buffer
[0]);
10051 sizeflag
= priv
.orig_sizeflag
;
10053 if (!ckprefix () || rex_used
)
10055 /* Too many prefixes or unused REX prefixes. */
10057 i
< (int) ARRAY_SIZE (all_prefixes
) && all_prefixes
[i
];
10059 (*info
->fprintf_func
) (info
->stream
, "%s%s",
10061 prefix_name (all_prefixes
[i
], sizeflag
));
10065 insn_codep
= codep
;
10067 FETCH_DATA (info
, codep
+ 1);
10068 two_source_ops
= (*codep
== 0x62) || (*codep
== 0xc8);
10070 if (((prefixes
& PREFIX_FWAIT
)
10071 && ((*codep
< 0xd8) || (*codep
> 0xdf))))
10073 /* Handle prefixes before fwait. */
10074 for (i
= 0; i
< fwait_prefix
&& all_prefixes
[i
];
10076 (*info
->fprintf_func
) (info
->stream
, "%s ",
10077 prefix_name (all_prefixes
[i
], sizeflag
));
10078 (*info
->fprintf_func
) (info
->stream
, "fwait");
10082 if (*codep
== 0x0f)
10084 unsigned char threebyte
;
10087 FETCH_DATA (info
, codep
+ 1);
10088 threebyte
= *codep
;
10089 dp
= &dis386_twobyte
[threebyte
];
10090 need_modrm
= twobyte_has_modrm
[threebyte
];
10095 dp
= &dis386
[*codep
];
10096 need_modrm
= onebyte_has_modrm
[*codep
];
10100 /* Save sizeflag for printing the extra prefixes later before updating
10101 it for mnemonic and operand processing. The prefix names depend
10102 only on the address mode. */
10103 orig_sizeflag
= sizeflag
;
10104 if (prefixes
& PREFIX_ADDR
)
10106 if ((prefixes
& PREFIX_DATA
))
10112 FETCH_DATA (info
, codep
+ 1);
10113 modrm
.mod
= (*codep
>> 6) & 3;
10114 modrm
.reg
= (*codep
>> 3) & 7;
10115 modrm
.rm
= *codep
& 7;
10118 memset (&modrm
, 0, sizeof (modrm
));
10121 memset (&vex
, 0, sizeof (vex
));
10123 if (dp
->name
== NULL
&& dp
->op
[0].bytemode
== FLOATCODE
)
10125 get_sib (info
, sizeflag
);
10126 dofloat (sizeflag
);
10130 dp
= get_valid_dis386 (dp
, info
);
10131 if (dp
!= NULL
&& putop (dp
->name
, sizeflag
) == 0)
10133 get_sib (info
, sizeflag
);
10134 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
10137 op_ad
= MAX_OPERANDS
- 1 - i
;
10139 (*dp
->op
[i
].rtn
) (dp
->op
[i
].bytemode
, sizeflag
);
10140 /* For EVEX instruction after the last operand masking
10141 should be printed. */
10142 if (i
== 0 && vex
.evex
)
10144 /* Don't print {%k0}. */
10145 if (vex
.mask_register_specifier
)
10148 oappend (names_mask
[vex
.mask_register_specifier
]);
10158 /* Clear instruction information. */
10161 the_info
->insn_info_valid
= 0;
10162 the_info
->branch_delay_insns
= 0;
10163 the_info
->data_size
= 0;
10164 the_info
->insn_type
= dis_noninsn
;
10165 the_info
->target
= 0;
10166 the_info
->target2
= 0;
10169 /* Reset jump operation indicator. */
10170 op_is_jump
= FALSE
;
10173 int jump_detection
= 0;
10175 /* Extract flags. */
10176 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
10178 if ((dp
->op
[i
].rtn
== OP_J
)
10179 || (dp
->op
[i
].rtn
== OP_indirE
))
10180 jump_detection
|= 1;
10181 else if ((dp
->op
[i
].rtn
== BND_Fixup
)
10182 || (!dp
->op
[i
].rtn
&& !dp
->op
[i
].bytemode
))
10183 jump_detection
|= 2;
10184 else if ((dp
->op
[i
].bytemode
== cond_jump_mode
)
10185 || (dp
->op
[i
].bytemode
== loop_jcxz_mode
))
10186 jump_detection
|= 4;
10189 /* Determine if this is a jump or branch. */
10190 if ((jump_detection
& 0x3) == 0x3)
10193 if (jump_detection
& 0x4)
10194 the_info
->insn_type
= dis_condbranch
;
10196 the_info
->insn_type
=
10197 (dp
->name
&& !strncmp(dp
->name
, "call", 4))
10198 ? dis_jsr
: dis_branch
;
10202 /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
10203 are all 0s in inverted form. */
10204 if (need_vex
&& vex
.register_specifier
!= 0)
10206 (*info
->fprintf_func
) (info
->stream
, "(bad)");
10207 return end_codep
- priv
.the_buffer
;
10210 switch (dp
->prefix_requirement
)
10213 /* If only the data prefix is marked as mandatory, its absence renders
10214 the encoding invalid. Most other PREFIX_OPCODE rules still apply. */
10215 if (need_vex
? !vex
.prefix
: !(prefixes
& PREFIX_DATA
))
10217 (*info
->fprintf_func
) (info
->stream
, "(bad)");
10218 return end_codep
- priv
.the_buffer
;
10220 used_prefixes
|= PREFIX_DATA
;
10221 /* Fall through. */
10222 case PREFIX_OPCODE
:
10223 /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
10224 unused, opcode is invalid. Since the PREFIX_DATA prefix may be
10225 used by putop and MMX/SSE operand and may be overridden by the
10226 PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
10229 ? vex
.prefix
== REPE_PREFIX_OPCODE
10230 || vex
.prefix
== REPNE_PREFIX_OPCODE
10232 & (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0)
10234 & (PREFIX_REPZ
| PREFIX_REPNZ
)) == 0)
10236 ? vex
.prefix
== DATA_PREFIX_OPCODE
10238 & (PREFIX_REPZ
| PREFIX_REPNZ
| PREFIX_DATA
))
10240 && (used_prefixes
& PREFIX_DATA
) == 0))
10241 || (vex
.evex
&& dp
->prefix_requirement
!= PREFIX_DATA
10242 && !vex
.w
!= !(used_prefixes
& PREFIX_DATA
)))
10244 (*info
->fprintf_func
) (info
->stream
, "(bad)");
10245 return end_codep
- priv
.the_buffer
;
10250 /* Check if the REX prefix is used. */
10251 if ((rex
^ rex_used
) == 0 && !need_vex
&& last_rex_prefix
>= 0)
10252 all_prefixes
[last_rex_prefix
] = 0;
10254 /* Check if the SEG prefix is used. */
10255 if ((prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
| PREFIX_ES
10256 | PREFIX_FS
| PREFIX_GS
)) != 0
10257 && (used_prefixes
& active_seg_prefix
) != 0)
10258 all_prefixes
[last_seg_prefix
] = 0;
10260 /* Check if the ADDR prefix is used. */
10261 if ((prefixes
& PREFIX_ADDR
) != 0
10262 && (used_prefixes
& PREFIX_ADDR
) != 0)
10263 all_prefixes
[last_addr_prefix
] = 0;
10265 /* Check if the DATA prefix is used. */
10266 if ((prefixes
& PREFIX_DATA
) != 0
10267 && (used_prefixes
& PREFIX_DATA
) != 0
10269 all_prefixes
[last_data_prefix
] = 0;
10271 /* Print the extra prefixes. */
10273 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
10274 if (all_prefixes
[i
])
10277 name
= prefix_name (all_prefixes
[i
], orig_sizeflag
);
10280 prefix_length
+= strlen (name
) + 1;
10281 (*info
->fprintf_func
) (info
->stream
, "%s ", name
);
10284 /* Check maximum code length. */
10285 if ((codep
- start_codep
) > MAX_CODE_LENGTH
)
10287 (*info
->fprintf_func
) (info
->stream
, "(bad)");
10288 return MAX_CODE_LENGTH
;
10291 obufp
= mnemonicendp
;
10292 for (i
= strlen (obuf
) + prefix_length
; i
< 6; i
++)
10295 (*info
->fprintf_func
) (info
->stream
, "%s", obuf
);
10297 /* The enter and bound instructions are printed with operands in the same
10298 order as the intel book; everything else is printed in reverse order. */
10299 if (intel_syntax
|| two_source_ops
)
10303 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
10304 op_txt
[i
] = op_out
[i
];
10306 if (intel_syntax
&& dp
&& dp
->op
[2].rtn
== OP_Rounding
10307 && dp
->op
[3].rtn
== OP_E
&& dp
->op
[4].rtn
== NULL
)
10309 op_txt
[2] = op_out
[3];
10310 op_txt
[3] = op_out
[2];
10313 for (i
= 0; i
< (MAX_OPERANDS
>> 1); ++i
)
10315 op_ad
= op_index
[i
];
10316 op_index
[i
] = op_index
[MAX_OPERANDS
- 1 - i
];
10317 op_index
[MAX_OPERANDS
- 1 - i
] = op_ad
;
10318 riprel
= op_riprel
[i
];
10319 op_riprel
[i
] = op_riprel
[MAX_OPERANDS
- 1 - i
];
10320 op_riprel
[MAX_OPERANDS
- 1 - i
] = riprel
;
10325 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
10326 op_txt
[MAX_OPERANDS
- 1 - i
] = op_out
[i
];
10330 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
10334 (*info
->fprintf_func
) (info
->stream
, ",");
10335 if (op_index
[i
] != -1 && !op_riprel
[i
])
10337 bfd_vma target
= (bfd_vma
) op_address
[op_index
[i
]];
10339 if (the_info
&& op_is_jump
)
10341 the_info
->insn_info_valid
= 1;
10342 the_info
->branch_delay_insns
= 0;
10343 the_info
->data_size
= 0;
10344 the_info
->target
= target
;
10345 the_info
->target2
= 0;
10347 (*info
->print_address_func
) (target
, info
);
10350 (*info
->fprintf_func
) (info
->stream
, "%s", op_txt
[i
]);
10354 for (i
= 0; i
< MAX_OPERANDS
; i
++)
10355 if (op_index
[i
] != -1 && op_riprel
[i
])
10357 (*info
->fprintf_func
) (info
->stream
, " # ");
10358 (*info
->print_address_func
) ((bfd_vma
) (start_pc
+ (codep
- start_codep
)
10359 + op_address
[op_index
[i
]]), info
);
10362 return codep
- priv
.the_buffer
;
10365 static const char *float_mem
[] = {
10440 static const unsigned char float_mem_mode
[] = {
10515 #define ST { OP_ST, 0 }
10516 #define STi { OP_STi, 0 }
10518 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
10519 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
10520 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
10521 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
10522 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
10523 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
10524 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
10525 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
10526 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
10528 static const struct dis386 float_reg
[][8] = {
10531 { "fadd", { ST
, STi
}, 0 },
10532 { "fmul", { ST
, STi
}, 0 },
10533 { "fcom", { STi
}, 0 },
10534 { "fcomp", { STi
}, 0 },
10535 { "fsub", { ST
, STi
}, 0 },
10536 { "fsubr", { ST
, STi
}, 0 },
10537 { "fdiv", { ST
, STi
}, 0 },
10538 { "fdivr", { ST
, STi
}, 0 },
10542 { "fld", { STi
}, 0 },
10543 { "fxch", { STi
}, 0 },
10553 { "fcmovb", { ST
, STi
}, 0 },
10554 { "fcmove", { ST
, STi
}, 0 },
10555 { "fcmovbe",{ ST
, STi
}, 0 },
10556 { "fcmovu", { ST
, STi
}, 0 },
10564 { "fcmovnb",{ ST
, STi
}, 0 },
10565 { "fcmovne",{ ST
, STi
}, 0 },
10566 { "fcmovnbe",{ ST
, STi
}, 0 },
10567 { "fcmovnu",{ ST
, STi
}, 0 },
10569 { "fucomi", { ST
, STi
}, 0 },
10570 { "fcomi", { ST
, STi
}, 0 },
10575 { "fadd", { STi
, ST
}, 0 },
10576 { "fmul", { STi
, ST
}, 0 },
10579 { "fsub{!M|r}", { STi
, ST
}, 0 },
10580 { "fsub{M|}", { STi
, ST
}, 0 },
10581 { "fdiv{!M|r}", { STi
, ST
}, 0 },
10582 { "fdiv{M|}", { STi
, ST
}, 0 },
10586 { "ffree", { STi
}, 0 },
10588 { "fst", { STi
}, 0 },
10589 { "fstp", { STi
}, 0 },
10590 { "fucom", { STi
}, 0 },
10591 { "fucomp", { STi
}, 0 },
10597 { "faddp", { STi
, ST
}, 0 },
10598 { "fmulp", { STi
, ST
}, 0 },
10601 { "fsub{!M|r}p", { STi
, ST
}, 0 },
10602 { "fsub{M|}p", { STi
, ST
}, 0 },
10603 { "fdiv{!M|r}p", { STi
, ST
}, 0 },
10604 { "fdiv{M|}p", { STi
, ST
}, 0 },
10608 { "ffreep", { STi
}, 0 },
10613 { "fucomip", { ST
, STi
}, 0 },
10614 { "fcomip", { ST
, STi
}, 0 },
10619 static char *fgrps
[][8] = {
10622 "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10627 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10632 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
10637 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
10642 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
10647 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
10652 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10657 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
10658 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
10663 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10668 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10673 swap_operand (void)
10675 mnemonicendp
[0] = '.';
10676 mnemonicendp
[1] = 's';
10681 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED
,
10682 int sizeflag ATTRIBUTE_UNUSED
)
10684 /* Skip mod/rm byte. */
10690 dofloat (int sizeflag
)
10692 const struct dis386
*dp
;
10693 unsigned char floatop
;
10695 floatop
= codep
[-1];
10697 if (modrm
.mod
!= 3)
10699 int fp_indx
= (floatop
- 0xd8) * 8 + modrm
.reg
;
10701 putop (float_mem
[fp_indx
], sizeflag
);
10704 OP_E (float_mem_mode
[fp_indx
], sizeflag
);
10707 /* Skip mod/rm byte. */
10711 dp
= &float_reg
[floatop
- 0xd8][modrm
.reg
];
10712 if (dp
->name
== NULL
)
10714 putop (fgrps
[dp
->op
[0].bytemode
][modrm
.rm
], sizeflag
);
10716 /* Instruction fnstsw is only one with strange arg. */
10717 if (floatop
== 0xdf && codep
[-1] == 0xe0)
10718 strcpy (op_out
[0], names16
[0]);
10722 putop (dp
->name
, sizeflag
);
10727 (*dp
->op
[0].rtn
) (dp
->op
[0].bytemode
, sizeflag
);
10732 (*dp
->op
[1].rtn
) (dp
->op
[1].bytemode
, sizeflag
);
10736 /* Like oappend (below), but S is a string starting with '%'.
10737 In Intel syntax, the '%' is elided. */
10739 oappend_maybe_intel (const char *s
)
10741 oappend (s
+ intel_syntax
);
10745 OP_ST (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
10747 oappend_maybe_intel ("%st");
10751 OP_STi (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
10753 sprintf (scratchbuf
, "%%st(%d)", modrm
.rm
);
10754 oappend_maybe_intel (scratchbuf
);
10757 /* Capital letters in template are macros. */
10759 putop (const char *in_template
, int sizeflag
)
10764 unsigned int l
= 0, len
= 0;
10767 for (p
= in_template
; *p
; p
++)
10771 if (l
>= sizeof (last
) || !ISUPPER (*p
))
10790 while (*++p
!= '|')
10791 if (*p
== '}' || *p
== '\0')
10797 while (*++p
!= '}')
10809 if ((need_modrm
&& modrm
.mod
!= 3)
10810 || (sizeflag
& SUFFIX_ALWAYS
))
10819 if (sizeflag
& SUFFIX_ALWAYS
)
10822 else if (l
== 1 && last
[0] == 'L')
10824 if (address_mode
== mode_64bit
10825 && !(prefixes
& PREFIX_ADDR
))
10838 if (intel_syntax
&& !alt
)
10840 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
10842 if (sizeflag
& DFLAG
)
10843 *obufp
++ = intel_syntax
? 'd' : 'l';
10845 *obufp
++ = intel_syntax
? 'w' : 's';
10846 used_prefixes
|= (prefixes
& PREFIX_DATA
);
10850 if (intel_syntax
|| !(sizeflag
& SUFFIX_ALWAYS
))
10853 if (modrm
.mod
== 3)
10859 if (sizeflag
& DFLAG
)
10860 *obufp
++ = intel_syntax
? 'd' : 'l';
10863 used_prefixes
|= (prefixes
& PREFIX_DATA
);
10869 case 'E': /* For jcxz/jecxz */
10870 if (address_mode
== mode_64bit
)
10872 if (sizeflag
& AFLAG
)
10878 if (sizeflag
& AFLAG
)
10880 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
10885 if ((prefixes
& PREFIX_ADDR
) || (sizeflag
& SUFFIX_ALWAYS
))
10887 if (sizeflag
& AFLAG
)
10888 *obufp
++ = address_mode
== mode_64bit
? 'q' : 'l';
10890 *obufp
++ = address_mode
== mode_64bit
? 'l' : 'w';
10891 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
10895 if (intel_syntax
|| (obufp
[-1] != 's' && !(sizeflag
& SUFFIX_ALWAYS
)))
10897 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
10901 if (!(rex
& REX_W
))
10902 used_prefixes
|= (prefixes
& PREFIX_DATA
);
10907 if ((prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_CS
10908 || (prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_DS
)
10910 used_prefixes
|= prefixes
& (PREFIX_CS
| PREFIX_DS
);
10914 /* Set active_seg_prefix even if not set in 64-bit mode
10915 because here it is a valid branch hint. */
10916 if (prefixes
& PREFIX_DS
)
10918 active_seg_prefix
= PREFIX_DS
;
10923 active_seg_prefix
= PREFIX_CS
;
10938 if (intel_mnemonic
!= cond
)
10942 if ((prefixes
& PREFIX_FWAIT
) == 0)
10945 used_prefixes
|= PREFIX_FWAIT
;
10951 else if (intel_syntax
&& (sizeflag
& DFLAG
))
10955 if (!(rex
& REX_W
))
10956 used_prefixes
|= (prefixes
& PREFIX_DATA
);
10959 if (address_mode
== mode_64bit
10960 && (isa64
== intel64
|| (rex
& REX_W
)
10961 || !(prefixes
& PREFIX_DATA
)))
10963 if (sizeflag
& SUFFIX_ALWAYS
)
10967 /* Fall through. */
10971 if ((modrm
.mod
== 3 || !cond
)
10972 && !(sizeflag
& SUFFIX_ALWAYS
))
10974 /* Fall through. */
10976 if ((!(rex
& REX_W
) && (prefixes
& PREFIX_DATA
))
10977 || ((sizeflag
& SUFFIX_ALWAYS
)
10978 && address_mode
!= mode_64bit
))
10980 *obufp
++ = (sizeflag
& DFLAG
) ?
10981 intel_syntax
? 'd' : 'l' : 'w';
10982 used_prefixes
|= (prefixes
& PREFIX_DATA
);
10984 else if (sizeflag
& SUFFIX_ALWAYS
)
10987 else if (l
== 1 && last
[0] == 'L')
10989 if ((prefixes
& PREFIX_DATA
)
10991 || (sizeflag
& SUFFIX_ALWAYS
))
10998 if (sizeflag
& DFLAG
)
10999 *obufp
++ = intel_syntax
? 'd' : 'l';
11002 used_prefixes
|= (prefixes
& PREFIX_DATA
);
11012 if (intel_syntax
&& !alt
)
11015 if ((need_modrm
&& modrm
.mod
!= 3)
11016 || (sizeflag
& SUFFIX_ALWAYS
))
11022 if (sizeflag
& DFLAG
)
11023 *obufp
++ = intel_syntax
? 'd' : 'l';
11026 used_prefixes
|= (prefixes
& PREFIX_DATA
);
11030 else if (l
== 1 && last
[0] == 'D')
11031 *obufp
++ = vex
.w
? 'q' : 'd';
11032 else if (l
== 1 && last
[0] == 'L')
11034 if (cond
? modrm
.mod
== 3 && !(sizeflag
& SUFFIX_ALWAYS
)
11035 : address_mode
!= mode_64bit
)
11042 else if((address_mode
== mode_64bit
&& cond
)
11043 || (sizeflag
& SUFFIX_ALWAYS
))
11044 *obufp
++ = intel_syntax
? 'd' : 'l';
11053 else if (sizeflag
& DFLAG
)
11062 if (intel_syntax
&& !p
[1]
11063 && ((rex
& REX_W
) || (sizeflag
& DFLAG
)))
11065 if (!(rex
& REX_W
))
11066 used_prefixes
|= (prefixes
& PREFIX_DATA
);
11074 if (sizeflag
& SUFFIX_ALWAYS
)
11080 if (sizeflag
& DFLAG
)
11084 used_prefixes
|= (prefixes
& PREFIX_DATA
);
11088 else if (l
== 1 && last
[0] == 'L')
11090 if (address_mode
== mode_64bit
11091 && !(prefixes
& PREFIX_ADDR
))
11107 && (last
[0] == 'L' || last
[0] == 'X'))
11109 if (last
[0] == 'X')
11117 else if (rex
& REX_W
)
11130 /* operand size flag for cwtl, cbtw */
11139 else if (sizeflag
& DFLAG
)
11143 if (!(rex
& REX_W
))
11144 used_prefixes
|= (prefixes
& PREFIX_DATA
);
11150 if (last
[0] == 'X')
11151 *obufp
++ = vex
.w
? 'd': 's';
11152 else if (last
[0] == 'B')
11153 *obufp
++ = vex
.w
? 'w': 'b';
11164 ? vex
.prefix
== DATA_PREFIX_OPCODE
11165 : prefixes
& PREFIX_DATA
)
11168 used_prefixes
|= PREFIX_DATA
;
11174 if (l
== 1 && last
[0] == 'X')
11179 || ((modrm
.mod
== 3 || vex
.b
) && !(sizeflag
& SUFFIX_ALWAYS
)))
11181 switch (vex
.length
)
11201 /* These insns ignore ModR/M.mod: Force it to 3 for OP_E(). */
11203 if (!intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
11204 *obufp
++ = address_mode
== mode_64bit
? 'q' : 'l';
11206 else if (l
== 1 && last
[0] == 'X')
11208 if (!need_vex
|| !vex
.evex
)
11211 || ((modrm
.mod
== 3 || vex
.b
) && !(sizeflag
& SUFFIX_ALWAYS
)))
11213 switch (vex
.length
)
11234 if (isa64
== intel64
&& (rex
& REX_W
))
11240 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
11242 if (sizeflag
& DFLAG
)
11246 used_prefixes
|= (prefixes
& PREFIX_DATA
);
11255 mnemonicendp
= obufp
;
11260 oappend (const char *s
)
11262 obufp
= stpcpy (obufp
, s
);
11268 /* Only print the active segment register. */
11269 if (!active_seg_prefix
)
11272 used_prefixes
|= active_seg_prefix
;
11273 switch (active_seg_prefix
)
11276 oappend_maybe_intel ("%cs:");
11279 oappend_maybe_intel ("%ds:");
11282 oappend_maybe_intel ("%ss:");
11285 oappend_maybe_intel ("%es:");
11288 oappend_maybe_intel ("%fs:");
11291 oappend_maybe_intel ("%gs:");
11299 OP_indirE (int bytemode
, int sizeflag
)
11303 OP_E (bytemode
, sizeflag
);
11307 print_operand_value (char *buf
, int hex
, bfd_vma disp
)
11309 if (address_mode
== mode_64bit
)
11317 sprintf_vma (tmp
, disp
);
11318 for (i
= 0; tmp
[i
] == '0' && tmp
[i
+ 1]; i
++);
11319 strcpy (buf
+ 2, tmp
+ i
);
11323 bfd_signed_vma v
= disp
;
11330 /* Check for possible overflow on 0x8000000000000000. */
11333 strcpy (buf
, "9223372036854775808");
11347 tmp
[28 - i
] = (v
% 10) + '0';
11351 strcpy (buf
, tmp
+ 29 - i
);
11357 sprintf (buf
, "0x%x", (unsigned int) disp
);
11359 sprintf (buf
, "%d", (int) disp
);
11363 /* Put DISP in BUF as signed hex number. */
11366 print_displacement (char *buf
, bfd_vma disp
)
11368 bfd_signed_vma val
= disp
;
11377 /* Check for possible overflow. */
11380 switch (address_mode
)
11383 strcpy (buf
+ j
, "0x8000000000000000");
11386 strcpy (buf
+ j
, "0x80000000");
11389 strcpy (buf
+ j
, "0x8000");
11399 sprintf_vma (tmp
, (bfd_vma
) val
);
11400 for (i
= 0; tmp
[i
] == '0'; i
++)
11402 if (tmp
[i
] == '\0')
11404 strcpy (buf
+ j
, tmp
+ i
);
11408 intel_operand_size (int bytemode
, int sizeflag
)
11412 && (bytemode
== x_mode
11413 || bytemode
== evex_half_bcst_xmmq_mode
))
11416 oappend ("QWORD PTR ");
11418 oappend ("DWORD PTR ");
11427 oappend ("BYTE PTR ");
11432 oappend ("WORD PTR ");
11435 if (address_mode
== mode_64bit
&& isa64
== intel64
)
11437 oappend ("QWORD PTR ");
11440 /* Fall through. */
11442 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
11444 oappend ("QWORD PTR ");
11447 /* Fall through. */
11453 oappend ("QWORD PTR ");
11454 else if (bytemode
== dq_mode
)
11455 oappend ("DWORD PTR ");
11458 if (sizeflag
& DFLAG
)
11459 oappend ("DWORD PTR ");
11461 oappend ("WORD PTR ");
11462 used_prefixes
|= (prefixes
& PREFIX_DATA
);
11466 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
11468 oappend ("WORD PTR ");
11469 if (!(rex
& REX_W
))
11470 used_prefixes
|= (prefixes
& PREFIX_DATA
);
11473 if (sizeflag
& DFLAG
)
11474 oappend ("QWORD PTR ");
11476 oappend ("DWORD PTR ");
11477 used_prefixes
|= (prefixes
& PREFIX_DATA
);
11480 if (!(sizeflag
& DFLAG
) && isa64
== intel64
)
11481 oappend ("WORD PTR ");
11483 oappend ("DWORD PTR ");
11484 used_prefixes
|= (prefixes
& PREFIX_DATA
);
11489 oappend ("DWORD PTR ");
11493 oappend ("QWORD PTR ");
11496 if (address_mode
== mode_64bit
)
11497 oappend ("QWORD PTR ");
11499 oappend ("DWORD PTR ");
11502 if (sizeflag
& DFLAG
)
11503 oappend ("FWORD PTR ");
11505 oappend ("DWORD PTR ");
11506 used_prefixes
|= (prefixes
& PREFIX_DATA
);
11509 oappend ("TBYTE PTR ");
11513 case evex_x_gscat_mode
:
11514 case evex_x_nobcst_mode
:
11518 switch (vex
.length
)
11521 oappend ("XMMWORD PTR ");
11524 oappend ("YMMWORD PTR ");
11527 oappend ("ZMMWORD PTR ");
11534 oappend ("XMMWORD PTR ");
11537 oappend ("XMMWORD PTR ");
11540 oappend ("YMMWORD PTR ");
11543 case evex_half_bcst_xmmq_mode
:
11547 switch (vex
.length
)
11550 oappend ("QWORD PTR ");
11553 oappend ("XMMWORD PTR ");
11556 oappend ("YMMWORD PTR ");
11566 switch (vex
.length
)
11571 oappend ("BYTE PTR ");
11581 switch (vex
.length
)
11586 oappend ("WORD PTR ");
11596 switch (vex
.length
)
11601 oappend ("DWORD PTR ");
11611 switch (vex
.length
)
11616 oappend ("QWORD PTR ");
11626 switch (vex
.length
)
11629 oappend ("WORD PTR ");
11632 oappend ("DWORD PTR ");
11635 oappend ("QWORD PTR ");
11645 switch (vex
.length
)
11648 oappend ("DWORD PTR ");
11651 oappend ("QWORD PTR ");
11654 oappend ("XMMWORD PTR ");
11664 switch (vex
.length
)
11667 oappend ("QWORD PTR ");
11670 oappend ("YMMWORD PTR ");
11673 oappend ("ZMMWORD PTR ");
11683 switch (vex
.length
)
11687 oappend ("XMMWORD PTR ");
11694 oappend ("OWORD PTR ");
11696 case vex_scalar_w_dq_mode
:
11701 oappend ("QWORD PTR ");
11703 oappend ("DWORD PTR ");
11705 case vex_vsib_d_w_dq_mode
:
11706 case vex_vsib_q_w_dq_mode
:
11713 oappend ("QWORD PTR ");
11715 oappend ("DWORD PTR ");
11719 switch (vex
.length
)
11722 oappend ("XMMWORD PTR ");
11725 oappend ("YMMWORD PTR ");
11728 oappend ("ZMMWORD PTR ");
11735 case vex_vsib_q_w_d_mode
:
11736 case vex_vsib_d_w_d_mode
:
11737 if (!need_vex
|| !vex
.evex
)
11740 switch (vex
.length
)
11743 oappend ("QWORD PTR ");
11746 oappend ("XMMWORD PTR ");
11749 oappend ("YMMWORD PTR ");
11757 if (!need_vex
|| vex
.length
!= 128)
11760 oappend ("DWORD PTR ");
11762 oappend ("BYTE PTR ");
11768 oappend ("QWORD PTR ");
11770 oappend ("WORD PTR ");
11780 OP_E_register (int bytemode
, int sizeflag
)
11782 int reg
= modrm
.rm
;
11783 const char **names
;
11789 if ((sizeflag
& SUFFIX_ALWAYS
)
11790 && (bytemode
== b_swap_mode
11791 || bytemode
== bnd_swap_mode
11792 || bytemode
== v_swap_mode
))
11819 names
= address_mode
== mode_64bit
? names64
: names32
;
11822 case bnd_swap_mode
:
11831 if (address_mode
== mode_64bit
&& isa64
== intel64
)
11836 /* Fall through. */
11838 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
11844 /* Fall through. */
11854 else if (bytemode
!= v_mode
&& bytemode
!= v_swap_mode
)
11858 if (sizeflag
& DFLAG
)
11862 used_prefixes
|= (prefixes
& PREFIX_DATA
);
11866 if (!(sizeflag
& DFLAG
) && isa64
== intel64
)
11870 used_prefixes
|= (prefixes
& PREFIX_DATA
);
11873 names
= (address_mode
== mode_64bit
11874 ? names64
: names32
);
11875 if (!(prefixes
& PREFIX_ADDR
))
11876 names
= (address_mode
== mode_16bit
11877 ? names16
: names
);
11880 /* Remove "addr16/addr32". */
11881 all_prefixes
[last_addr_prefix
] = 0;
11882 names
= (address_mode
!= mode_32bit
11883 ? names32
: names16
);
11884 used_prefixes
|= PREFIX_ADDR
;
11894 names
= names_mask
;
11899 oappend (INTERNAL_DISASSEMBLER_ERROR
);
11902 oappend (names
[reg
]);
11906 OP_E_memory (int bytemode
, int sizeflag
)
11909 int add
= (rex
& REX_B
) ? 8 : 0;
11915 /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */
11917 && bytemode
!= x_mode
11918 && bytemode
!= xmmq_mode
11919 && bytemode
!= evex_half_bcst_xmmq_mode
)
11937 if (address_mode
!= mode_64bit
)
11947 case vex_scalar_w_dq_mode
:
11948 case vex_vsib_d_w_dq_mode
:
11949 case vex_vsib_d_w_d_mode
:
11950 case vex_vsib_q_w_dq_mode
:
11951 case vex_vsib_q_w_d_mode
:
11952 case evex_x_gscat_mode
:
11953 shift
= vex
.w
? 3 : 2;
11956 case evex_half_bcst_xmmq_mode
:
11960 shift
= vex
.w
? 3 : 2;
11963 /* Fall through. */
11967 case evex_x_nobcst_mode
:
11969 switch (vex
.length
)
11983 /* Make necessary corrections to shift for modes that need it. */
11984 if (bytemode
== xmmq_mode
11985 || bytemode
== evex_half_bcst_xmmq_mode
11986 || (bytemode
== ymmq_mode
&& vex
.length
== 128))
11988 else if (bytemode
== xmmqd_mode
)
11990 else if (bytemode
== xmmdw_mode
)
12005 shift
= vex
.w
? 1 : 0;
12016 intel_operand_size (bytemode
, sizeflag
);
12019 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
12021 /* 32/64 bit address mode */
12031 int addr32flag
= !((sizeflag
& AFLAG
)
12032 || bytemode
== v_bnd_mode
12033 || bytemode
== v_bndmk_mode
12034 || bytemode
== bnd_mode
12035 || bytemode
== bnd_swap_mode
);
12036 const char **indexes64
= names64
;
12037 const char **indexes32
= names32
;
12047 vindex
= sib
.index
;
12053 case vex_vsib_d_w_dq_mode
:
12054 case vex_vsib_d_w_d_mode
:
12055 case vex_vsib_q_w_dq_mode
:
12056 case vex_vsib_q_w_d_mode
:
12066 switch (vex
.length
)
12069 indexes64
= indexes32
= names_xmm
;
12073 || bytemode
== vex_vsib_q_w_dq_mode
12074 || bytemode
== vex_vsib_q_w_d_mode
)
12075 indexes64
= indexes32
= names_ymm
;
12077 indexes64
= indexes32
= names_xmm
;
12081 || bytemode
== vex_vsib_q_w_dq_mode
12082 || bytemode
== vex_vsib_q_w_d_mode
)
12083 indexes64
= indexes32
= names_zmm
;
12085 indexes64
= indexes32
= names_ymm
;
12092 haveindex
= vindex
!= 4;
12101 /* mandatory non-vector SIB must have sib */
12102 if (bytemode
== vex_sibmem_mode
)
12108 rbase
= base
+ add
;
12116 if (address_mode
== mode_64bit
&& !havesib
)
12119 if (riprel
&& bytemode
== v_bndmk_mode
)
12127 FETCH_DATA (the_info
, codep
+ 1);
12129 if ((disp
& 0x80) != 0)
12131 if (vex
.evex
&& shift
> 0)
12144 && address_mode
!= mode_16bit
)
12146 if (address_mode
== mode_64bit
)
12150 /* Without base nor index registers, zero-extend the
12151 lower 32-bit displacement to 64 bits. */
12152 disp
= (unsigned int) disp
;
12159 /* In 32-bit mode, we need index register to tell [offset]
12160 from [eiz*1 + offset]. */
12165 havedisp
= (havebase
12167 || (havesib
&& (haveindex
|| scale
!= 0)));
12170 if (modrm
.mod
!= 0 || base
== 5)
12172 if (havedisp
|| riprel
)
12173 print_displacement (scratchbuf
, disp
);
12175 print_operand_value (scratchbuf
, 1, disp
);
12176 oappend (scratchbuf
);
12180 oappend (!addr32flag
? "(%rip)" : "(%eip)");
12184 if ((havebase
|| haveindex
|| needindex
|| needaddr32
|| riprel
)
12185 && (address_mode
!= mode_64bit
12186 || ((bytemode
!= v_bnd_mode
)
12187 && (bytemode
!= v_bndmk_mode
)
12188 && (bytemode
!= bnd_mode
)
12189 && (bytemode
!= bnd_swap_mode
))))
12190 used_prefixes
|= PREFIX_ADDR
;
12192 if (havedisp
|| (intel_syntax
&& riprel
))
12194 *obufp
++ = open_char
;
12195 if (intel_syntax
&& riprel
)
12198 oappend (!addr32flag
? "rip" : "eip");
12202 oappend (address_mode
== mode_64bit
&& !addr32flag
12203 ? names64
[rbase
] : names32
[rbase
]);
12206 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
12207 print index to tell base + index from base. */
12211 || (havebase
&& base
!= ESP_REG_NUM
))
12213 if (!intel_syntax
|| havebase
)
12215 *obufp
++ = separator_char
;
12219 oappend (address_mode
== mode_64bit
&& !addr32flag
12220 ? indexes64
[vindex
] : indexes32
[vindex
]);
12222 oappend (address_mode
== mode_64bit
&& !addr32flag
12223 ? index64
: index32
);
12225 *obufp
++ = scale_char
;
12227 sprintf (scratchbuf
, "%d", 1 << scale
);
12228 oappend (scratchbuf
);
12232 && (disp
|| modrm
.mod
!= 0 || base
== 5))
12234 if (!havedisp
|| (bfd_signed_vma
) disp
>= 0)
12239 else if (modrm
.mod
!= 1 && disp
!= -disp
)
12247 print_displacement (scratchbuf
, disp
);
12249 print_operand_value (scratchbuf
, 1, disp
);
12250 oappend (scratchbuf
);
12253 *obufp
++ = close_char
;
12256 else if (intel_syntax
)
12258 if (modrm
.mod
!= 0 || base
== 5)
12260 if (!active_seg_prefix
)
12262 oappend (names_seg
[ds_reg
- es_reg
]);
12265 print_operand_value (scratchbuf
, 1, disp
);
12266 oappend (scratchbuf
);
12270 else if (bytemode
== v_bnd_mode
12271 || bytemode
== v_bndmk_mode
12272 || bytemode
== bnd_mode
12273 || bytemode
== bnd_swap_mode
)
12280 /* 16 bit address mode */
12281 used_prefixes
|= prefixes
& PREFIX_ADDR
;
12288 if ((disp
& 0x8000) != 0)
12293 FETCH_DATA (the_info
, codep
+ 1);
12295 if ((disp
& 0x80) != 0)
12297 if (vex
.evex
&& shift
> 0)
12302 if ((disp
& 0x8000) != 0)
12308 if (modrm
.mod
!= 0 || modrm
.rm
== 6)
12310 print_displacement (scratchbuf
, disp
);
12311 oappend (scratchbuf
);
12314 if (modrm
.mod
!= 0 || modrm
.rm
!= 6)
12316 *obufp
++ = open_char
;
12318 oappend (index16
[modrm
.rm
]);
12320 && (disp
|| modrm
.mod
!= 0 || modrm
.rm
== 6))
12322 if ((bfd_signed_vma
) disp
>= 0)
12327 else if (modrm
.mod
!= 1)
12334 print_displacement (scratchbuf
, disp
);
12335 oappend (scratchbuf
);
12338 *obufp
++ = close_char
;
12341 else if (intel_syntax
)
12343 if (!active_seg_prefix
)
12345 oappend (names_seg
[ds_reg
- es_reg
]);
12348 print_operand_value (scratchbuf
, 1, disp
& 0xffff);
12349 oappend (scratchbuf
);
12352 if (vex
.evex
&& vex
.b
12353 && (bytemode
== x_mode
12354 || bytemode
== xmmq_mode
12355 || bytemode
== evex_half_bcst_xmmq_mode
))
12358 || bytemode
== xmmq_mode
12359 || bytemode
== evex_half_bcst_xmmq_mode
)
12361 switch (vex
.length
)
12364 oappend ("{1to2}");
12367 oappend ("{1to4}");
12370 oappend ("{1to8}");
12378 switch (vex
.length
)
12381 oappend ("{1to4}");
12384 oappend ("{1to8}");
12387 oappend ("{1to16}");
12397 OP_E (int bytemode
, int sizeflag
)
12399 /* Skip mod/rm byte. */
12403 if (modrm
.mod
== 3)
12404 OP_E_register (bytemode
, sizeflag
);
12406 OP_E_memory (bytemode
, sizeflag
);
12410 OP_G (int bytemode
, int sizeflag
)
12413 const char **names
;
12423 oappend (names8rex
[modrm
.reg
+ add
]);
12425 oappend (names8
[modrm
.reg
+ add
]);
12428 oappend (names16
[modrm
.reg
+ add
]);
12433 oappend (names32
[modrm
.reg
+ add
]);
12436 oappend (names64
[modrm
.reg
+ add
]);
12439 if (modrm
.reg
> 0x3)
12444 oappend (names_bnd
[modrm
.reg
]);
12454 oappend (names64
[modrm
.reg
+ add
]);
12455 else if (bytemode
!= v_mode
&& bytemode
!= movsxd_mode
)
12456 oappend (names32
[modrm
.reg
+ add
]);
12459 if (sizeflag
& DFLAG
)
12460 oappend (names32
[modrm
.reg
+ add
]);
12462 oappend (names16
[modrm
.reg
+ add
]);
12463 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12467 names
= (address_mode
== mode_64bit
12468 ? names64
: names32
);
12469 if (!(prefixes
& PREFIX_ADDR
))
12471 if (address_mode
== mode_16bit
)
12476 /* Remove "addr16/addr32". */
12477 all_prefixes
[last_addr_prefix
] = 0;
12478 names
= (address_mode
!= mode_32bit
12479 ? names32
: names16
);
12480 used_prefixes
|= PREFIX_ADDR
;
12482 oappend (names
[modrm
.reg
+ add
]);
12485 if (address_mode
== mode_64bit
)
12486 oappend (names64
[modrm
.reg
+ add
]);
12488 oappend (names32
[modrm
.reg
+ add
]);
12492 if ((modrm
.reg
+ add
) > 0x7)
12497 oappend (names_mask
[modrm
.reg
+ add
]);
12500 oappend (INTERNAL_DISASSEMBLER_ERROR
);
12513 FETCH_DATA (the_info
, codep
+ 8);
12514 a
= *codep
++ & 0xff;
12515 a
|= (*codep
++ & 0xff) << 8;
12516 a
|= (*codep
++ & 0xff) << 16;
12517 a
|= (*codep
++ & 0xffu
) << 24;
12518 b
= *codep
++ & 0xff;
12519 b
|= (*codep
++ & 0xff) << 8;
12520 b
|= (*codep
++ & 0xff) << 16;
12521 b
|= (*codep
++ & 0xffu
) << 24;
12522 x
= a
+ ((bfd_vma
) b
<< 32);
12530 static bfd_signed_vma
12535 FETCH_DATA (the_info
, codep
+ 4);
12536 x
= *codep
++ & (bfd_vma
) 0xff;
12537 x
|= (*codep
++ & (bfd_vma
) 0xff) << 8;
12538 x
|= (*codep
++ & (bfd_vma
) 0xff) << 16;
12539 x
|= (*codep
++ & (bfd_vma
) 0xff) << 24;
12543 static bfd_signed_vma
12548 FETCH_DATA (the_info
, codep
+ 4);
12549 x
= *codep
++ & (bfd_vma
) 0xff;
12550 x
|= (*codep
++ & (bfd_vma
) 0xff) << 8;
12551 x
|= (*codep
++ & (bfd_vma
) 0xff) << 16;
12552 x
|= (*codep
++ & (bfd_vma
) 0xff) << 24;
12554 x
= (x
^ ((bfd_vma
) 1 << 31)) - ((bfd_vma
) 1 << 31);
12564 FETCH_DATA (the_info
, codep
+ 2);
12565 x
= *codep
++ & 0xff;
12566 x
|= (*codep
++ & 0xff) << 8;
12571 set_op (bfd_vma op
, int riprel
)
12573 op_index
[op_ad
] = op_ad
;
12574 if (address_mode
== mode_64bit
)
12576 op_address
[op_ad
] = op
;
12577 op_riprel
[op_ad
] = riprel
;
12581 /* Mask to get a 32-bit address. */
12582 op_address
[op_ad
] = op
& 0xffffffff;
12583 op_riprel
[op_ad
] = riprel
& 0xffffffff;
12588 OP_REG (int code
, int sizeflag
)
12595 case es_reg
: case ss_reg
: case cs_reg
:
12596 case ds_reg
: case fs_reg
: case gs_reg
:
12597 oappend (names_seg
[code
- es_reg
]);
12609 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
12610 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
12611 s
= names16
[code
- ax_reg
+ add
];
12613 case ah_reg
: case ch_reg
: case dh_reg
: case bh_reg
:
12615 /* Fall through. */
12616 case al_reg
: case cl_reg
: case dl_reg
: case bl_reg
:
12618 s
= names8rex
[code
- al_reg
+ add
];
12620 s
= names8
[code
- al_reg
];
12622 case rAX_reg
: case rCX_reg
: case rDX_reg
: case rBX_reg
:
12623 case rSP_reg
: case rBP_reg
: case rSI_reg
: case rDI_reg
:
12624 if (address_mode
== mode_64bit
12625 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
12627 s
= names64
[code
- rAX_reg
+ add
];
12630 code
+= eAX_reg
- rAX_reg
;
12631 /* Fall through. */
12632 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
12633 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
12636 s
= names64
[code
- eAX_reg
+ add
];
12639 if (sizeflag
& DFLAG
)
12640 s
= names32
[code
- eAX_reg
+ add
];
12642 s
= names16
[code
- eAX_reg
+ add
];
12643 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12647 s
= INTERNAL_DISASSEMBLER_ERROR
;
12654 OP_IMREG (int code
, int sizeflag
)
12666 case al_reg
: case cl_reg
:
12667 s
= names8
[code
- al_reg
];
12676 /* Fall through. */
12677 case z_mode_ax_reg
:
12678 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
12682 if (!(rex
& REX_W
))
12683 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12686 s
= INTERNAL_DISASSEMBLER_ERROR
;
12693 OP_I (int bytemode
, int sizeflag
)
12696 bfd_signed_vma mask
= -1;
12701 FETCH_DATA (the_info
, codep
+ 1);
12711 if (sizeflag
& DFLAG
)
12721 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12737 oappend (INTERNAL_DISASSEMBLER_ERROR
);
12742 scratchbuf
[0] = '$';
12743 print_operand_value (scratchbuf
+ 1, 1, op
);
12744 oappend_maybe_intel (scratchbuf
);
12745 scratchbuf
[0] = '\0';
12749 OP_I64 (int bytemode
, int sizeflag
)
12751 if (bytemode
!= v_mode
|| address_mode
!= mode_64bit
|| !(rex
& REX_W
))
12753 OP_I (bytemode
, sizeflag
);
12759 scratchbuf
[0] = '$';
12760 print_operand_value (scratchbuf
+ 1, 1, get64 ());
12761 oappend_maybe_intel (scratchbuf
);
12762 scratchbuf
[0] = '\0';
12766 OP_sI (int bytemode
, int sizeflag
)
12774 FETCH_DATA (the_info
, codep
+ 1);
12776 if ((op
& 0x80) != 0)
12778 if (bytemode
== b_T_mode
)
12780 if (address_mode
!= mode_64bit
12781 || !((sizeflag
& DFLAG
) || (rex
& REX_W
)))
12783 /* The operand-size prefix is overridden by a REX prefix. */
12784 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
12792 if (!(rex
& REX_W
))
12794 if (sizeflag
& DFLAG
)
12802 /* The operand-size prefix is overridden by a REX prefix. */
12803 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
12809 oappend (INTERNAL_DISASSEMBLER_ERROR
);
12813 scratchbuf
[0] = '$';
12814 print_operand_value (scratchbuf
+ 1, 1, op
);
12815 oappend_maybe_intel (scratchbuf
);
12819 OP_J (int bytemode
, int sizeflag
)
12823 bfd_vma segment
= 0;
12828 FETCH_DATA (the_info
, codep
+ 1);
12830 if ((disp
& 0x80) != 0)
12835 if ((sizeflag
& DFLAG
)
12836 || (address_mode
== mode_64bit
12837 && ((isa64
== intel64
&& bytemode
!= dqw_mode
)
12838 || (rex
& REX_W
))))
12843 if ((disp
& 0x8000) != 0)
12845 /* In 16bit mode, address is wrapped around at 64k within
12846 the same segment. Otherwise, a data16 prefix on a jump
12847 instruction means that the pc is masked to 16 bits after
12848 the displacement is added! */
12850 if ((prefixes
& PREFIX_DATA
) == 0)
12851 segment
= ((start_pc
+ (codep
- start_codep
))
12852 & ~((bfd_vma
) 0xffff));
12854 if (address_mode
!= mode_64bit
12855 || (isa64
!= intel64
&& !(rex
& REX_W
)))
12856 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12859 oappend (INTERNAL_DISASSEMBLER_ERROR
);
12862 disp
= ((start_pc
+ (codep
- start_codep
) + disp
) & mask
) | segment
;
12864 print_operand_value (scratchbuf
, 1, disp
);
12865 oappend (scratchbuf
);
12869 OP_SEG (int bytemode
, int sizeflag
)
12871 if (bytemode
== w_mode
)
12872 oappend (names_seg
[modrm
.reg
]);
12874 OP_E (modrm
.mod
== 3 ? bytemode
: w_mode
, sizeflag
);
12878 OP_DIR (int dummy ATTRIBUTE_UNUSED
, int sizeflag
)
12882 if (sizeflag
& DFLAG
)
12892 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12894 sprintf (scratchbuf
, "0x%x:0x%x", seg
, offset
);
12896 sprintf (scratchbuf
, "$0x%x,$0x%x", seg
, offset
);
12897 oappend (scratchbuf
);
12901 OP_OFF (int bytemode
, int sizeflag
)
12905 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
12906 intel_operand_size (bytemode
, sizeflag
);
12909 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
12916 if (!active_seg_prefix
)
12918 oappend (names_seg
[ds_reg
- es_reg
]);
12922 print_operand_value (scratchbuf
, 1, off
);
12923 oappend (scratchbuf
);
12927 OP_OFF64 (int bytemode
, int sizeflag
)
12931 if (address_mode
!= mode_64bit
12932 || (prefixes
& PREFIX_ADDR
))
12934 OP_OFF (bytemode
, sizeflag
);
12938 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
12939 intel_operand_size (bytemode
, sizeflag
);
12946 if (!active_seg_prefix
)
12948 oappend (names_seg
[ds_reg
- es_reg
]);
12952 print_operand_value (scratchbuf
, 1, off
);
12953 oappend (scratchbuf
);
12957 ptr_reg (int code
, int sizeflag
)
12961 *obufp
++ = open_char
;
12962 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
12963 if (address_mode
== mode_64bit
)
12965 if (!(sizeflag
& AFLAG
))
12966 s
= names32
[code
- eAX_reg
];
12968 s
= names64
[code
- eAX_reg
];
12970 else if (sizeflag
& AFLAG
)
12971 s
= names32
[code
- eAX_reg
];
12973 s
= names16
[code
- eAX_reg
];
12975 *obufp
++ = close_char
;
12980 OP_ESreg (int code
, int sizeflag
)
12986 case 0x6d: /* insw/insl */
12987 intel_operand_size (z_mode
, sizeflag
);
12989 case 0xa5: /* movsw/movsl/movsq */
12990 case 0xa7: /* cmpsw/cmpsl/cmpsq */
12991 case 0xab: /* stosw/stosl */
12992 case 0xaf: /* scasw/scasl */
12993 intel_operand_size (v_mode
, sizeflag
);
12996 intel_operand_size (b_mode
, sizeflag
);
12999 oappend_maybe_intel ("%es:");
13000 ptr_reg (code
, sizeflag
);
13004 OP_DSreg (int code
, int sizeflag
)
13010 case 0x6f: /* outsw/outsl */
13011 intel_operand_size (z_mode
, sizeflag
);
13013 case 0xa5: /* movsw/movsl/movsq */
13014 case 0xa7: /* cmpsw/cmpsl/cmpsq */
13015 case 0xad: /* lodsw/lodsl/lodsq */
13016 intel_operand_size (v_mode
, sizeflag
);
13019 intel_operand_size (b_mode
, sizeflag
);
13022 /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
13023 default segment register DS is printed. */
13024 if (!active_seg_prefix
)
13025 active_seg_prefix
= PREFIX_DS
;
13027 ptr_reg (code
, sizeflag
);
13031 OP_C (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
13039 else if (address_mode
!= mode_64bit
&& (prefixes
& PREFIX_LOCK
))
13041 all_prefixes
[last_lock_prefix
] = 0;
13042 used_prefixes
|= PREFIX_LOCK
;
13047 sprintf (scratchbuf
, "%%cr%d", modrm
.reg
+ add
);
13048 oappend_maybe_intel (scratchbuf
);
13052 OP_D (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
13061 sprintf (scratchbuf
, "dr%d", modrm
.reg
+ add
);
13063 sprintf (scratchbuf
, "%%db%d", modrm
.reg
+ add
);
13064 oappend (scratchbuf
);
13068 OP_T (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
13070 sprintf (scratchbuf
, "%%tr%d", modrm
.reg
);
13071 oappend_maybe_intel (scratchbuf
);
13075 OP_MMX (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
13077 int reg
= modrm
.reg
;
13078 const char **names
;
13080 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13081 if (prefixes
& PREFIX_DATA
)
13090 oappend (names
[reg
]);
13094 OP_XMM (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
13096 int reg
= modrm
.reg
;
13097 const char **names
;
13109 && bytemode
!= xmm_mode
13110 && bytemode
!= xmmq_mode
13111 && bytemode
!= evex_half_bcst_xmmq_mode
13112 && bytemode
!= ymm_mode
13113 && bytemode
!= tmm_mode
13114 && bytemode
!= scalar_mode
)
13116 switch (vex
.length
)
13123 || (bytemode
!= vex_vsib_q_w_dq_mode
13124 && bytemode
!= vex_vsib_q_w_d_mode
))
13136 else if (bytemode
== xmmq_mode
13137 || bytemode
== evex_half_bcst_xmmq_mode
)
13139 switch (vex
.length
)
13152 else if (bytemode
== tmm_mode
)
13162 else if (bytemode
== ymm_mode
)
13166 oappend (names
[reg
]);
13170 OP_EM (int bytemode
, int sizeflag
)
13173 const char **names
;
13175 if (modrm
.mod
!= 3)
13178 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
13180 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
13181 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13183 OP_E (bytemode
, sizeflag
);
13187 if ((sizeflag
& SUFFIX_ALWAYS
) && bytemode
== v_swap_mode
)
13190 /* Skip mod/rm byte. */
13193 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13195 if (prefixes
& PREFIX_DATA
)
13204 oappend (names
[reg
]);
13207 /* cvt* are the only instructions in sse2 which have
13208 both SSE and MMX operands and also have 0x66 prefix
13209 in their opcode. 0x66 was originally used to differentiate
13210 between SSE and MMX instruction(operands). So we have to handle the
13211 cvt* separately using OP_EMC and OP_MXC */
13213 OP_EMC (int bytemode
, int sizeflag
)
13215 if (modrm
.mod
!= 3)
13217 if (intel_syntax
&& bytemode
== v_mode
)
13219 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
13220 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13222 OP_E (bytemode
, sizeflag
);
13226 /* Skip mod/rm byte. */
13229 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13230 oappend (names_mm
[modrm
.rm
]);
13234 OP_MXC (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
13236 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13237 oappend (names_mm
[modrm
.reg
]);
13241 OP_EX (int bytemode
, int sizeflag
)
13244 const char **names
;
13246 /* Skip mod/rm byte. */
13250 if (modrm
.mod
!= 3)
13252 OP_E_memory (bytemode
, sizeflag
);
13267 if ((sizeflag
& SUFFIX_ALWAYS
)
13268 && (bytemode
== x_swap_mode
13269 || bytemode
== d_swap_mode
13270 || bytemode
== q_swap_mode
))
13274 && bytemode
!= xmm_mode
13275 && bytemode
!= xmmdw_mode
13276 && bytemode
!= xmmqd_mode
13277 && bytemode
!= xmm_mb_mode
13278 && bytemode
!= xmm_mw_mode
13279 && bytemode
!= xmm_md_mode
13280 && bytemode
!= xmm_mq_mode
13281 && bytemode
!= xmmq_mode
13282 && bytemode
!= evex_half_bcst_xmmq_mode
13283 && bytemode
!= ymm_mode
13284 && bytemode
!= tmm_mode
13285 && bytemode
!= vex_scalar_w_dq_mode
)
13287 switch (vex
.length
)
13302 else if (bytemode
== xmmq_mode
13303 || bytemode
== evex_half_bcst_xmmq_mode
)
13305 switch (vex
.length
)
13318 else if (bytemode
== tmm_mode
)
13328 else if (bytemode
== ymm_mode
)
13332 oappend (names
[reg
]);
13336 OP_MS (int bytemode
, int sizeflag
)
13338 if (modrm
.mod
== 3)
13339 OP_EM (bytemode
, sizeflag
);
13345 OP_XS (int bytemode
, int sizeflag
)
13347 if (modrm
.mod
== 3)
13348 OP_EX (bytemode
, sizeflag
);
13354 OP_M (int bytemode
, int sizeflag
)
13356 if (modrm
.mod
== 3)
13357 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
13360 OP_E (bytemode
, sizeflag
);
13364 OP_0f07 (int bytemode
, int sizeflag
)
13366 if (modrm
.mod
!= 3 || modrm
.rm
!= 0)
13369 OP_E (bytemode
, sizeflag
);
13372 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
13373 32bit mode and "xchg %rax,%rax" in 64bit mode. */
13376 NOP_Fixup1 (int bytemode
, int sizeflag
)
13378 if ((prefixes
& PREFIX_DATA
) != 0
13381 && address_mode
== mode_64bit
))
13382 OP_REG (bytemode
, sizeflag
);
13384 strcpy (obuf
, "nop");
13388 NOP_Fixup2 (int bytemode
, int sizeflag
)
13390 if ((prefixes
& PREFIX_DATA
) != 0
13393 && address_mode
== mode_64bit
))
13394 OP_IMREG (bytemode
, sizeflag
);
13397 static const char *const Suffix3DNow
[] = {
13398 /* 00 */ NULL
, NULL
, NULL
, NULL
,
13399 /* 04 */ NULL
, NULL
, NULL
, NULL
,
13400 /* 08 */ NULL
, NULL
, NULL
, NULL
,
13401 /* 0C */ "pi2fw", "pi2fd", NULL
, NULL
,
13402 /* 10 */ NULL
, NULL
, NULL
, NULL
,
13403 /* 14 */ NULL
, NULL
, NULL
, NULL
,
13404 /* 18 */ NULL
, NULL
, NULL
, NULL
,
13405 /* 1C */ "pf2iw", "pf2id", NULL
, NULL
,
13406 /* 20 */ NULL
, NULL
, NULL
, NULL
,
13407 /* 24 */ NULL
, NULL
, NULL
, NULL
,
13408 /* 28 */ NULL
, NULL
, NULL
, NULL
,
13409 /* 2C */ NULL
, NULL
, NULL
, NULL
,
13410 /* 30 */ NULL
, NULL
, NULL
, NULL
,
13411 /* 34 */ NULL
, NULL
, NULL
, NULL
,
13412 /* 38 */ NULL
, NULL
, NULL
, NULL
,
13413 /* 3C */ NULL
, NULL
, NULL
, NULL
,
13414 /* 40 */ NULL
, NULL
, NULL
, NULL
,
13415 /* 44 */ NULL
, NULL
, NULL
, NULL
,
13416 /* 48 */ NULL
, NULL
, NULL
, NULL
,
13417 /* 4C */ NULL
, NULL
, NULL
, NULL
,
13418 /* 50 */ NULL
, NULL
, NULL
, NULL
,
13419 /* 54 */ NULL
, NULL
, NULL
, NULL
,
13420 /* 58 */ NULL
, NULL
, NULL
, NULL
,
13421 /* 5C */ NULL
, NULL
, NULL
, NULL
,
13422 /* 60 */ NULL
, NULL
, NULL
, NULL
,
13423 /* 64 */ NULL
, NULL
, NULL
, NULL
,
13424 /* 68 */ NULL
, NULL
, NULL
, NULL
,
13425 /* 6C */ NULL
, NULL
, NULL
, NULL
,
13426 /* 70 */ NULL
, NULL
, NULL
, NULL
,
13427 /* 74 */ NULL
, NULL
, NULL
, NULL
,
13428 /* 78 */ NULL
, NULL
, NULL
, NULL
,
13429 /* 7C */ NULL
, NULL
, NULL
, NULL
,
13430 /* 80 */ NULL
, NULL
, NULL
, NULL
,
13431 /* 84 */ NULL
, NULL
, NULL
, NULL
,
13432 /* 88 */ NULL
, NULL
, "pfnacc", NULL
,
13433 /* 8C */ NULL
, NULL
, "pfpnacc", NULL
,
13434 /* 90 */ "pfcmpge", NULL
, NULL
, NULL
,
13435 /* 94 */ "pfmin", NULL
, "pfrcp", "pfrsqrt",
13436 /* 98 */ NULL
, NULL
, "pfsub", NULL
,
13437 /* 9C */ NULL
, NULL
, "pfadd", NULL
,
13438 /* A0 */ "pfcmpgt", NULL
, NULL
, NULL
,
13439 /* A4 */ "pfmax", NULL
, "pfrcpit1", "pfrsqit1",
13440 /* A8 */ NULL
, NULL
, "pfsubr", NULL
,
13441 /* AC */ NULL
, NULL
, "pfacc", NULL
,
13442 /* B0 */ "pfcmpeq", NULL
, NULL
, NULL
,
13443 /* B4 */ "pfmul", NULL
, "pfrcpit2", "pmulhrw",
13444 /* B8 */ NULL
, NULL
, NULL
, "pswapd",
13445 /* BC */ NULL
, NULL
, NULL
, "pavgusb",
13446 /* C0 */ NULL
, NULL
, NULL
, NULL
,
13447 /* C4 */ NULL
, NULL
, NULL
, NULL
,
13448 /* C8 */ NULL
, NULL
, NULL
, NULL
,
13449 /* CC */ NULL
, NULL
, NULL
, NULL
,
13450 /* D0 */ NULL
, NULL
, NULL
, NULL
,
13451 /* D4 */ NULL
, NULL
, NULL
, NULL
,
13452 /* D8 */ NULL
, NULL
, NULL
, NULL
,
13453 /* DC */ NULL
, NULL
, NULL
, NULL
,
13454 /* E0 */ NULL
, NULL
, NULL
, NULL
,
13455 /* E4 */ NULL
, NULL
, NULL
, NULL
,
13456 /* E8 */ NULL
, NULL
, NULL
, NULL
,
13457 /* EC */ NULL
, NULL
, NULL
, NULL
,
13458 /* F0 */ NULL
, NULL
, NULL
, NULL
,
13459 /* F4 */ NULL
, NULL
, NULL
, NULL
,
13460 /* F8 */ NULL
, NULL
, NULL
, NULL
,
13461 /* FC */ NULL
, NULL
, NULL
, NULL
,
13465 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
13467 const char *mnemonic
;
13469 FETCH_DATA (the_info
, codep
+ 1);
13470 /* AMD 3DNow! instructions are specified by an opcode suffix in the
13471 place where an 8-bit immediate would normally go. ie. the last
13472 byte of the instruction. */
13473 obufp
= mnemonicendp
;
13474 mnemonic
= Suffix3DNow
[*codep
++ & 0xff];
13476 oappend (mnemonic
);
13479 /* Since a variable sized modrm/sib chunk is between the start
13480 of the opcode (0x0f0f) and the opcode suffix, we need to do
13481 all the modrm processing first, and don't know until now that
13482 we have a bad opcode. This necessitates some cleaning up. */
13483 op_out
[0][0] = '\0';
13484 op_out
[1][0] = '\0';
13487 mnemonicendp
= obufp
;
13490 static const struct op simd_cmp_op
[] =
13492 { STRING_COMMA_LEN ("eq") },
13493 { STRING_COMMA_LEN ("lt") },
13494 { STRING_COMMA_LEN ("le") },
13495 { STRING_COMMA_LEN ("unord") },
13496 { STRING_COMMA_LEN ("neq") },
13497 { STRING_COMMA_LEN ("nlt") },
13498 { STRING_COMMA_LEN ("nle") },
13499 { STRING_COMMA_LEN ("ord") }
13502 static const struct op vex_cmp_op
[] =
13504 { STRING_COMMA_LEN ("eq_uq") },
13505 { STRING_COMMA_LEN ("nge") },
13506 { STRING_COMMA_LEN ("ngt") },
13507 { STRING_COMMA_LEN ("false") },
13508 { STRING_COMMA_LEN ("neq_oq") },
13509 { STRING_COMMA_LEN ("ge") },
13510 { STRING_COMMA_LEN ("gt") },
13511 { STRING_COMMA_LEN ("true") },
13512 { STRING_COMMA_LEN ("eq_os") },
13513 { STRING_COMMA_LEN ("lt_oq") },
13514 { STRING_COMMA_LEN ("le_oq") },
13515 { STRING_COMMA_LEN ("unord_s") },
13516 { STRING_COMMA_LEN ("neq_us") },
13517 { STRING_COMMA_LEN ("nlt_uq") },
13518 { STRING_COMMA_LEN ("nle_uq") },
13519 { STRING_COMMA_LEN ("ord_s") },
13520 { STRING_COMMA_LEN ("eq_us") },
13521 { STRING_COMMA_LEN ("nge_uq") },
13522 { STRING_COMMA_LEN ("ngt_uq") },
13523 { STRING_COMMA_LEN ("false_os") },
13524 { STRING_COMMA_LEN ("neq_os") },
13525 { STRING_COMMA_LEN ("ge_oq") },
13526 { STRING_COMMA_LEN ("gt_oq") },
13527 { STRING_COMMA_LEN ("true_us") },
13531 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
13533 unsigned int cmp_type
;
13535 FETCH_DATA (the_info
, codep
+ 1);
13536 cmp_type
= *codep
++ & 0xff;
13537 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
))
13540 char *p
= mnemonicendp
- 2;
13544 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
13545 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
13548 && cmp_type
< ARRAY_SIZE (simd_cmp_op
) + ARRAY_SIZE (vex_cmp_op
))
13551 char *p
= mnemonicendp
- 2;
13555 cmp_type
-= ARRAY_SIZE (simd_cmp_op
);
13556 sprintf (p
, "%s%s", vex_cmp_op
[cmp_type
].name
, suffix
);
13557 mnemonicendp
+= vex_cmp_op
[cmp_type
].len
;
13561 /* We have a reserved extension byte. Output it directly. */
13562 scratchbuf
[0] = '$';
13563 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
13564 oappend_maybe_intel (scratchbuf
);
13565 scratchbuf
[0] = '\0';
13570 OP_Mwait (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
13572 /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx */
13575 strcpy (op_out
[0], names32
[0]);
13576 strcpy (op_out
[1], names32
[1]);
13577 if (bytemode
== eBX_reg
)
13578 strcpy (op_out
[2], names32
[3]);
13579 two_source_ops
= 1;
13581 /* Skip mod/rm byte. */
13587 OP_Monitor (int bytemode ATTRIBUTE_UNUSED
,
13588 int sizeflag ATTRIBUTE_UNUSED
)
13590 /* monitor %{e,r,}ax,%ecx,%edx" */
13593 const char **names
= (address_mode
== mode_64bit
13594 ? names64
: names32
);
13596 if (prefixes
& PREFIX_ADDR
)
13598 /* Remove "addr16/addr32". */
13599 all_prefixes
[last_addr_prefix
] = 0;
13600 names
= (address_mode
!= mode_32bit
13601 ? names32
: names16
);
13602 used_prefixes
|= PREFIX_ADDR
;
13604 else if (address_mode
== mode_16bit
)
13606 strcpy (op_out
[0], names
[0]);
13607 strcpy (op_out
[1], names32
[1]);
13608 strcpy (op_out
[2], names32
[2]);
13609 two_source_ops
= 1;
13611 /* Skip mod/rm byte. */
13619 /* Throw away prefixes and 1st. opcode byte. */
13620 codep
= insn_codep
+ 1;
13625 REP_Fixup (int bytemode
, int sizeflag
)
13627 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
13629 if (prefixes
& PREFIX_REPZ
)
13630 all_prefixes
[last_repz_prefix
] = REP_PREFIX
;
13637 OP_IMREG (bytemode
, sizeflag
);
13640 OP_ESreg (bytemode
, sizeflag
);
13643 OP_DSreg (bytemode
, sizeflag
);
13652 SEP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
13654 if ( isa64
!= amd64
)
13659 mnemonicendp
= obufp
;
13663 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
13667 BND_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
13669 if (prefixes
& PREFIX_REPNZ
)
13670 all_prefixes
[last_repnz_prefix
] = BND_PREFIX
;
13673 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
13677 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED
,
13678 int sizeflag ATTRIBUTE_UNUSED
)
13681 /* Since active_seg_prefix is not set in 64-bit mode, check whether
13682 we've seen a PREFIX_DS. */
13683 if ((prefixes
& PREFIX_DS
) != 0
13684 && (address_mode
!= mode_64bit
|| last_data_prefix
< 0))
13686 /* NOTRACK prefix is only valid on indirect branch instructions.
13687 NB: DATA prefix is unsupported for Intel64. */
13688 active_seg_prefix
= 0;
13689 all_prefixes
[last_seg_prefix
] = NOTRACK_PREFIX
;
13693 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
13694 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
13698 HLE_Fixup1 (int bytemode
, int sizeflag
)
13701 && (prefixes
& PREFIX_LOCK
) != 0)
13703 if (prefixes
& PREFIX_REPZ
)
13704 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
13705 if (prefixes
& PREFIX_REPNZ
)
13706 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
13709 OP_E (bytemode
, sizeflag
);
13712 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
13713 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
13717 HLE_Fixup2 (int bytemode
, int sizeflag
)
13719 if (modrm
.mod
!= 3)
13721 if (prefixes
& PREFIX_REPZ
)
13722 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
13723 if (prefixes
& PREFIX_REPNZ
)
13724 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
13727 OP_E (bytemode
, sizeflag
);
13730 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
13731 "xrelease" for memory operand. No check for LOCK prefix. */
13734 HLE_Fixup3 (int bytemode
, int sizeflag
)
13737 && last_repz_prefix
> last_repnz_prefix
13738 && (prefixes
& PREFIX_REPZ
) != 0)
13739 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
13741 OP_E (bytemode
, sizeflag
);
13745 CMPXCHG8B_Fixup (int bytemode
, int sizeflag
)
13750 /* Change cmpxchg8b to cmpxchg16b. */
13751 char *p
= mnemonicendp
- 2;
13752 mnemonicendp
= stpcpy (p
, "16b");
13755 else if ((prefixes
& PREFIX_LOCK
) != 0)
13757 if (prefixes
& PREFIX_REPZ
)
13758 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
13759 if (prefixes
& PREFIX_REPNZ
)
13760 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
13763 OP_M (bytemode
, sizeflag
);
13767 XMM_Fixup (int reg
, int sizeflag ATTRIBUTE_UNUSED
)
13769 const char **names
;
13773 switch (vex
.length
)
13787 oappend (names
[reg
]);
13791 FXSAVE_Fixup (int bytemode
, int sizeflag
)
13793 /* Add proper suffix to "fxsave" and "fxrstor". */
13797 char *p
= mnemonicendp
;
13803 OP_M (bytemode
, sizeflag
);
13806 /* Display the destination register operand for instructions with
13810 OP_VEX (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
13813 const char **names
;
13818 reg
= vex
.register_specifier
;
13819 vex
.register_specifier
= 0;
13820 if (address_mode
!= mode_64bit
)
13822 else if (vex
.evex
&& !vex
.v
)
13825 if (bytemode
== vex_scalar_mode
)
13827 oappend (names_xmm
[reg
]);
13831 if (bytemode
== tmm_mode
)
13833 /* All 3 TMM registers must be distinct. */
13838 /* This must be the 3rd operand. */
13839 if (obufp
!= op_out
[2])
13841 oappend (names_tmm
[reg
]);
13842 if (reg
== modrm
.reg
|| reg
== modrm
.rm
)
13843 strcpy (obufp
, "/(bad)");
13846 if (modrm
.reg
== modrm
.rm
|| modrm
.reg
== reg
|| modrm
.rm
== reg
)
13849 && (modrm
.reg
== modrm
.rm
|| modrm
.reg
== reg
))
13850 strcat (op_out
[0], "/(bad)");
13852 && (modrm
.rm
== modrm
.reg
|| modrm
.rm
== reg
))
13853 strcat (op_out
[1], "/(bad)");
13859 switch (vex
.length
)
13865 case vex_vsib_q_w_dq_mode
:
13866 case vex_vsib_q_w_d_mode
:
13882 names
= names_mask
;
13895 case vex_vsib_q_w_dq_mode
:
13896 case vex_vsib_q_w_d_mode
:
13897 names
= vex
.w
? names_ymm
: names_xmm
;
13906 names
= names_mask
;
13909 /* See PR binutils/20893 for a reproducer. */
13921 oappend (names
[reg
]);
13925 OP_VexR (int bytemode
, int sizeflag
)
13927 if (modrm
.mod
== 3)
13928 OP_VEX (bytemode
, sizeflag
);
13932 OP_VexW (int bytemode
, int sizeflag
)
13934 OP_VEX (bytemode
, sizeflag
);
13938 /* Swap 2nd and 3rd operands. */
13939 strcpy (scratchbuf
, op_out
[2]);
13940 strcpy (op_out
[2], op_out
[1]);
13941 strcpy (op_out
[1], scratchbuf
);
13946 OP_REG_VexI4 (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
13949 const char **names
= names_xmm
;
13951 FETCH_DATA (the_info
, codep
+ 1);
13954 if (bytemode
!= x_mode
&& bytemode
!= scalar_mode
)
13958 if (address_mode
!= mode_64bit
)
13961 if (bytemode
== x_mode
&& vex
.length
== 256)
13964 oappend (names
[reg
]);
13968 /* Swap 3rd and 4th operands. */
13969 strcpy (scratchbuf
, op_out
[3]);
13970 strcpy (op_out
[3], op_out
[2]);
13971 strcpy (op_out
[2], scratchbuf
);
13976 OP_VexI4 (int bytemode ATTRIBUTE_UNUSED
,
13977 int sizeflag ATTRIBUTE_UNUSED
)
13979 scratchbuf
[0] = '$';
13980 print_operand_value (scratchbuf
+ 1, 1, codep
[-1] & 0xf);
13981 oappend_maybe_intel (scratchbuf
);
13985 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
,
13986 int sizeflag ATTRIBUTE_UNUSED
)
13988 unsigned int cmp_type
;
13993 FETCH_DATA (the_info
, codep
+ 1);
13994 cmp_type
= *codep
++ & 0xff;
13995 /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
13996 If it's the case, print suffix, otherwise - print the immediate. */
13997 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
)
14002 char *p
= mnemonicendp
- 2;
14004 /* vpcmp* can have both one- and two-lettered suffix. */
14018 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
14019 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
14023 /* We have a reserved extension byte. Output it directly. */
14024 scratchbuf
[0] = '$';
14025 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
14026 oappend_maybe_intel (scratchbuf
);
14027 scratchbuf
[0] = '\0';
14031 static const struct op xop_cmp_op
[] =
14033 { STRING_COMMA_LEN ("lt") },
14034 { STRING_COMMA_LEN ("le") },
14035 { STRING_COMMA_LEN ("gt") },
14036 { STRING_COMMA_LEN ("ge") },
14037 { STRING_COMMA_LEN ("eq") },
14038 { STRING_COMMA_LEN ("neq") },
14039 { STRING_COMMA_LEN ("false") },
14040 { STRING_COMMA_LEN ("true") }
14044 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED
,
14045 int sizeflag ATTRIBUTE_UNUSED
)
14047 unsigned int cmp_type
;
14049 FETCH_DATA (the_info
, codep
+ 1);
14050 cmp_type
= *codep
++ & 0xff;
14051 if (cmp_type
< ARRAY_SIZE (xop_cmp_op
))
14054 char *p
= mnemonicendp
- 2;
14056 /* vpcom* can have both one- and two-lettered suffix. */
14070 sprintf (p
, "%s%s", xop_cmp_op
[cmp_type
].name
, suffix
);
14071 mnemonicendp
+= xop_cmp_op
[cmp_type
].len
;
14075 /* We have a reserved extension byte. Output it directly. */
14076 scratchbuf
[0] = '$';
14077 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
14078 oappend_maybe_intel (scratchbuf
);
14079 scratchbuf
[0] = '\0';
14083 static const struct op pclmul_op
[] =
14085 { STRING_COMMA_LEN ("lql") },
14086 { STRING_COMMA_LEN ("hql") },
14087 { STRING_COMMA_LEN ("lqh") },
14088 { STRING_COMMA_LEN ("hqh") }
14092 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED
,
14093 int sizeflag ATTRIBUTE_UNUSED
)
14095 unsigned int pclmul_type
;
14097 FETCH_DATA (the_info
, codep
+ 1);
14098 pclmul_type
= *codep
++ & 0xff;
14099 switch (pclmul_type
)
14110 if (pclmul_type
< ARRAY_SIZE (pclmul_op
))
14113 char *p
= mnemonicendp
- 3;
14118 sprintf (p
, "%s%s", pclmul_op
[pclmul_type
].name
, suffix
);
14119 mnemonicendp
+= pclmul_op
[pclmul_type
].len
;
14123 /* We have a reserved extension byte. Output it directly. */
14124 scratchbuf
[0] = '$';
14125 print_operand_value (scratchbuf
+ 1, 1, pclmul_type
);
14126 oappend_maybe_intel (scratchbuf
);
14127 scratchbuf
[0] = '\0';
14132 MOVSXD_Fixup (int bytemode
, int sizeflag
)
14134 /* Add proper suffix to "movsxd". */
14135 char *p
= mnemonicendp
;
14160 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14167 OP_E (bytemode
, sizeflag
);
14171 OP_Mask (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
14174 || (bytemode
!= mask_mode
&& bytemode
!= mask_bd_mode
))
14178 if ((rex
& REX_R
) != 0 || !vex
.r
)
14184 oappend (names_mask
[modrm
.reg
]);
14188 OP_Rounding (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
14190 if (modrm
.mod
== 3 && vex
.b
)
14193 case evex_rounding_64_mode
:
14194 if (address_mode
!= mode_64bit
)
14199 /* Fall through. */
14200 case evex_rounding_mode
:
14201 oappend (names_rounding
[vex
.ll
]);
14203 case evex_sae_mode
: