1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988-2017 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
24 modified by John Hassey (hassey@dg-rtp.dg.com)
25 x86-64 support added by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
28 /* The main tables describing the instructions is essentially a copy
29 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30 Programmers Manual. Usually, there is a capital letter, followed
31 by a small letter. The capital letter tell the addressing mode,
32 and the small letter tells about the operand size. Refer to
33 the Intel manual for details. */
38 #include "opcode/i386.h"
39 #include "libiberty.h"
43 static int print_insn (bfd_vma
, disassemble_info
*);
44 static void dofloat (int);
45 static void OP_ST (int, int);
46 static void OP_STi (int, int);
47 static int putop (const char *, int);
48 static void oappend (const char *);
49 static void append_seg (void);
50 static void OP_indirE (int, int);
51 static void print_operand_value (char *, int, bfd_vma
);
52 static void OP_E_register (int, int);
53 static void OP_E_memory (int, int);
54 static void print_displacement (char *, bfd_vma
);
55 static void OP_E (int, int);
56 static void OP_G (int, int);
57 static bfd_vma
get64 (void);
58 static bfd_signed_vma
get32 (void);
59 static bfd_signed_vma
get32s (void);
60 static int get16 (void);
61 static void set_op (bfd_vma
, int);
62 static void OP_Skip_MODRM (int, int);
63 static void OP_REG (int, int);
64 static void OP_IMREG (int, int);
65 static void OP_I (int, int);
66 static void OP_I64 (int, int);
67 static void OP_sI (int, int);
68 static void OP_J (int, int);
69 static void OP_SEG (int, int);
70 static void OP_DIR (int, int);
71 static void OP_OFF (int, int);
72 static void OP_OFF64 (int, int);
73 static void ptr_reg (int, int);
74 static void OP_ESreg (int, int);
75 static void OP_DSreg (int, int);
76 static void OP_C (int, int);
77 static void OP_D (int, int);
78 static void OP_T (int, int);
79 static void OP_R (int, int);
80 static void OP_MMX (int, int);
81 static void OP_XMM (int, int);
82 static void OP_EM (int, int);
83 static void OP_EX (int, int);
84 static void OP_EMC (int,int);
85 static void OP_MXC (int,int);
86 static void OP_MS (int, int);
87 static void OP_XS (int, int);
88 static void OP_M (int, int);
89 static void OP_VEX (int, int);
90 static void OP_EX_Vex (int, int);
91 static void OP_EX_VexW (int, int);
92 static void OP_EX_VexImmW (int, int);
93 static void OP_XMM_Vex (int, int);
94 static void OP_XMM_VexW (int, int);
95 static void OP_Rounding (int, int);
96 static void OP_REG_VexI4 (int, int);
97 static void PCLMUL_Fixup (int, int);
98 static void VEXI4_Fixup (int, int);
99 static void VZERO_Fixup (int, int);
100 static void VCMP_Fixup (int, int);
101 static void VPCMP_Fixup (int, int);
102 static void OP_0f07 (int, int);
103 static void OP_Monitor (int, int);
104 static void OP_Mwait (int, int);
105 static void OP_Mwaitx (int, int);
106 static void NOP_Fixup1 (int, int);
107 static void NOP_Fixup2 (int, int);
108 static void OP_3DNowSuffix (int, int);
109 static void CMP_Fixup (int, int);
110 static void BadOp (void);
111 static void REP_Fixup (int, int);
112 static void BND_Fixup (int, int);
113 static void HLE_Fixup1 (int, int);
114 static void HLE_Fixup2 (int, int);
115 static void HLE_Fixup3 (int, int);
116 static void CMPXCHG8B_Fixup (int, int);
117 static void XMM_Fixup (int, int);
118 static void CRC32_Fixup (int, int);
119 static void FXSAVE_Fixup (int, int);
120 static void PCMPESTR_Fixup (int, int);
121 static void OP_LWPCB_E (int, int);
122 static void OP_LWP_E (int, int);
123 static void OP_Vex_2src_1 (int, int);
124 static void OP_Vex_2src_2 (int, int);
126 static void MOVBE_Fixup (int, int);
128 static void OP_Mask (int, int);
131 /* Points to first byte not fetched. */
132 bfd_byte
*max_fetched
;
133 bfd_byte the_buffer
[MAX_MNEM_SIZE
];
136 OPCODES_SIGJMP_BUF bailout
;
146 enum address_mode address_mode
;
148 /* Flags for the prefixes for the current instruction. See below. */
151 /* REX prefix the current instruction. See below. */
153 /* Bits of REX we've already used. */
155 /* REX bits in original REX prefix ignored. */
156 static int rex_ignored
;
157 /* Mark parts used in the REX prefix. When we are testing for
158 empty prefix (for 8bit register REX extension), just mask it
159 out. Otherwise test for REX bit is excuse for existence of REX
160 only in case value is nonzero. */
161 #define USED_REX(value) \
166 rex_used |= (value) | REX_OPCODE; \
169 rex_used |= REX_OPCODE; \
172 /* Flags for prefixes which we somehow handled when printing the
173 current instruction. */
174 static int used_prefixes
;
176 /* Flags stored in PREFIXES. */
177 #define PREFIX_REPZ 1
178 #define PREFIX_REPNZ 2
179 #define PREFIX_LOCK 4
181 #define PREFIX_SS 0x10
182 #define PREFIX_DS 0x20
183 #define PREFIX_ES 0x40
184 #define PREFIX_FS 0x80
185 #define PREFIX_GS 0x100
186 #define PREFIX_DATA 0x200
187 #define PREFIX_ADDR 0x400
188 #define PREFIX_FWAIT 0x800
190 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
191 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
193 #define FETCH_DATA(info, addr) \
194 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
195 ? 1 : fetch_data ((info), (addr)))
198 fetch_data (struct disassemble_info
*info
, bfd_byte
*addr
)
201 struct dis_private
*priv
= (struct dis_private
*) info
->private_data
;
202 bfd_vma start
= priv
->insn_start
+ (priv
->max_fetched
- priv
->the_buffer
);
204 if (addr
<= priv
->the_buffer
+ MAX_MNEM_SIZE
)
205 status
= (*info
->read_memory_func
) (start
,
207 addr
- priv
->max_fetched
,
213 /* If we did manage to read at least one byte, then
214 print_insn_i386 will do something sensible. Otherwise, print
215 an error. We do that here because this is where we know
217 if (priv
->max_fetched
== priv
->the_buffer
)
218 (*info
->memory_error_func
) (status
, start
, info
);
219 OPCODES_SIGLONGJMP (priv
->bailout
, 1);
222 priv
->max_fetched
= addr
;
226 /* Possible values for prefix requirement. */
227 #define PREFIX_IGNORED_SHIFT 16
228 #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
229 #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
230 #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
231 #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
232 #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
234 /* Opcode prefixes. */
235 #define PREFIX_OPCODE (PREFIX_REPZ \
239 /* Prefixes ignored. */
240 #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \
241 | PREFIX_IGNORED_REPNZ \
242 | PREFIX_IGNORED_DATA)
244 #define XX { NULL, 0 }
245 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
247 #define Eb { OP_E, b_mode }
248 #define Ebnd { OP_E, bnd_mode }
249 #define EbS { OP_E, b_swap_mode }
250 #define Ev { OP_E, v_mode }
251 #define Ev_bnd { OP_E, v_bnd_mode }
252 #define EvS { OP_E, v_swap_mode }
253 #define Ed { OP_E, d_mode }
254 #define Edq { OP_E, dq_mode }
255 #define Edqw { OP_E, dqw_mode }
256 #define Edqb { OP_E, dqb_mode }
257 #define Edb { OP_E, db_mode }
258 #define Edw { OP_E, dw_mode }
259 #define Edqd { OP_E, dqd_mode }
260 #define Eq { OP_E, q_mode }
261 #define indirEv { OP_indirE, indir_v_mode }
262 #define indirEp { OP_indirE, f_mode }
263 #define stackEv { OP_E, stack_v_mode }
264 #define Em { OP_E, m_mode }
265 #define Ew { OP_E, w_mode }
266 #define M { OP_M, 0 } /* lea, lgdt, etc. */
267 #define Ma { OP_M, a_mode }
268 #define Mb { OP_M, b_mode }
269 #define Md { OP_M, d_mode }
270 #define Mo { OP_M, o_mode }
271 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
272 #define Mq { OP_M, q_mode }
273 #define Mx { OP_M, x_mode }
274 #define Mxmm { OP_M, xmm_mode }
275 #define Gb { OP_G, b_mode }
276 #define Gbnd { OP_G, bnd_mode }
277 #define Gv { OP_G, v_mode }
278 #define Gd { OP_G, d_mode }
279 #define Gdq { OP_G, dq_mode }
280 #define Gm { OP_G, m_mode }
281 #define Gw { OP_G, w_mode }
282 #define Rd { OP_R, d_mode }
283 #define Rdq { OP_R, dq_mode }
284 #define Rm { OP_R, m_mode }
285 #define Ib { OP_I, b_mode }
286 #define sIb { OP_sI, b_mode } /* sign extened byte */
287 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
288 #define Iv { OP_I, v_mode }
289 #define sIv { OP_sI, v_mode }
290 #define Iq { OP_I, q_mode }
291 #define Iv64 { OP_I64, v_mode }
292 #define Iw { OP_I, w_mode }
293 #define I1 { OP_I, const_1_mode }
294 #define Jb { OP_J, b_mode }
295 #define Jv { OP_J, v_mode }
296 #define Cm { OP_C, m_mode }
297 #define Dm { OP_D, m_mode }
298 #define Td { OP_T, d_mode }
299 #define Skip_MODRM { OP_Skip_MODRM, 0 }
301 #define RMeAX { OP_REG, eAX_reg }
302 #define RMeBX { OP_REG, eBX_reg }
303 #define RMeCX { OP_REG, eCX_reg }
304 #define RMeDX { OP_REG, eDX_reg }
305 #define RMeSP { OP_REG, eSP_reg }
306 #define RMeBP { OP_REG, eBP_reg }
307 #define RMeSI { OP_REG, eSI_reg }
308 #define RMeDI { OP_REG, eDI_reg }
309 #define RMrAX { OP_REG, rAX_reg }
310 #define RMrBX { OP_REG, rBX_reg }
311 #define RMrCX { OP_REG, rCX_reg }
312 #define RMrDX { OP_REG, rDX_reg }
313 #define RMrSP { OP_REG, rSP_reg }
314 #define RMrBP { OP_REG, rBP_reg }
315 #define RMrSI { OP_REG, rSI_reg }
316 #define RMrDI { OP_REG, rDI_reg }
317 #define RMAL { OP_REG, al_reg }
318 #define RMCL { OP_REG, cl_reg }
319 #define RMDL { OP_REG, dl_reg }
320 #define RMBL { OP_REG, bl_reg }
321 #define RMAH { OP_REG, ah_reg }
322 #define RMCH { OP_REG, ch_reg }
323 #define RMDH { OP_REG, dh_reg }
324 #define RMBH { OP_REG, bh_reg }
325 #define RMAX { OP_REG, ax_reg }
326 #define RMDX { OP_REG, dx_reg }
328 #define eAX { OP_IMREG, eAX_reg }
329 #define eBX { OP_IMREG, eBX_reg }
330 #define eCX { OP_IMREG, eCX_reg }
331 #define eDX { OP_IMREG, eDX_reg }
332 #define eSP { OP_IMREG, eSP_reg }
333 #define eBP { OP_IMREG, eBP_reg }
334 #define eSI { OP_IMREG, eSI_reg }
335 #define eDI { OP_IMREG, eDI_reg }
336 #define AL { OP_IMREG, al_reg }
337 #define CL { OP_IMREG, cl_reg }
338 #define DL { OP_IMREG, dl_reg }
339 #define BL { OP_IMREG, bl_reg }
340 #define AH { OP_IMREG, ah_reg }
341 #define CH { OP_IMREG, ch_reg }
342 #define DH { OP_IMREG, dh_reg }
343 #define BH { OP_IMREG, bh_reg }
344 #define AX { OP_IMREG, ax_reg }
345 #define DX { OP_IMREG, dx_reg }
346 #define zAX { OP_IMREG, z_mode_ax_reg }
347 #define indirDX { OP_IMREG, indir_dx_reg }
349 #define Sw { OP_SEG, w_mode }
350 #define Sv { OP_SEG, v_mode }
351 #define Ap { OP_DIR, 0 }
352 #define Ob { OP_OFF64, b_mode }
353 #define Ov { OP_OFF64, v_mode }
354 #define Xb { OP_DSreg, eSI_reg }
355 #define Xv { OP_DSreg, eSI_reg }
356 #define Xz { OP_DSreg, eSI_reg }
357 #define Yb { OP_ESreg, eDI_reg }
358 #define Yv { OP_ESreg, eDI_reg }
359 #define DSBX { OP_DSreg, eBX_reg }
361 #define es { OP_REG, es_reg }
362 #define ss { OP_REG, ss_reg }
363 #define cs { OP_REG, cs_reg }
364 #define ds { OP_REG, ds_reg }
365 #define fs { OP_REG, fs_reg }
366 #define gs { OP_REG, gs_reg }
368 #define MX { OP_MMX, 0 }
369 #define XM { OP_XMM, 0 }
370 #define XMScalar { OP_XMM, scalar_mode }
371 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
372 #define XMM { OP_XMM, xmm_mode }
373 #define XMxmmq { OP_XMM, xmmq_mode }
374 #define EM { OP_EM, v_mode }
375 #define EMS { OP_EM, v_swap_mode }
376 #define EMd { OP_EM, d_mode }
377 #define EMx { OP_EM, x_mode }
378 #define EXw { OP_EX, w_mode }
379 #define EXd { OP_EX, d_mode }
380 #define EXdScalar { OP_EX, d_scalar_mode }
381 #define EXdS { OP_EX, d_swap_mode }
382 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
383 #define EXq { OP_EX, q_mode }
384 #define EXqScalar { OP_EX, q_scalar_mode }
385 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
386 #define EXqS { OP_EX, q_swap_mode }
387 #define EXx { OP_EX, x_mode }
388 #define EXxS { OP_EX, x_swap_mode }
389 #define EXxmm { OP_EX, xmm_mode }
390 #define EXymm { OP_EX, ymm_mode }
391 #define EXxmmq { OP_EX, xmmq_mode }
392 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
393 #define EXxmm_mb { OP_EX, xmm_mb_mode }
394 #define EXxmm_mw { OP_EX, xmm_mw_mode }
395 #define EXxmm_md { OP_EX, xmm_md_mode }
396 #define EXxmm_mq { OP_EX, xmm_mq_mode }
397 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
398 #define EXxmmdw { OP_EX, xmmdw_mode }
399 #define EXxmmqd { OP_EX, xmmqd_mode }
400 #define EXymmq { OP_EX, ymmq_mode }
401 #define EXVexWdq { OP_EX, vex_w_dq_mode }
402 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
403 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
404 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
405 #define MS { OP_MS, v_mode }
406 #define XS { OP_XS, v_mode }
407 #define EMCq { OP_EMC, q_mode }
408 #define MXC { OP_MXC, 0 }
409 #define OPSUF { OP_3DNowSuffix, 0 }
410 #define CMP { CMP_Fixup, 0 }
411 #define XMM0 { XMM_Fixup, 0 }
412 #define FXSAVE { FXSAVE_Fixup, 0 }
413 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
414 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
416 #define Vex { OP_VEX, vex_mode }
417 #define VexScalar { OP_VEX, vex_scalar_mode }
418 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
419 #define Vex128 { OP_VEX, vex128_mode }
420 #define Vex256 { OP_VEX, vex256_mode }
421 #define VexGdq { OP_VEX, dq_mode }
422 #define VexI4 { VEXI4_Fixup, 0}
423 #define EXdVex { OP_EX_Vex, d_mode }
424 #define EXdVexS { OP_EX_Vex, d_swap_mode }
425 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
426 #define EXqVex { OP_EX_Vex, q_mode }
427 #define EXqVexS { OP_EX_Vex, q_swap_mode }
428 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
429 #define EXVexW { OP_EX_VexW, x_mode }
430 #define EXdVexW { OP_EX_VexW, d_mode }
431 #define EXqVexW { OP_EX_VexW, q_mode }
432 #define EXVexImmW { OP_EX_VexImmW, x_mode }
433 #define XMVex { OP_XMM_Vex, 0 }
434 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
435 #define XMVexW { OP_XMM_VexW, 0 }
436 #define XMVexI4 { OP_REG_VexI4, x_mode }
437 #define PCLMUL { PCLMUL_Fixup, 0 }
438 #define VZERO { VZERO_Fixup, 0 }
439 #define VCMP { VCMP_Fixup, 0 }
440 #define VPCMP { VPCMP_Fixup, 0 }
442 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
443 #define EXxEVexS { OP_Rounding, evex_sae_mode }
445 #define XMask { OP_Mask, mask_mode }
446 #define MaskG { OP_G, mask_mode }
447 #define MaskE { OP_E, mask_mode }
448 #define MaskBDE { OP_E, mask_bd_mode }
449 #define MaskR { OP_R, mask_mode }
450 #define MaskVex { OP_VEX, mask_mode }
452 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
453 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
454 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
455 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
457 /* Used handle "rep" prefix for string instructions. */
458 #define Xbr { REP_Fixup, eSI_reg }
459 #define Xvr { REP_Fixup, eSI_reg }
460 #define Ybr { REP_Fixup, eDI_reg }
461 #define Yvr { REP_Fixup, eDI_reg }
462 #define Yzr { REP_Fixup, eDI_reg }
463 #define indirDXr { REP_Fixup, indir_dx_reg }
464 #define ALr { REP_Fixup, al_reg }
465 #define eAXr { REP_Fixup, eAX_reg }
467 /* Used handle HLE prefix for lockable instructions. */
468 #define Ebh1 { HLE_Fixup1, b_mode }
469 #define Evh1 { HLE_Fixup1, v_mode }
470 #define Ebh2 { HLE_Fixup2, b_mode }
471 #define Evh2 { HLE_Fixup2, v_mode }
472 #define Ebh3 { HLE_Fixup3, b_mode }
473 #define Evh3 { HLE_Fixup3, v_mode }
475 #define BND { BND_Fixup, 0 }
477 #define cond_jump_flag { NULL, cond_jump_mode }
478 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
480 /* bits in sizeflag */
481 #define SUFFIX_ALWAYS 4
489 /* byte operand with operand swapped */
491 /* byte operand, sign extend like 'T' suffix */
493 /* operand size depends on prefixes */
495 /* operand size depends on prefixes with operand swapped */
499 /* double word operand */
501 /* double word operand with operand swapped */
503 /* quad word operand */
505 /* quad word operand with operand swapped */
507 /* ten-byte operand */
509 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
510 broadcast enabled. */
512 /* Similar to x_mode, but with different EVEX mem shifts. */
514 /* Similar to x_mode, but with disabled broadcast. */
516 /* Similar to x_mode, but with operands swapped and disabled broadcast
519 /* 16-byte XMM operand */
521 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
522 memory operand (depending on vector length). Broadcast isn't
525 /* Same as xmmq_mode, but broadcast is allowed. */
526 evex_half_bcst_xmmq_mode
,
527 /* XMM register or byte memory operand */
529 /* XMM register or word memory operand */
531 /* XMM register or double word memory operand */
533 /* XMM register or quad word memory operand */
535 /* XMM register or double/quad word memory operand, depending on
538 /* 16-byte XMM, word, double word or quad word operand. */
540 /* 16-byte XMM, double word, quad word operand or xmm word operand. */
542 /* 32-byte YMM operand */
544 /* quad word, ymmword or zmmword memory operand. */
546 /* 32-byte YMM or 16-byte word operand */
548 /* d_mode in 32bit, q_mode in 64bit mode. */
550 /* pair of v_mode operands */
555 /* operand size depends on REX prefixes. */
557 /* registers like dq_mode, memory like w_mode. */
560 /* 4- or 6-byte pointer operand */
563 /* v_mode for indirect branch opcodes. */
565 /* v_mode for stack-related opcodes. */
567 /* non-quad operand size depends on prefixes */
569 /* 16-byte operand */
571 /* registers like dq_mode, memory like b_mode. */
573 /* registers like d_mode, memory like b_mode. */
575 /* registers like d_mode, memory like w_mode. */
577 /* registers like dq_mode, memory like d_mode. */
579 /* normal vex mode */
581 /* 128bit vex mode */
583 /* 256bit vex mode */
585 /* operand size depends on the VEX.W bit. */
588 /* Similar to vex_w_dq_mode, with VSIB dword indices. */
589 vex_vsib_d_w_dq_mode
,
590 /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */
592 /* Similar to vex_w_dq_mode, with VSIB qword indices. */
593 vex_vsib_q_w_dq_mode
,
594 /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */
597 /* scalar, ignore vector length. */
599 /* like d_mode, ignore vector length. */
601 /* like d_swap_mode, ignore vector length. */
603 /* like q_mode, ignore vector length. */
605 /* like q_swap_mode, ignore vector length. */
607 /* like vex_mode, ignore vector length. */
609 /* like vex_w_dq_mode, ignore vector length. */
610 vex_scalar_w_dq_mode
,
612 /* Static rounding. */
614 /* Supress all exceptions. */
617 /* Mask register operand. */
619 /* Mask register operand. */
686 #define FLOAT NULL, { { NULL, FLOATCODE } }, 0
688 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0
689 #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P
690 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
691 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
692 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
693 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
694 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
695 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
696 #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
697 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
698 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
699 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
700 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
701 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
702 #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I))
820 MOD_VEX_0F12_PREFIX_0
,
822 MOD_VEX_0F16_PREFIX_0
,
825 MOD_VEX_W_0_0F41_P_0_LEN_1
,
826 MOD_VEX_W_1_0F41_P_0_LEN_1
,
827 MOD_VEX_W_0_0F41_P_2_LEN_1
,
828 MOD_VEX_W_1_0F41_P_2_LEN_1
,
829 MOD_VEX_W_0_0F42_P_0_LEN_1
,
830 MOD_VEX_W_1_0F42_P_0_LEN_1
,
831 MOD_VEX_W_0_0F42_P_2_LEN_1
,
832 MOD_VEX_W_1_0F42_P_2_LEN_1
,
833 MOD_VEX_W_0_0F44_P_0_LEN_1
,
834 MOD_VEX_W_1_0F44_P_0_LEN_1
,
835 MOD_VEX_W_0_0F44_P_2_LEN_1
,
836 MOD_VEX_W_1_0F44_P_2_LEN_1
,
837 MOD_VEX_W_0_0F45_P_0_LEN_1
,
838 MOD_VEX_W_1_0F45_P_0_LEN_1
,
839 MOD_VEX_W_0_0F45_P_2_LEN_1
,
840 MOD_VEX_W_1_0F45_P_2_LEN_1
,
841 MOD_VEX_W_0_0F46_P_0_LEN_1
,
842 MOD_VEX_W_1_0F46_P_0_LEN_1
,
843 MOD_VEX_W_0_0F46_P_2_LEN_1
,
844 MOD_VEX_W_1_0F46_P_2_LEN_1
,
845 MOD_VEX_W_0_0F47_P_0_LEN_1
,
846 MOD_VEX_W_1_0F47_P_0_LEN_1
,
847 MOD_VEX_W_0_0F47_P_2_LEN_1
,
848 MOD_VEX_W_1_0F47_P_2_LEN_1
,
849 MOD_VEX_W_0_0F4A_P_0_LEN_1
,
850 MOD_VEX_W_1_0F4A_P_0_LEN_1
,
851 MOD_VEX_W_0_0F4A_P_2_LEN_1
,
852 MOD_VEX_W_1_0F4A_P_2_LEN_1
,
853 MOD_VEX_W_0_0F4B_P_0_LEN_1
,
854 MOD_VEX_W_1_0F4B_P_0_LEN_1
,
855 MOD_VEX_W_0_0F4B_P_2_LEN_1
,
867 MOD_VEX_W_0_0F91_P_0_LEN_0
,
868 MOD_VEX_W_1_0F91_P_0_LEN_0
,
869 MOD_VEX_W_0_0F91_P_2_LEN_0
,
870 MOD_VEX_W_1_0F91_P_2_LEN_0
,
871 MOD_VEX_W_0_0F92_P_0_LEN_0
,
872 MOD_VEX_W_0_0F92_P_2_LEN_0
,
873 MOD_VEX_W_0_0F92_P_3_LEN_0
,
874 MOD_VEX_W_1_0F92_P_3_LEN_0
,
875 MOD_VEX_W_0_0F93_P_0_LEN_0
,
876 MOD_VEX_W_0_0F93_P_2_LEN_0
,
877 MOD_VEX_W_0_0F93_P_3_LEN_0
,
878 MOD_VEX_W_1_0F93_P_3_LEN_0
,
879 MOD_VEX_W_0_0F98_P_0_LEN_0
,
880 MOD_VEX_W_1_0F98_P_0_LEN_0
,
881 MOD_VEX_W_0_0F98_P_2_LEN_0
,
882 MOD_VEX_W_1_0F98_P_2_LEN_0
,
883 MOD_VEX_W_0_0F99_P_0_LEN_0
,
884 MOD_VEX_W_1_0F99_P_0_LEN_0
,
885 MOD_VEX_W_0_0F99_P_2_LEN_0
,
886 MOD_VEX_W_1_0F99_P_2_LEN_0
,
889 MOD_VEX_0FD7_PREFIX_2
,
890 MOD_VEX_0FE7_PREFIX_2
,
891 MOD_VEX_0FF0_PREFIX_3
,
892 MOD_VEX_0F381A_PREFIX_2
,
893 MOD_VEX_0F382A_PREFIX_2
,
894 MOD_VEX_0F382C_PREFIX_2
,
895 MOD_VEX_0F382D_PREFIX_2
,
896 MOD_VEX_0F382E_PREFIX_2
,
897 MOD_VEX_0F382F_PREFIX_2
,
898 MOD_VEX_0F385A_PREFIX_2
,
899 MOD_VEX_0F388C_PREFIX_2
,
900 MOD_VEX_0F388E_PREFIX_2
,
901 MOD_VEX_W_0_0F3A30_P_2_LEN_0
,
902 MOD_VEX_W_1_0F3A30_P_2_LEN_0
,
903 MOD_VEX_W_0_0F3A31_P_2_LEN_0
,
904 MOD_VEX_W_1_0F3A31_P_2_LEN_0
,
905 MOD_VEX_W_0_0F3A32_P_2_LEN_0
,
906 MOD_VEX_W_1_0F3A32_P_2_LEN_0
,
907 MOD_VEX_W_0_0F3A33_P_2_LEN_0
,
908 MOD_VEX_W_1_0F3A33_P_2_LEN_0
,
910 MOD_EVEX_0F10_PREFIX_1
,
911 MOD_EVEX_0F10_PREFIX_3
,
912 MOD_EVEX_0F11_PREFIX_1
,
913 MOD_EVEX_0F11_PREFIX_3
,
914 MOD_EVEX_0F12_PREFIX_0
,
915 MOD_EVEX_0F16_PREFIX_0
,
916 MOD_EVEX_0F38C6_REG_1
,
917 MOD_EVEX_0F38C6_REG_2
,
918 MOD_EVEX_0F38C6_REG_5
,
919 MOD_EVEX_0F38C6_REG_6
,
920 MOD_EVEX_0F38C7_REG_1
,
921 MOD_EVEX_0F38C7_REG_2
,
922 MOD_EVEX_0F38C7_REG_5
,
923 MOD_EVEX_0F38C7_REG_6
986 PREFIX_MOD_0_0FAE_REG_4
,
987 PREFIX_MOD_3_0FAE_REG_4
,
995 PREFIX_MOD_0_0FC7_REG_6
,
996 PREFIX_MOD_3_0FC7_REG_6
,
997 PREFIX_MOD_3_0FC7_REG_7
,
1121 PREFIX_VEX_0F71_REG_2
,
1122 PREFIX_VEX_0F71_REG_4
,
1123 PREFIX_VEX_0F71_REG_6
,
1124 PREFIX_VEX_0F72_REG_2
,
1125 PREFIX_VEX_0F72_REG_4
,
1126 PREFIX_VEX_0F72_REG_6
,
1127 PREFIX_VEX_0F73_REG_2
,
1128 PREFIX_VEX_0F73_REG_3
,
1129 PREFIX_VEX_0F73_REG_6
,
1130 PREFIX_VEX_0F73_REG_7
,
1302 PREFIX_VEX_0F38F3_REG_1
,
1303 PREFIX_VEX_0F38F3_REG_2
,
1304 PREFIX_VEX_0F38F3_REG_3
,
1421 PREFIX_EVEX_0F71_REG_2
,
1422 PREFIX_EVEX_0F71_REG_4
,
1423 PREFIX_EVEX_0F71_REG_6
,
1424 PREFIX_EVEX_0F72_REG_0
,
1425 PREFIX_EVEX_0F72_REG_1
,
1426 PREFIX_EVEX_0F72_REG_2
,
1427 PREFIX_EVEX_0F72_REG_4
,
1428 PREFIX_EVEX_0F72_REG_6
,
1429 PREFIX_EVEX_0F73_REG_2
,
1430 PREFIX_EVEX_0F73_REG_3
,
1431 PREFIX_EVEX_0F73_REG_6
,
1432 PREFIX_EVEX_0F73_REG_7
,
1618 PREFIX_EVEX_0F38C6_REG_1
,
1619 PREFIX_EVEX_0F38C6_REG_2
,
1620 PREFIX_EVEX_0F38C6_REG_5
,
1621 PREFIX_EVEX_0F38C6_REG_6
,
1622 PREFIX_EVEX_0F38C7_REG_1
,
1623 PREFIX_EVEX_0F38C7_REG_2
,
1624 PREFIX_EVEX_0F38C7_REG_5
,
1625 PREFIX_EVEX_0F38C7_REG_6
,
1715 THREE_BYTE_0F38
= 0,
1742 VEX_LEN_0F10_P_1
= 0,
1746 VEX_LEN_0F12_P_0_M_0
,
1747 VEX_LEN_0F12_P_0_M_1
,
1750 VEX_LEN_0F16_P_0_M_0
,
1751 VEX_LEN_0F16_P_0_M_1
,
1815 VEX_LEN_0FAE_R_2_M_0
,
1816 VEX_LEN_0FAE_R_3_M_0
,
1825 VEX_LEN_0F381A_P_2_M_0
,
1828 VEX_LEN_0F385A_P_2_M_0
,
1835 VEX_LEN_0F38F3_R_1_P_0
,
1836 VEX_LEN_0F38F3_R_2_P_0
,
1837 VEX_LEN_0F38F3_R_3_P_0
,
1883 VEX_LEN_0FXOP_08_CC
,
1884 VEX_LEN_0FXOP_08_CD
,
1885 VEX_LEN_0FXOP_08_CE
,
1886 VEX_LEN_0FXOP_08_CF
,
1887 VEX_LEN_0FXOP_08_EC
,
1888 VEX_LEN_0FXOP_08_ED
,
1889 VEX_LEN_0FXOP_08_EE
,
1890 VEX_LEN_0FXOP_08_EF
,
1891 VEX_LEN_0FXOP_09_80
,
1925 VEX_W_0F41_P_0_LEN_1
,
1926 VEX_W_0F41_P_2_LEN_1
,
1927 VEX_W_0F42_P_0_LEN_1
,
1928 VEX_W_0F42_P_2_LEN_1
,
1929 VEX_W_0F44_P_0_LEN_0
,
1930 VEX_W_0F44_P_2_LEN_0
,
1931 VEX_W_0F45_P_0_LEN_1
,
1932 VEX_W_0F45_P_2_LEN_1
,
1933 VEX_W_0F46_P_0_LEN_1
,
1934 VEX_W_0F46_P_2_LEN_1
,
1935 VEX_W_0F47_P_0_LEN_1
,
1936 VEX_W_0F47_P_2_LEN_1
,
1937 VEX_W_0F4A_P_0_LEN_1
,
1938 VEX_W_0F4A_P_2_LEN_1
,
1939 VEX_W_0F4B_P_0_LEN_1
,
1940 VEX_W_0F4B_P_2_LEN_1
,
2020 VEX_W_0F90_P_0_LEN_0
,
2021 VEX_W_0F90_P_2_LEN_0
,
2022 VEX_W_0F91_P_0_LEN_0
,
2023 VEX_W_0F91_P_2_LEN_0
,
2024 VEX_W_0F92_P_0_LEN_0
,
2025 VEX_W_0F92_P_2_LEN_0
,
2026 VEX_W_0F92_P_3_LEN_0
,
2027 VEX_W_0F93_P_0_LEN_0
,
2028 VEX_W_0F93_P_2_LEN_0
,
2029 VEX_W_0F93_P_3_LEN_0
,
2030 VEX_W_0F98_P_0_LEN_0
,
2031 VEX_W_0F98_P_2_LEN_0
,
2032 VEX_W_0F99_P_0_LEN_0
,
2033 VEX_W_0F99_P_2_LEN_0
,
2112 VEX_W_0F381A_P_2_M_0
,
2124 VEX_W_0F382A_P_2_M_0
,
2126 VEX_W_0F382C_P_2_M_0
,
2127 VEX_W_0F382D_P_2_M_0
,
2128 VEX_W_0F382E_P_2_M_0
,
2129 VEX_W_0F382F_P_2_M_0
,
2151 VEX_W_0F385A_P_2_M_0
,
2179 VEX_W_0F3A30_P_2_LEN_0
,
2180 VEX_W_0F3A31_P_2_LEN_0
,
2181 VEX_W_0F3A32_P_2_LEN_0
,
2182 VEX_W_0F3A33_P_2_LEN_0
,
2200 EVEX_W_0F10_P_1_M_0
,
2201 EVEX_W_0F10_P_1_M_1
,
2203 EVEX_W_0F10_P_3_M_0
,
2204 EVEX_W_0F10_P_3_M_1
,
2206 EVEX_W_0F11_P_1_M_0
,
2207 EVEX_W_0F11_P_1_M_1
,
2209 EVEX_W_0F11_P_3_M_0
,
2210 EVEX_W_0F11_P_3_M_1
,
2211 EVEX_W_0F12_P_0_M_0
,
2212 EVEX_W_0F12_P_0_M_1
,
2222 EVEX_W_0F16_P_0_M_0
,
2223 EVEX_W_0F16_P_0_M_1
,
2294 EVEX_W_0F72_R_2_P_2
,
2295 EVEX_W_0F72_R_6_P_2
,
2296 EVEX_W_0F73_R_2_P_2
,
2297 EVEX_W_0F73_R_6_P_2
,
2398 EVEX_W_0F38C7_R_1_P_2
,
2399 EVEX_W_0F38C7_R_2_P_2
,
2400 EVEX_W_0F38C7_R_5_P_2
,
2401 EVEX_W_0F38C7_R_6_P_2
,
2436 typedef void (*op_rtn
) (int bytemode
, int sizeflag
);
2445 unsigned int prefix_requirement
;
2448 /* Upper case letters in the instruction names here are macros.
2449 'A' => print 'b' if no register operands or suffix_always is true
2450 'B' => print 'b' if suffix_always is true
2451 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2453 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2454 suffix_always is true
2455 'E' => print 'e' if 32-bit form of jcxz
2456 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2457 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2458 'H' => print ",pt" or ",pn" branch hint
2459 'I' => honor following macro letter even in Intel mode (implemented only
2460 for some of the macro letters)
2462 'K' => print 'd' or 'q' if rex prefix is present.
2463 'L' => print 'l' if suffix_always is true
2464 'M' => print 'r' if intel_mnemonic is false.
2465 'N' => print 'n' if instruction has no wait "prefix"
2466 'O' => print 'd' or 'o' (or 'q' in Intel mode)
2467 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2468 or suffix_always is true. print 'q' if rex prefix is present.
2469 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2471 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2472 'S' => print 'w', 'l' or 'q' if suffix_always is true
2473 'T' => print 'q' in 64bit mode if instruction has no operand size
2474 prefix and behave as 'P' otherwise
2475 'U' => print 'q' in 64bit mode if instruction has no operand size
2476 prefix and behave as 'Q' otherwise
2477 'V' => print 'q' in 64bit mode if instruction has no operand size
2478 prefix and behave as 'S' otherwise
2479 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2480 'X' => print 's', 'd' depending on data16 prefix (for XMM)
2481 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
2482 suffix_always is true.
2483 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2484 '!' => change condition from true to false or from false to true.
2485 '%' => add 1 upper case letter to the macro.
2486 '^' => print 'w' or 'l' depending on operand size prefix or
2487 suffix_always is true (lcall/ljmp).
2488 '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2489 on operand size prefix.
2490 '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2491 has no operand size prefix for AMD64 ISA, behave as 'P'
2494 2 upper case letter macros:
2495 "XY" => print 'x' or 'y' if suffix_always is true or no register
2496 operands and no broadcast.
2497 "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2498 register operands and no broadcast.
2499 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2500 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2501 or suffix_always is true
2502 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2503 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2504 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2505 "LW" => print 'd', 'q' depending on the VEX.W bit
2506 "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2507 an operand size prefix, or suffix_always is true. print
2508 'q' if rex prefix is present.
2510 Many of the above letters print nothing in Intel mode. See "putop"
2513 Braces '{' and '}', and vertical bars '|', indicate alternative
2514 mnemonic strings for AT&T and Intel. */
2516 static const struct dis386 dis386
[] = {
2518 { "addB", { Ebh1
, Gb
}, 0 },
2519 { "addS", { Evh1
, Gv
}, 0 },
2520 { "addB", { Gb
, EbS
}, 0 },
2521 { "addS", { Gv
, EvS
}, 0 },
2522 { "addB", { AL
, Ib
}, 0 },
2523 { "addS", { eAX
, Iv
}, 0 },
2524 { X86_64_TABLE (X86_64_06
) },
2525 { X86_64_TABLE (X86_64_07
) },
2527 { "orB", { Ebh1
, Gb
}, 0 },
2528 { "orS", { Evh1
, Gv
}, 0 },
2529 { "orB", { Gb
, EbS
}, 0 },
2530 { "orS", { Gv
, EvS
}, 0 },
2531 { "orB", { AL
, Ib
}, 0 },
2532 { "orS", { eAX
, Iv
}, 0 },
2533 { X86_64_TABLE (X86_64_0D
) },
2534 { Bad_Opcode
}, /* 0x0f extended opcode escape */
2536 { "adcB", { Ebh1
, Gb
}, 0 },
2537 { "adcS", { Evh1
, Gv
}, 0 },
2538 { "adcB", { Gb
, EbS
}, 0 },
2539 { "adcS", { Gv
, EvS
}, 0 },
2540 { "adcB", { AL
, Ib
}, 0 },
2541 { "adcS", { eAX
, Iv
}, 0 },
2542 { X86_64_TABLE (X86_64_16
) },
2543 { X86_64_TABLE (X86_64_17
) },
2545 { "sbbB", { Ebh1
, Gb
}, 0 },
2546 { "sbbS", { Evh1
, Gv
}, 0 },
2547 { "sbbB", { Gb
, EbS
}, 0 },
2548 { "sbbS", { Gv
, EvS
}, 0 },
2549 { "sbbB", { AL
, Ib
}, 0 },
2550 { "sbbS", { eAX
, Iv
}, 0 },
2551 { X86_64_TABLE (X86_64_1E
) },
2552 { X86_64_TABLE (X86_64_1F
) },
2554 { "andB", { Ebh1
, Gb
}, 0 },
2555 { "andS", { Evh1
, Gv
}, 0 },
2556 { "andB", { Gb
, EbS
}, 0 },
2557 { "andS", { Gv
, EvS
}, 0 },
2558 { "andB", { AL
, Ib
}, 0 },
2559 { "andS", { eAX
, Iv
}, 0 },
2560 { Bad_Opcode
}, /* SEG ES prefix */
2561 { X86_64_TABLE (X86_64_27
) },
2563 { "subB", { Ebh1
, Gb
}, 0 },
2564 { "subS", { Evh1
, Gv
}, 0 },
2565 { "subB", { Gb
, EbS
}, 0 },
2566 { "subS", { Gv
, EvS
}, 0 },
2567 { "subB", { AL
, Ib
}, 0 },
2568 { "subS", { eAX
, Iv
}, 0 },
2569 { Bad_Opcode
}, /* SEG CS prefix */
2570 { X86_64_TABLE (X86_64_2F
) },
2572 { "xorB", { Ebh1
, Gb
}, 0 },
2573 { "xorS", { Evh1
, Gv
}, 0 },
2574 { "xorB", { Gb
, EbS
}, 0 },
2575 { "xorS", { Gv
, EvS
}, 0 },
2576 { "xorB", { AL
, Ib
}, 0 },
2577 { "xorS", { eAX
, Iv
}, 0 },
2578 { Bad_Opcode
}, /* SEG SS prefix */
2579 { X86_64_TABLE (X86_64_37
) },
2581 { "cmpB", { Eb
, Gb
}, 0 },
2582 { "cmpS", { Ev
, Gv
}, 0 },
2583 { "cmpB", { Gb
, EbS
}, 0 },
2584 { "cmpS", { Gv
, EvS
}, 0 },
2585 { "cmpB", { AL
, Ib
}, 0 },
2586 { "cmpS", { eAX
, Iv
}, 0 },
2587 { Bad_Opcode
}, /* SEG DS prefix */
2588 { X86_64_TABLE (X86_64_3F
) },
2590 { "inc{S|}", { RMeAX
}, 0 },
2591 { "inc{S|}", { RMeCX
}, 0 },
2592 { "inc{S|}", { RMeDX
}, 0 },
2593 { "inc{S|}", { RMeBX
}, 0 },
2594 { "inc{S|}", { RMeSP
}, 0 },
2595 { "inc{S|}", { RMeBP
}, 0 },
2596 { "inc{S|}", { RMeSI
}, 0 },
2597 { "inc{S|}", { RMeDI
}, 0 },
2599 { "dec{S|}", { RMeAX
}, 0 },
2600 { "dec{S|}", { RMeCX
}, 0 },
2601 { "dec{S|}", { RMeDX
}, 0 },
2602 { "dec{S|}", { RMeBX
}, 0 },
2603 { "dec{S|}", { RMeSP
}, 0 },
2604 { "dec{S|}", { RMeBP
}, 0 },
2605 { "dec{S|}", { RMeSI
}, 0 },
2606 { "dec{S|}", { RMeDI
}, 0 },
2608 { "pushV", { RMrAX
}, 0 },
2609 { "pushV", { RMrCX
}, 0 },
2610 { "pushV", { RMrDX
}, 0 },
2611 { "pushV", { RMrBX
}, 0 },
2612 { "pushV", { RMrSP
}, 0 },
2613 { "pushV", { RMrBP
}, 0 },
2614 { "pushV", { RMrSI
}, 0 },
2615 { "pushV", { RMrDI
}, 0 },
2617 { "popV", { RMrAX
}, 0 },
2618 { "popV", { RMrCX
}, 0 },
2619 { "popV", { RMrDX
}, 0 },
2620 { "popV", { RMrBX
}, 0 },
2621 { "popV", { RMrSP
}, 0 },
2622 { "popV", { RMrBP
}, 0 },
2623 { "popV", { RMrSI
}, 0 },
2624 { "popV", { RMrDI
}, 0 },
2626 { X86_64_TABLE (X86_64_60
) },
2627 { X86_64_TABLE (X86_64_61
) },
2628 { X86_64_TABLE (X86_64_62
) },
2629 { X86_64_TABLE (X86_64_63
) },
2630 { Bad_Opcode
}, /* seg fs */
2631 { Bad_Opcode
}, /* seg gs */
2632 { Bad_Opcode
}, /* op size prefix */
2633 { Bad_Opcode
}, /* adr size prefix */
2635 { "pushT", { sIv
}, 0 },
2636 { "imulS", { Gv
, Ev
, Iv
}, 0 },
2637 { "pushT", { sIbT
}, 0 },
2638 { "imulS", { Gv
, Ev
, sIb
}, 0 },
2639 { "ins{b|}", { Ybr
, indirDX
}, 0 },
2640 { X86_64_TABLE (X86_64_6D
) },
2641 { "outs{b|}", { indirDXr
, Xb
}, 0 },
2642 { X86_64_TABLE (X86_64_6F
) },
2644 { "joH", { Jb
, BND
, cond_jump_flag
}, 0 },
2645 { "jnoH", { Jb
, BND
, cond_jump_flag
}, 0 },
2646 { "jbH", { Jb
, BND
, cond_jump_flag
}, 0 },
2647 { "jaeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2648 { "jeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2649 { "jneH", { Jb
, BND
, cond_jump_flag
}, 0 },
2650 { "jbeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2651 { "jaH", { Jb
, BND
, cond_jump_flag
}, 0 },
2653 { "jsH", { Jb
, BND
, cond_jump_flag
}, 0 },
2654 { "jnsH", { Jb
, BND
, cond_jump_flag
}, 0 },
2655 { "jpH", { Jb
, BND
, cond_jump_flag
}, 0 },
2656 { "jnpH", { Jb
, BND
, cond_jump_flag
}, 0 },
2657 { "jlH", { Jb
, BND
, cond_jump_flag
}, 0 },
2658 { "jgeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2659 { "jleH", { Jb
, BND
, cond_jump_flag
}, 0 },
2660 { "jgH", { Jb
, BND
, cond_jump_flag
}, 0 },
2662 { REG_TABLE (REG_80
) },
2663 { REG_TABLE (REG_81
) },
2664 { X86_64_TABLE (X86_64_82
) },
2665 { REG_TABLE (REG_83
) },
2666 { "testB", { Eb
, Gb
}, 0 },
2667 { "testS", { Ev
, Gv
}, 0 },
2668 { "xchgB", { Ebh2
, Gb
}, 0 },
2669 { "xchgS", { Evh2
, Gv
}, 0 },
2671 { "movB", { Ebh3
, Gb
}, 0 },
2672 { "movS", { Evh3
, Gv
}, 0 },
2673 { "movB", { Gb
, EbS
}, 0 },
2674 { "movS", { Gv
, EvS
}, 0 },
2675 { "movD", { Sv
, Sw
}, 0 },
2676 { MOD_TABLE (MOD_8D
) },
2677 { "movD", { Sw
, Sv
}, 0 },
2678 { REG_TABLE (REG_8F
) },
2680 { PREFIX_TABLE (PREFIX_90
) },
2681 { "xchgS", { RMeCX
, eAX
}, 0 },
2682 { "xchgS", { RMeDX
, eAX
}, 0 },
2683 { "xchgS", { RMeBX
, eAX
}, 0 },
2684 { "xchgS", { RMeSP
, eAX
}, 0 },
2685 { "xchgS", { RMeBP
, eAX
}, 0 },
2686 { "xchgS", { RMeSI
, eAX
}, 0 },
2687 { "xchgS", { RMeDI
, eAX
}, 0 },
2689 { "cW{t|}R", { XX
}, 0 },
2690 { "cR{t|}O", { XX
}, 0 },
2691 { X86_64_TABLE (X86_64_9A
) },
2692 { Bad_Opcode
}, /* fwait */
2693 { "pushfT", { XX
}, 0 },
2694 { "popfT", { XX
}, 0 },
2695 { "sahf", { XX
}, 0 },
2696 { "lahf", { XX
}, 0 },
2698 { "mov%LB", { AL
, Ob
}, 0 },
2699 { "mov%LS", { eAX
, Ov
}, 0 },
2700 { "mov%LB", { Ob
, AL
}, 0 },
2701 { "mov%LS", { Ov
, eAX
}, 0 },
2702 { "movs{b|}", { Ybr
, Xb
}, 0 },
2703 { "movs{R|}", { Yvr
, Xv
}, 0 },
2704 { "cmps{b|}", { Xb
, Yb
}, 0 },
2705 { "cmps{R|}", { Xv
, Yv
}, 0 },
2707 { "testB", { AL
, Ib
}, 0 },
2708 { "testS", { eAX
, Iv
}, 0 },
2709 { "stosB", { Ybr
, AL
}, 0 },
2710 { "stosS", { Yvr
, eAX
}, 0 },
2711 { "lodsB", { ALr
, Xb
}, 0 },
2712 { "lodsS", { eAXr
, Xv
}, 0 },
2713 { "scasB", { AL
, Yb
}, 0 },
2714 { "scasS", { eAX
, Yv
}, 0 },
2716 { "movB", { RMAL
, Ib
}, 0 },
2717 { "movB", { RMCL
, Ib
}, 0 },
2718 { "movB", { RMDL
, Ib
}, 0 },
2719 { "movB", { RMBL
, Ib
}, 0 },
2720 { "movB", { RMAH
, Ib
}, 0 },
2721 { "movB", { RMCH
, Ib
}, 0 },
2722 { "movB", { RMDH
, Ib
}, 0 },
2723 { "movB", { RMBH
, Ib
}, 0 },
2725 { "mov%LV", { RMeAX
, Iv64
}, 0 },
2726 { "mov%LV", { RMeCX
, Iv64
}, 0 },
2727 { "mov%LV", { RMeDX
, Iv64
}, 0 },
2728 { "mov%LV", { RMeBX
, Iv64
}, 0 },
2729 { "mov%LV", { RMeSP
, Iv64
}, 0 },
2730 { "mov%LV", { RMeBP
, Iv64
}, 0 },
2731 { "mov%LV", { RMeSI
, Iv64
}, 0 },
2732 { "mov%LV", { RMeDI
, Iv64
}, 0 },
2734 { REG_TABLE (REG_C0
) },
2735 { REG_TABLE (REG_C1
) },
2736 { "retT", { Iw
, BND
}, 0 },
2737 { "retT", { BND
}, 0 },
2738 { X86_64_TABLE (X86_64_C4
) },
2739 { X86_64_TABLE (X86_64_C5
) },
2740 { REG_TABLE (REG_C6
) },
2741 { REG_TABLE (REG_C7
) },
2743 { "enterT", { Iw
, Ib
}, 0 },
2744 { "leaveT", { XX
}, 0 },
2745 { "Jret{|f}P", { Iw
}, 0 },
2746 { "Jret{|f}P", { XX
}, 0 },
2747 { "int3", { XX
}, 0 },
2748 { "int", { Ib
}, 0 },
2749 { X86_64_TABLE (X86_64_CE
) },
2750 { "iret%LP", { XX
}, 0 },
2752 { REG_TABLE (REG_D0
) },
2753 { REG_TABLE (REG_D1
) },
2754 { REG_TABLE (REG_D2
) },
2755 { REG_TABLE (REG_D3
) },
2756 { X86_64_TABLE (X86_64_D4
) },
2757 { X86_64_TABLE (X86_64_D5
) },
2759 { "xlat", { DSBX
}, 0 },
2770 { "loopneFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2771 { "loopeFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2772 { "loopFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2773 { "jEcxzH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2774 { "inB", { AL
, Ib
}, 0 },
2775 { "inG", { zAX
, Ib
}, 0 },
2776 { "outB", { Ib
, AL
}, 0 },
2777 { "outG", { Ib
, zAX
}, 0 },
2779 { X86_64_TABLE (X86_64_E8
) },
2780 { X86_64_TABLE (X86_64_E9
) },
2781 { X86_64_TABLE (X86_64_EA
) },
2782 { "jmp", { Jb
, BND
}, 0 },
2783 { "inB", { AL
, indirDX
}, 0 },
2784 { "inG", { zAX
, indirDX
}, 0 },
2785 { "outB", { indirDX
, AL
}, 0 },
2786 { "outG", { indirDX
, zAX
}, 0 },
2788 { Bad_Opcode
}, /* lock prefix */
2789 { "icebp", { XX
}, 0 },
2790 { Bad_Opcode
}, /* repne */
2791 { Bad_Opcode
}, /* repz */
2792 { "hlt", { XX
}, 0 },
2793 { "cmc", { XX
}, 0 },
2794 { REG_TABLE (REG_F6
) },
2795 { REG_TABLE (REG_F7
) },
2797 { "clc", { XX
}, 0 },
2798 { "stc", { XX
}, 0 },
2799 { "cli", { XX
}, 0 },
2800 { "sti", { XX
}, 0 },
2801 { "cld", { XX
}, 0 },
2802 { "std", { XX
}, 0 },
2803 { REG_TABLE (REG_FE
) },
2804 { REG_TABLE (REG_FF
) },
2807 static const struct dis386 dis386_twobyte
[] = {
2809 { REG_TABLE (REG_0F00
) },
2810 { REG_TABLE (REG_0F01
) },
2811 { "larS", { Gv
, Ew
}, 0 },
2812 { "lslS", { Gv
, Ew
}, 0 },
2814 { "syscall", { XX
}, 0 },
2815 { "clts", { XX
}, 0 },
2816 { "sysret%LP", { XX
}, 0 },
2818 { "invd", { XX
}, 0 },
2819 { "wbinvd", { XX
}, 0 },
2821 { "ud2", { XX
}, 0 },
2823 { REG_TABLE (REG_0F0D
) },
2824 { "femms", { XX
}, 0 },
2825 { "", { MX
, EM
, OPSUF
}, 0 }, /* See OP_3DNowSuffix. */
2827 { PREFIX_TABLE (PREFIX_0F10
) },
2828 { PREFIX_TABLE (PREFIX_0F11
) },
2829 { PREFIX_TABLE (PREFIX_0F12
) },
2830 { MOD_TABLE (MOD_0F13
) },
2831 { "unpcklpX", { XM
, EXx
}, PREFIX_OPCODE
},
2832 { "unpckhpX", { XM
, EXx
}, PREFIX_OPCODE
},
2833 { PREFIX_TABLE (PREFIX_0F16
) },
2834 { MOD_TABLE (MOD_0F17
) },
2836 { REG_TABLE (REG_0F18
) },
2837 { "nopQ", { Ev
}, 0 },
2838 { PREFIX_TABLE (PREFIX_0F1A
) },
2839 { PREFIX_TABLE (PREFIX_0F1B
) },
2840 { "nopQ", { Ev
}, 0 },
2841 { "nopQ", { Ev
}, 0 },
2842 { "nopQ", { Ev
}, 0 },
2843 { "nopQ", { Ev
}, 0 },
2845 { "movZ", { Rm
, Cm
}, 0 },
2846 { "movZ", { Rm
, Dm
}, 0 },
2847 { "movZ", { Cm
, Rm
}, 0 },
2848 { "movZ", { Dm
, Rm
}, 0 },
2849 { MOD_TABLE (MOD_0F24
) },
2851 { MOD_TABLE (MOD_0F26
) },
2854 { "movapX", { XM
, EXx
}, PREFIX_OPCODE
},
2855 { "movapX", { EXxS
, XM
}, PREFIX_OPCODE
},
2856 { PREFIX_TABLE (PREFIX_0F2A
) },
2857 { PREFIX_TABLE (PREFIX_0F2B
) },
2858 { PREFIX_TABLE (PREFIX_0F2C
) },
2859 { PREFIX_TABLE (PREFIX_0F2D
) },
2860 { PREFIX_TABLE (PREFIX_0F2E
) },
2861 { PREFIX_TABLE (PREFIX_0F2F
) },
2863 { "wrmsr", { XX
}, 0 },
2864 { "rdtsc", { XX
}, 0 },
2865 { "rdmsr", { XX
}, 0 },
2866 { "rdpmc", { XX
}, 0 },
2867 { "sysenter", { XX
}, 0 },
2868 { "sysexit", { XX
}, 0 },
2870 { "getsec", { XX
}, 0 },
2872 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38
, PREFIX_OPCODE
) },
2874 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A
, PREFIX_OPCODE
) },
2881 { "cmovoS", { Gv
, Ev
}, 0 },
2882 { "cmovnoS", { Gv
, Ev
}, 0 },
2883 { "cmovbS", { Gv
, Ev
}, 0 },
2884 { "cmovaeS", { Gv
, Ev
}, 0 },
2885 { "cmoveS", { Gv
, Ev
}, 0 },
2886 { "cmovneS", { Gv
, Ev
}, 0 },
2887 { "cmovbeS", { Gv
, Ev
}, 0 },
2888 { "cmovaS", { Gv
, Ev
}, 0 },
2890 { "cmovsS", { Gv
, Ev
}, 0 },
2891 { "cmovnsS", { Gv
, Ev
}, 0 },
2892 { "cmovpS", { Gv
, Ev
}, 0 },
2893 { "cmovnpS", { Gv
, Ev
}, 0 },
2894 { "cmovlS", { Gv
, Ev
}, 0 },
2895 { "cmovgeS", { Gv
, Ev
}, 0 },
2896 { "cmovleS", { Gv
, Ev
}, 0 },
2897 { "cmovgS", { Gv
, Ev
}, 0 },
2899 { MOD_TABLE (MOD_0F51
) },
2900 { PREFIX_TABLE (PREFIX_0F51
) },
2901 { PREFIX_TABLE (PREFIX_0F52
) },
2902 { PREFIX_TABLE (PREFIX_0F53
) },
2903 { "andpX", { XM
, EXx
}, PREFIX_OPCODE
},
2904 { "andnpX", { XM
, EXx
}, PREFIX_OPCODE
},
2905 { "orpX", { XM
, EXx
}, PREFIX_OPCODE
},
2906 { "xorpX", { XM
, EXx
}, PREFIX_OPCODE
},
2908 { PREFIX_TABLE (PREFIX_0F58
) },
2909 { PREFIX_TABLE (PREFIX_0F59
) },
2910 { PREFIX_TABLE (PREFIX_0F5A
) },
2911 { PREFIX_TABLE (PREFIX_0F5B
) },
2912 { PREFIX_TABLE (PREFIX_0F5C
) },
2913 { PREFIX_TABLE (PREFIX_0F5D
) },
2914 { PREFIX_TABLE (PREFIX_0F5E
) },
2915 { PREFIX_TABLE (PREFIX_0F5F
) },
2917 { PREFIX_TABLE (PREFIX_0F60
) },
2918 { PREFIX_TABLE (PREFIX_0F61
) },
2919 { PREFIX_TABLE (PREFIX_0F62
) },
2920 { "packsswb", { MX
, EM
}, PREFIX_OPCODE
},
2921 { "pcmpgtb", { MX
, EM
}, PREFIX_OPCODE
},
2922 { "pcmpgtw", { MX
, EM
}, PREFIX_OPCODE
},
2923 { "pcmpgtd", { MX
, EM
}, PREFIX_OPCODE
},
2924 { "packuswb", { MX
, EM
}, PREFIX_OPCODE
},
2926 { "punpckhbw", { MX
, EM
}, PREFIX_OPCODE
},
2927 { "punpckhwd", { MX
, EM
}, PREFIX_OPCODE
},
2928 { "punpckhdq", { MX
, EM
}, PREFIX_OPCODE
},
2929 { "packssdw", { MX
, EM
}, PREFIX_OPCODE
},
2930 { PREFIX_TABLE (PREFIX_0F6C
) },
2931 { PREFIX_TABLE (PREFIX_0F6D
) },
2932 { "movK", { MX
, Edq
}, PREFIX_OPCODE
},
2933 { PREFIX_TABLE (PREFIX_0F6F
) },
2935 { PREFIX_TABLE (PREFIX_0F70
) },
2936 { REG_TABLE (REG_0F71
) },
2937 { REG_TABLE (REG_0F72
) },
2938 { REG_TABLE (REG_0F73
) },
2939 { "pcmpeqb", { MX
, EM
}, PREFIX_OPCODE
},
2940 { "pcmpeqw", { MX
, EM
}, PREFIX_OPCODE
},
2941 { "pcmpeqd", { MX
, EM
}, PREFIX_OPCODE
},
2942 { "emms", { XX
}, PREFIX_OPCODE
},
2944 { PREFIX_TABLE (PREFIX_0F78
) },
2945 { PREFIX_TABLE (PREFIX_0F79
) },
2948 { PREFIX_TABLE (PREFIX_0F7C
) },
2949 { PREFIX_TABLE (PREFIX_0F7D
) },
2950 { PREFIX_TABLE (PREFIX_0F7E
) },
2951 { PREFIX_TABLE (PREFIX_0F7F
) },
2953 { "joH", { Jv
, BND
, cond_jump_flag
}, 0 },
2954 { "jnoH", { Jv
, BND
, cond_jump_flag
}, 0 },
2955 { "jbH", { Jv
, BND
, cond_jump_flag
}, 0 },
2956 { "jaeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2957 { "jeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2958 { "jneH", { Jv
, BND
, cond_jump_flag
}, 0 },
2959 { "jbeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2960 { "jaH", { Jv
, BND
, cond_jump_flag
}, 0 },
2962 { "jsH", { Jv
, BND
, cond_jump_flag
}, 0 },
2963 { "jnsH", { Jv
, BND
, cond_jump_flag
}, 0 },
2964 { "jpH", { Jv
, BND
, cond_jump_flag
}, 0 },
2965 { "jnpH", { Jv
, BND
, cond_jump_flag
}, 0 },
2966 { "jlH", { Jv
, BND
, cond_jump_flag
}, 0 },
2967 { "jgeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2968 { "jleH", { Jv
, BND
, cond_jump_flag
}, 0 },
2969 { "jgH", { Jv
, BND
, cond_jump_flag
}, 0 },
2971 { "seto", { Eb
}, 0 },
2972 { "setno", { Eb
}, 0 },
2973 { "setb", { Eb
}, 0 },
2974 { "setae", { Eb
}, 0 },
2975 { "sete", { Eb
}, 0 },
2976 { "setne", { Eb
}, 0 },
2977 { "setbe", { Eb
}, 0 },
2978 { "seta", { Eb
}, 0 },
2980 { "sets", { Eb
}, 0 },
2981 { "setns", { Eb
}, 0 },
2982 { "setp", { Eb
}, 0 },
2983 { "setnp", { Eb
}, 0 },
2984 { "setl", { Eb
}, 0 },
2985 { "setge", { Eb
}, 0 },
2986 { "setle", { Eb
}, 0 },
2987 { "setg", { Eb
}, 0 },
2989 { "pushT", { fs
}, 0 },
2990 { "popT", { fs
}, 0 },
2991 { "cpuid", { XX
}, 0 },
2992 { "btS", { Ev
, Gv
}, 0 },
2993 { "shldS", { Ev
, Gv
, Ib
}, 0 },
2994 { "shldS", { Ev
, Gv
, CL
}, 0 },
2995 { REG_TABLE (REG_0FA6
) },
2996 { REG_TABLE (REG_0FA7
) },
2998 { "pushT", { gs
}, 0 },
2999 { "popT", { gs
}, 0 },
3000 { "rsm", { XX
}, 0 },
3001 { "btsS", { Evh1
, Gv
}, 0 },
3002 { "shrdS", { Ev
, Gv
, Ib
}, 0 },
3003 { "shrdS", { Ev
, Gv
, CL
}, 0 },
3004 { REG_TABLE (REG_0FAE
) },
3005 { "imulS", { Gv
, Ev
}, 0 },
3007 { "cmpxchgB", { Ebh1
, Gb
}, 0 },
3008 { "cmpxchgS", { Evh1
, Gv
}, 0 },
3009 { MOD_TABLE (MOD_0FB2
) },
3010 { "btrS", { Evh1
, Gv
}, 0 },
3011 { MOD_TABLE (MOD_0FB4
) },
3012 { MOD_TABLE (MOD_0FB5
) },
3013 { "movz{bR|x}", { Gv
, Eb
}, 0 },
3014 { "movz{wR|x}", { Gv
, Ew
}, 0 }, /* yes, there really is movzww ! */
3016 { PREFIX_TABLE (PREFIX_0FB8
) },
3017 { "ud1", { XX
}, 0 },
3018 { REG_TABLE (REG_0FBA
) },
3019 { "btcS", { Evh1
, Gv
}, 0 },
3020 { PREFIX_TABLE (PREFIX_0FBC
) },
3021 { PREFIX_TABLE (PREFIX_0FBD
) },
3022 { "movs{bR|x}", { Gv
, Eb
}, 0 },
3023 { "movs{wR|x}", { Gv
, Ew
}, 0 }, /* yes, there really is movsww ! */
3025 { "xaddB", { Ebh1
, Gb
}, 0 },
3026 { "xaddS", { Evh1
, Gv
}, 0 },
3027 { PREFIX_TABLE (PREFIX_0FC2
) },
3028 { MOD_TABLE (MOD_0FC3
) },
3029 { "pinsrw", { MX
, Edqw
, Ib
}, PREFIX_OPCODE
},
3030 { "pextrw", { Gdq
, MS
, Ib
}, PREFIX_OPCODE
},
3031 { "shufpX", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3032 { REG_TABLE (REG_0FC7
) },
3034 { "bswap", { RMeAX
}, 0 },
3035 { "bswap", { RMeCX
}, 0 },
3036 { "bswap", { RMeDX
}, 0 },
3037 { "bswap", { RMeBX
}, 0 },
3038 { "bswap", { RMeSP
}, 0 },
3039 { "bswap", { RMeBP
}, 0 },
3040 { "bswap", { RMeSI
}, 0 },
3041 { "bswap", { RMeDI
}, 0 },
3043 { PREFIX_TABLE (PREFIX_0FD0
) },
3044 { "psrlw", { MX
, EM
}, PREFIX_OPCODE
},
3045 { "psrld", { MX
, EM
}, PREFIX_OPCODE
},
3046 { "psrlq", { MX
, EM
}, PREFIX_OPCODE
},
3047 { "paddq", { MX
, EM
}, PREFIX_OPCODE
},
3048 { "pmullw", { MX
, EM
}, PREFIX_OPCODE
},
3049 { PREFIX_TABLE (PREFIX_0FD6
) },
3050 { MOD_TABLE (MOD_0FD7
) },
3052 { "psubusb", { MX
, EM
}, PREFIX_OPCODE
},
3053 { "psubusw", { MX
, EM
}, PREFIX_OPCODE
},
3054 { "pminub", { MX
, EM
}, PREFIX_OPCODE
},
3055 { "pand", { MX
, EM
}, PREFIX_OPCODE
},
3056 { "paddusb", { MX
, EM
}, PREFIX_OPCODE
},
3057 { "paddusw", { MX
, EM
}, PREFIX_OPCODE
},
3058 { "pmaxub", { MX
, EM
}, PREFIX_OPCODE
},
3059 { "pandn", { MX
, EM
}, PREFIX_OPCODE
},
3061 { "pavgb", { MX
, EM
}, PREFIX_OPCODE
},
3062 { "psraw", { MX
, EM
}, PREFIX_OPCODE
},
3063 { "psrad", { MX
, EM
}, PREFIX_OPCODE
},
3064 { "pavgw", { MX
, EM
}, PREFIX_OPCODE
},
3065 { "pmulhuw", { MX
, EM
}, PREFIX_OPCODE
},
3066 { "pmulhw", { MX
, EM
}, PREFIX_OPCODE
},
3067 { PREFIX_TABLE (PREFIX_0FE6
) },
3068 { PREFIX_TABLE (PREFIX_0FE7
) },
3070 { "psubsb", { MX
, EM
}, PREFIX_OPCODE
},
3071 { "psubsw", { MX
, EM
}, PREFIX_OPCODE
},
3072 { "pminsw", { MX
, EM
}, PREFIX_OPCODE
},
3073 { "por", { MX
, EM
}, PREFIX_OPCODE
},
3074 { "paddsb", { MX
, EM
}, PREFIX_OPCODE
},
3075 { "paddsw", { MX
, EM
}, PREFIX_OPCODE
},
3076 { "pmaxsw", { MX
, EM
}, PREFIX_OPCODE
},
3077 { "pxor", { MX
, EM
}, PREFIX_OPCODE
},
3079 { PREFIX_TABLE (PREFIX_0FF0
) },
3080 { "psllw", { MX
, EM
}, PREFIX_OPCODE
},
3081 { "pslld", { MX
, EM
}, PREFIX_OPCODE
},
3082 { "psllq", { MX
, EM
}, PREFIX_OPCODE
},
3083 { "pmuludq", { MX
, EM
}, PREFIX_OPCODE
},
3084 { "pmaddwd", { MX
, EM
}, PREFIX_OPCODE
},
3085 { "psadbw", { MX
, EM
}, PREFIX_OPCODE
},
3086 { PREFIX_TABLE (PREFIX_0FF7
) },
3088 { "psubb", { MX
, EM
}, PREFIX_OPCODE
},
3089 { "psubw", { MX
, EM
}, PREFIX_OPCODE
},
3090 { "psubd", { MX
, EM
}, PREFIX_OPCODE
},
3091 { "psubq", { MX
, EM
}, PREFIX_OPCODE
},
3092 { "paddb", { MX
, EM
}, PREFIX_OPCODE
},
3093 { "paddw", { MX
, EM
}, PREFIX_OPCODE
},
3094 { "paddd", { MX
, EM
}, PREFIX_OPCODE
},
3098 static const unsigned char onebyte_has_modrm
[256] = {
3099 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3100 /* ------------------------------- */
3101 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
3102 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
3103 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
3104 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
3105 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
3106 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
3107 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
3108 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
3109 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
3110 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
3111 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
3112 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
3113 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
3114 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
3115 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
3116 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
3117 /* ------------------------------- */
3118 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3121 static const unsigned char twobyte_has_modrm
[256] = {
3122 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3123 /* ------------------------------- */
3124 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
3125 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
3126 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
3127 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
3128 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
3129 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
3130 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
3131 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
3132 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
3133 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
3134 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
3135 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
3136 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
3137 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
3138 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
3139 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
3140 /* ------------------------------- */
3141 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3144 static char obuf
[100];
3146 static char *mnemonicendp
;
3147 static char scratchbuf
[100];
3148 static unsigned char *start_codep
;
3149 static unsigned char *insn_codep
;
3150 static unsigned char *codep
;
3151 static unsigned char *end_codep
;
3152 static int last_lock_prefix
;
3153 static int last_repz_prefix
;
3154 static int last_repnz_prefix
;
3155 static int last_data_prefix
;
3156 static int last_addr_prefix
;
3157 static int last_rex_prefix
;
3158 static int last_seg_prefix
;
3159 static int fwait_prefix
;
3160 /* The active segment register prefix. */
3161 static int active_seg_prefix
;
3162 #define MAX_CODE_LENGTH 15
3163 /* We can up to 14 prefixes since the maximum instruction length is
3165 static int all_prefixes
[MAX_CODE_LENGTH
- 1];
3166 static disassemble_info
*the_info
;
3174 static unsigned char need_modrm
;
3184 int register_specifier
;
3191 int mask_register_specifier
;
3197 static unsigned char need_vex
;
3198 static unsigned char need_vex_reg
;
3199 static unsigned char vex_w_done
;
3207 /* If we are accessing mod/rm/reg without need_modrm set, then the
3208 values are stale. Hitting this abort likely indicates that you
3209 need to update onebyte_has_modrm or twobyte_has_modrm. */
3210 #define MODRM_CHECK if (!need_modrm) abort ()
3212 static const char **names64
;
3213 static const char **names32
;
3214 static const char **names16
;
3215 static const char **names8
;
3216 static const char **names8rex
;
3217 static const char **names_seg
;
3218 static const char *index64
;
3219 static const char *index32
;
3220 static const char **index16
;
3221 static const char **names_bnd
;
3223 static const char *intel_names64
[] = {
3224 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3225 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3227 static const char *intel_names32
[] = {
3228 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3229 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3231 static const char *intel_names16
[] = {
3232 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3233 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3235 static const char *intel_names8
[] = {
3236 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3238 static const char *intel_names8rex
[] = {
3239 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3240 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3242 static const char *intel_names_seg
[] = {
3243 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3245 static const char *intel_index64
= "riz";
3246 static const char *intel_index32
= "eiz";
3247 static const char *intel_index16
[] = {
3248 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3251 static const char *att_names64
[] = {
3252 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3253 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3255 static const char *att_names32
[] = {
3256 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3257 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3259 static const char *att_names16
[] = {
3260 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3261 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3263 static const char *att_names8
[] = {
3264 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3266 static const char *att_names8rex
[] = {
3267 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3268 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3270 static const char *att_names_seg
[] = {
3271 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3273 static const char *att_index64
= "%riz";
3274 static const char *att_index32
= "%eiz";
3275 static const char *att_index16
[] = {
3276 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3279 static const char **names_mm
;
3280 static const char *intel_names_mm
[] = {
3281 "mm0", "mm1", "mm2", "mm3",
3282 "mm4", "mm5", "mm6", "mm7"
3284 static const char *att_names_mm
[] = {
3285 "%mm0", "%mm1", "%mm2", "%mm3",
3286 "%mm4", "%mm5", "%mm6", "%mm7"
3289 static const char *intel_names_bnd
[] = {
3290 "bnd0", "bnd1", "bnd2", "bnd3"
3293 static const char *att_names_bnd
[] = {
3294 "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3297 static const char **names_xmm
;
3298 static const char *intel_names_xmm
[] = {
3299 "xmm0", "xmm1", "xmm2", "xmm3",
3300 "xmm4", "xmm5", "xmm6", "xmm7",
3301 "xmm8", "xmm9", "xmm10", "xmm11",
3302 "xmm12", "xmm13", "xmm14", "xmm15",
3303 "xmm16", "xmm17", "xmm18", "xmm19",
3304 "xmm20", "xmm21", "xmm22", "xmm23",
3305 "xmm24", "xmm25", "xmm26", "xmm27",
3306 "xmm28", "xmm29", "xmm30", "xmm31"
3308 static const char *att_names_xmm
[] = {
3309 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3310 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3311 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3312 "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3313 "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3314 "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3315 "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3316 "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3319 static const char **names_ymm
;
3320 static const char *intel_names_ymm
[] = {
3321 "ymm0", "ymm1", "ymm2", "ymm3",
3322 "ymm4", "ymm5", "ymm6", "ymm7",
3323 "ymm8", "ymm9", "ymm10", "ymm11",
3324 "ymm12", "ymm13", "ymm14", "ymm15",
3325 "ymm16", "ymm17", "ymm18", "ymm19",
3326 "ymm20", "ymm21", "ymm22", "ymm23",
3327 "ymm24", "ymm25", "ymm26", "ymm27",
3328 "ymm28", "ymm29", "ymm30", "ymm31"
3330 static const char *att_names_ymm
[] = {
3331 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3332 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3333 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3334 "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3335 "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3336 "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3337 "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3338 "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3341 static const char **names_zmm
;
3342 static const char *intel_names_zmm
[] = {
3343 "zmm0", "zmm1", "zmm2", "zmm3",
3344 "zmm4", "zmm5", "zmm6", "zmm7",
3345 "zmm8", "zmm9", "zmm10", "zmm11",
3346 "zmm12", "zmm13", "zmm14", "zmm15",
3347 "zmm16", "zmm17", "zmm18", "zmm19",
3348 "zmm20", "zmm21", "zmm22", "zmm23",
3349 "zmm24", "zmm25", "zmm26", "zmm27",
3350 "zmm28", "zmm29", "zmm30", "zmm31"
3352 static const char *att_names_zmm
[] = {
3353 "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3354 "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3355 "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3356 "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3357 "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3358 "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3359 "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3360 "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3363 static const char **names_mask
;
3364 static const char *intel_names_mask
[] = {
3365 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3367 static const char *att_names_mask
[] = {
3368 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3371 static const char *names_rounding
[] =
3379 static const struct dis386 reg_table
[][8] = {
3382 { "addA", { Ebh1
, Ib
}, 0 },
3383 { "orA", { Ebh1
, Ib
}, 0 },
3384 { "adcA", { Ebh1
, Ib
}, 0 },
3385 { "sbbA", { Ebh1
, Ib
}, 0 },
3386 { "andA", { Ebh1
, Ib
}, 0 },
3387 { "subA", { Ebh1
, Ib
}, 0 },
3388 { "xorA", { Ebh1
, Ib
}, 0 },
3389 { "cmpA", { Eb
, Ib
}, 0 },
3393 { "addQ", { Evh1
, Iv
}, 0 },
3394 { "orQ", { Evh1
, Iv
}, 0 },
3395 { "adcQ", { Evh1
, Iv
}, 0 },
3396 { "sbbQ", { Evh1
, Iv
}, 0 },
3397 { "andQ", { Evh1
, Iv
}, 0 },
3398 { "subQ", { Evh1
, Iv
}, 0 },
3399 { "xorQ", { Evh1
, Iv
}, 0 },
3400 { "cmpQ", { Ev
, Iv
}, 0 },
3404 { "addQ", { Evh1
, sIb
}, 0 },
3405 { "orQ", { Evh1
, sIb
}, 0 },
3406 { "adcQ", { Evh1
, sIb
}, 0 },
3407 { "sbbQ", { Evh1
, sIb
}, 0 },
3408 { "andQ", { Evh1
, sIb
}, 0 },
3409 { "subQ", { Evh1
, sIb
}, 0 },
3410 { "xorQ", { Evh1
, sIb
}, 0 },
3411 { "cmpQ", { Ev
, sIb
}, 0 },
3415 { "popU", { stackEv
}, 0 },
3416 { XOP_8F_TABLE (XOP_09
) },
3420 { XOP_8F_TABLE (XOP_09
) },
3424 { "rolA", { Eb
, Ib
}, 0 },
3425 { "rorA", { Eb
, Ib
}, 0 },
3426 { "rclA", { Eb
, Ib
}, 0 },
3427 { "rcrA", { Eb
, Ib
}, 0 },
3428 { "shlA", { Eb
, Ib
}, 0 },
3429 { "shrA", { Eb
, Ib
}, 0 },
3431 { "sarA", { Eb
, Ib
}, 0 },
3435 { "rolQ", { Ev
, Ib
}, 0 },
3436 { "rorQ", { Ev
, Ib
}, 0 },
3437 { "rclQ", { Ev
, Ib
}, 0 },
3438 { "rcrQ", { Ev
, Ib
}, 0 },
3439 { "shlQ", { Ev
, Ib
}, 0 },
3440 { "shrQ", { Ev
, Ib
}, 0 },
3442 { "sarQ", { Ev
, Ib
}, 0 },
3446 { "movA", { Ebh3
, Ib
}, 0 },
3453 { MOD_TABLE (MOD_C6_REG_7
) },
3457 { "movQ", { Evh3
, Iv
}, 0 },
3464 { MOD_TABLE (MOD_C7_REG_7
) },
3468 { "rolA", { Eb
, I1
}, 0 },
3469 { "rorA", { Eb
, I1
}, 0 },
3470 { "rclA", { Eb
, I1
}, 0 },
3471 { "rcrA", { Eb
, I1
}, 0 },
3472 { "shlA", { Eb
, I1
}, 0 },
3473 { "shrA", { Eb
, I1
}, 0 },
3475 { "sarA", { Eb
, I1
}, 0 },
3479 { "rolQ", { Ev
, I1
}, 0 },
3480 { "rorQ", { Ev
, I1
}, 0 },
3481 { "rclQ", { Ev
, I1
}, 0 },
3482 { "rcrQ", { Ev
, I1
}, 0 },
3483 { "shlQ", { Ev
, I1
}, 0 },
3484 { "shrQ", { Ev
, I1
}, 0 },
3486 { "sarQ", { Ev
, I1
}, 0 },
3490 { "rolA", { Eb
, CL
}, 0 },
3491 { "rorA", { Eb
, CL
}, 0 },
3492 { "rclA", { Eb
, CL
}, 0 },
3493 { "rcrA", { Eb
, CL
}, 0 },
3494 { "shlA", { Eb
, CL
}, 0 },
3495 { "shrA", { Eb
, CL
}, 0 },
3497 { "sarA", { Eb
, CL
}, 0 },
3501 { "rolQ", { Ev
, CL
}, 0 },
3502 { "rorQ", { Ev
, CL
}, 0 },
3503 { "rclQ", { Ev
, CL
}, 0 },
3504 { "rcrQ", { Ev
, CL
}, 0 },
3505 { "shlQ", { Ev
, CL
}, 0 },
3506 { "shrQ", { Ev
, CL
}, 0 },
3508 { "sarQ", { Ev
, CL
}, 0 },
3512 { "testA", { Eb
, Ib
}, 0 },
3513 { "testA", { Eb
, Ib
}, 0 },
3514 { "notA", { Ebh1
}, 0 },
3515 { "negA", { Ebh1
}, 0 },
3516 { "mulA", { Eb
}, 0 }, /* Don't print the implicit %al register, */
3517 { "imulA", { Eb
}, 0 }, /* to distinguish these opcodes from other */
3518 { "divA", { Eb
}, 0 }, /* mul/imul opcodes. Do the same for div */
3519 { "idivA", { Eb
}, 0 }, /* and idiv for consistency. */
3523 { "testQ", { Ev
, Iv
}, 0 },
3524 { "testQ", { Ev
, Iv
}, 0 },
3525 { "notQ", { Evh1
}, 0 },
3526 { "negQ", { Evh1
}, 0 },
3527 { "mulQ", { Ev
}, 0 }, /* Don't print the implicit register. */
3528 { "imulQ", { Ev
}, 0 },
3529 { "divQ", { Ev
}, 0 },
3530 { "idivQ", { Ev
}, 0 },
3534 { "incA", { Ebh1
}, 0 },
3535 { "decA", { Ebh1
}, 0 },
3539 { "incQ", { Evh1
}, 0 },
3540 { "decQ", { Evh1
}, 0 },
3541 { "call{&|}", { indirEv
, BND
}, 0 },
3542 { MOD_TABLE (MOD_FF_REG_3
) },
3543 { "jmp{&|}", { indirEv
, BND
}, 0 },
3544 { MOD_TABLE (MOD_FF_REG_5
) },
3545 { "pushU", { stackEv
}, 0 },
3550 { "sldtD", { Sv
}, 0 },
3551 { "strD", { Sv
}, 0 },
3552 { "lldt", { Ew
}, 0 },
3553 { "ltr", { Ew
}, 0 },
3554 { "verr", { Ew
}, 0 },
3555 { "verw", { Ew
}, 0 },
3561 { MOD_TABLE (MOD_0F01_REG_0
) },
3562 { MOD_TABLE (MOD_0F01_REG_1
) },
3563 { MOD_TABLE (MOD_0F01_REG_2
) },
3564 { MOD_TABLE (MOD_0F01_REG_3
) },
3565 { "smswD", { Sv
}, 0 },
3566 { MOD_TABLE (MOD_0F01_REG_5
) },
3567 { "lmsw", { Ew
}, 0 },
3568 { MOD_TABLE (MOD_0F01_REG_7
) },
3572 { "prefetch", { Mb
}, 0 },
3573 { "prefetchw", { Mb
}, 0 },
3574 { "prefetchwt1", { Mb
}, 0 },
3575 { "prefetch", { Mb
}, 0 },
3576 { "prefetch", { Mb
}, 0 },
3577 { "prefetch", { Mb
}, 0 },
3578 { "prefetch", { Mb
}, 0 },
3579 { "prefetch", { Mb
}, 0 },
3583 { MOD_TABLE (MOD_0F18_REG_0
) },
3584 { MOD_TABLE (MOD_0F18_REG_1
) },
3585 { MOD_TABLE (MOD_0F18_REG_2
) },
3586 { MOD_TABLE (MOD_0F18_REG_3
) },
3587 { MOD_TABLE (MOD_0F18_REG_4
) },
3588 { MOD_TABLE (MOD_0F18_REG_5
) },
3589 { MOD_TABLE (MOD_0F18_REG_6
) },
3590 { MOD_TABLE (MOD_0F18_REG_7
) },
3596 { MOD_TABLE (MOD_0F71_REG_2
) },
3598 { MOD_TABLE (MOD_0F71_REG_4
) },
3600 { MOD_TABLE (MOD_0F71_REG_6
) },
3606 { MOD_TABLE (MOD_0F72_REG_2
) },
3608 { MOD_TABLE (MOD_0F72_REG_4
) },
3610 { MOD_TABLE (MOD_0F72_REG_6
) },
3616 { MOD_TABLE (MOD_0F73_REG_2
) },
3617 { MOD_TABLE (MOD_0F73_REG_3
) },
3620 { MOD_TABLE (MOD_0F73_REG_6
) },
3621 { MOD_TABLE (MOD_0F73_REG_7
) },
3625 { "montmul", { { OP_0f07
, 0 } }, 0 },
3626 { "xsha1", { { OP_0f07
, 0 } }, 0 },
3627 { "xsha256", { { OP_0f07
, 0 } }, 0 },
3631 { "xstore-rng", { { OP_0f07
, 0 } }, 0 },
3632 { "xcrypt-ecb", { { OP_0f07
, 0 } }, 0 },
3633 { "xcrypt-cbc", { { OP_0f07
, 0 } }, 0 },
3634 { "xcrypt-ctr", { { OP_0f07
, 0 } }, 0 },
3635 { "xcrypt-cfb", { { OP_0f07
, 0 } }, 0 },
3636 { "xcrypt-ofb", { { OP_0f07
, 0 } }, 0 },
3640 { MOD_TABLE (MOD_0FAE_REG_0
) },
3641 { MOD_TABLE (MOD_0FAE_REG_1
) },
3642 { MOD_TABLE (MOD_0FAE_REG_2
) },
3643 { MOD_TABLE (MOD_0FAE_REG_3
) },
3644 { MOD_TABLE (MOD_0FAE_REG_4
) },
3645 { MOD_TABLE (MOD_0FAE_REG_5
) },
3646 { MOD_TABLE (MOD_0FAE_REG_6
) },
3647 { MOD_TABLE (MOD_0FAE_REG_7
) },
3655 { "btQ", { Ev
, Ib
}, 0 },
3656 { "btsQ", { Evh1
, Ib
}, 0 },
3657 { "btrQ", { Evh1
, Ib
}, 0 },
3658 { "btcQ", { Evh1
, Ib
}, 0 },
3663 { "cmpxchg8b", { { CMPXCHG8B_Fixup
, q_mode
} }, 0 },
3665 { MOD_TABLE (MOD_0FC7_REG_3
) },
3666 { MOD_TABLE (MOD_0FC7_REG_4
) },
3667 { MOD_TABLE (MOD_0FC7_REG_5
) },
3668 { MOD_TABLE (MOD_0FC7_REG_6
) },
3669 { MOD_TABLE (MOD_0FC7_REG_7
) },
3675 { MOD_TABLE (MOD_VEX_0F71_REG_2
) },
3677 { MOD_TABLE (MOD_VEX_0F71_REG_4
) },
3679 { MOD_TABLE (MOD_VEX_0F71_REG_6
) },
3685 { MOD_TABLE (MOD_VEX_0F72_REG_2
) },
3687 { MOD_TABLE (MOD_VEX_0F72_REG_4
) },
3689 { MOD_TABLE (MOD_VEX_0F72_REG_6
) },
3695 { MOD_TABLE (MOD_VEX_0F73_REG_2
) },
3696 { MOD_TABLE (MOD_VEX_0F73_REG_3
) },
3699 { MOD_TABLE (MOD_VEX_0F73_REG_6
) },
3700 { MOD_TABLE (MOD_VEX_0F73_REG_7
) },
3706 { MOD_TABLE (MOD_VEX_0FAE_REG_2
) },
3707 { MOD_TABLE (MOD_VEX_0FAE_REG_3
) },
3709 /* REG_VEX_0F38F3 */
3712 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1
) },
3713 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2
) },
3714 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3
) },
3718 { "llwpcb", { { OP_LWPCB_E
, 0 } }, 0 },
3719 { "slwpcb", { { OP_LWPCB_E
, 0 } }, 0 },
3723 { "lwpins", { { OP_LWP_E
, 0 }, Ed
, Iq
}, 0 },
3724 { "lwpval", { { OP_LWP_E
, 0 }, Ed
, Iq
}, 0 },
3726 /* REG_XOP_TBM_01 */
3729 { "blcfill", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3730 { "blsfill", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3731 { "blcs", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3732 { "tzmsk", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3733 { "blcic", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3734 { "blsic", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3735 { "t1mskc", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3737 /* REG_XOP_TBM_02 */
3740 { "blcmsk", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3745 { "blci", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3747 #define NEED_REG_TABLE
3748 #include "i386-dis-evex.h"
3749 #undef NEED_REG_TABLE
3752 static const struct dis386 prefix_table
[][4] = {
3755 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} }, 0 },
3756 { "pause", { XX
}, 0 },
3757 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} }, 0 },
3758 { NULL
, { { NULL
, 0 } }, PREFIX_IGNORED
}
3763 { "movups", { XM
, EXx
}, PREFIX_OPCODE
},
3764 { "movss", { XM
, EXd
}, PREFIX_OPCODE
},
3765 { "movupd", { XM
, EXx
}, PREFIX_OPCODE
},
3766 { "movsd", { XM
, EXq
}, PREFIX_OPCODE
},
3771 { "movups", { EXxS
, XM
}, PREFIX_OPCODE
},
3772 { "movss", { EXdS
, XM
}, PREFIX_OPCODE
},
3773 { "movupd", { EXxS
, XM
}, PREFIX_OPCODE
},
3774 { "movsd", { EXqS
, XM
}, PREFIX_OPCODE
},
3779 { MOD_TABLE (MOD_0F12_PREFIX_0
) },
3780 { "movsldup", { XM
, EXx
}, PREFIX_OPCODE
},
3781 { "movlpd", { XM
, EXq
}, PREFIX_OPCODE
},
3782 { "movddup", { XM
, EXq
}, PREFIX_OPCODE
},
3787 { MOD_TABLE (MOD_0F16_PREFIX_0
) },
3788 { "movshdup", { XM
, EXx
}, PREFIX_OPCODE
},
3789 { "movhpd", { XM
, EXq
}, PREFIX_OPCODE
},
3794 { MOD_TABLE (MOD_0F1A_PREFIX_0
) },
3795 { "bndcl", { Gbnd
, Ev_bnd
}, 0 },
3796 { "bndmov", { Gbnd
, Ebnd
}, 0 },
3797 { "bndcu", { Gbnd
, Ev_bnd
}, 0 },
3802 { MOD_TABLE (MOD_0F1B_PREFIX_0
) },
3803 { MOD_TABLE (MOD_0F1B_PREFIX_1
) },
3804 { "bndmov", { Ebnd
, Gbnd
}, 0 },
3805 { "bndcn", { Gbnd
, Ev_bnd
}, 0 },
3810 { "cvtpi2ps", { XM
, EMCq
}, PREFIX_OPCODE
},
3811 { "cvtsi2ss%LQ", { XM
, Ev
}, PREFIX_OPCODE
},
3812 { "cvtpi2pd", { XM
, EMCq
}, PREFIX_OPCODE
},
3813 { "cvtsi2sd%LQ", { XM
, Ev
}, 0 },
3818 { MOD_TABLE (MOD_0F2B_PREFIX_0
) },
3819 { MOD_TABLE (MOD_0F2B_PREFIX_1
) },
3820 { MOD_TABLE (MOD_0F2B_PREFIX_2
) },
3821 { MOD_TABLE (MOD_0F2B_PREFIX_3
) },
3826 { "cvttps2pi", { MXC
, EXq
}, PREFIX_OPCODE
},
3827 { "cvttss2siY", { Gv
, EXd
}, PREFIX_OPCODE
},
3828 { "cvttpd2pi", { MXC
, EXx
}, PREFIX_OPCODE
},
3829 { "cvttsd2siY", { Gv
, EXq
}, PREFIX_OPCODE
},
3834 { "cvtps2pi", { MXC
, EXq
}, PREFIX_OPCODE
},
3835 { "cvtss2siY", { Gv
, EXd
}, PREFIX_OPCODE
},
3836 { "cvtpd2pi", { MXC
, EXx
}, PREFIX_OPCODE
},
3837 { "cvtsd2siY", { Gv
, EXq
}, PREFIX_OPCODE
},
3842 { "ucomiss",{ XM
, EXd
}, 0 },
3844 { "ucomisd",{ XM
, EXq
}, 0 },
3849 { "comiss", { XM
, EXd
}, 0 },
3851 { "comisd", { XM
, EXq
}, 0 },
3856 { "sqrtps", { XM
, EXx
}, PREFIX_OPCODE
},
3857 { "sqrtss", { XM
, EXd
}, PREFIX_OPCODE
},
3858 { "sqrtpd", { XM
, EXx
}, PREFIX_OPCODE
},
3859 { "sqrtsd", { XM
, EXq
}, PREFIX_OPCODE
},
3864 { "rsqrtps",{ XM
, EXx
}, PREFIX_OPCODE
},
3865 { "rsqrtss",{ XM
, EXd
}, PREFIX_OPCODE
},
3870 { "rcpps", { XM
, EXx
}, PREFIX_OPCODE
},
3871 { "rcpss", { XM
, EXd
}, PREFIX_OPCODE
},
3876 { "addps", { XM
, EXx
}, PREFIX_OPCODE
},
3877 { "addss", { XM
, EXd
}, PREFIX_OPCODE
},
3878 { "addpd", { XM
, EXx
}, PREFIX_OPCODE
},
3879 { "addsd", { XM
, EXq
}, PREFIX_OPCODE
},
3884 { "mulps", { XM
, EXx
}, PREFIX_OPCODE
},
3885 { "mulss", { XM
, EXd
}, PREFIX_OPCODE
},
3886 { "mulpd", { XM
, EXx
}, PREFIX_OPCODE
},
3887 { "mulsd", { XM
, EXq
}, PREFIX_OPCODE
},
3892 { "cvtps2pd", { XM
, EXq
}, PREFIX_OPCODE
},
3893 { "cvtss2sd", { XM
, EXd
}, PREFIX_OPCODE
},
3894 { "cvtpd2ps", { XM
, EXx
}, PREFIX_OPCODE
},
3895 { "cvtsd2ss", { XM
, EXq
}, PREFIX_OPCODE
},
3900 { "cvtdq2ps", { XM
, EXx
}, PREFIX_OPCODE
},
3901 { "cvttps2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3902 { "cvtps2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3907 { "subps", { XM
, EXx
}, PREFIX_OPCODE
},
3908 { "subss", { XM
, EXd
}, PREFIX_OPCODE
},
3909 { "subpd", { XM
, EXx
}, PREFIX_OPCODE
},
3910 { "subsd", { XM
, EXq
}, PREFIX_OPCODE
},
3915 { "minps", { XM
, EXx
}, PREFIX_OPCODE
},
3916 { "minss", { XM
, EXd
}, PREFIX_OPCODE
},
3917 { "minpd", { XM
, EXx
}, PREFIX_OPCODE
},
3918 { "minsd", { XM
, EXq
}, PREFIX_OPCODE
},
3923 { "divps", { XM
, EXx
}, PREFIX_OPCODE
},
3924 { "divss", { XM
, EXd
}, PREFIX_OPCODE
},
3925 { "divpd", { XM
, EXx
}, PREFIX_OPCODE
},
3926 { "divsd", { XM
, EXq
}, PREFIX_OPCODE
},
3931 { "maxps", { XM
, EXx
}, PREFIX_OPCODE
},
3932 { "maxss", { XM
, EXd
}, PREFIX_OPCODE
},
3933 { "maxpd", { XM
, EXx
}, PREFIX_OPCODE
},
3934 { "maxsd", { XM
, EXq
}, PREFIX_OPCODE
},
3939 { "punpcklbw",{ MX
, EMd
}, PREFIX_OPCODE
},
3941 { "punpcklbw",{ MX
, EMx
}, PREFIX_OPCODE
},
3946 { "punpcklwd",{ MX
, EMd
}, PREFIX_OPCODE
},
3948 { "punpcklwd",{ MX
, EMx
}, PREFIX_OPCODE
},
3953 { "punpckldq",{ MX
, EMd
}, PREFIX_OPCODE
},
3955 { "punpckldq",{ MX
, EMx
}, PREFIX_OPCODE
},
3962 { "punpcklqdq", { XM
, EXx
}, PREFIX_OPCODE
},
3969 { "punpckhqdq", { XM
, EXx
}, PREFIX_OPCODE
},
3974 { "movq", { MX
, EM
}, PREFIX_OPCODE
},
3975 { "movdqu", { XM
, EXx
}, PREFIX_OPCODE
},
3976 { "movdqa", { XM
, EXx
}, PREFIX_OPCODE
},
3981 { "pshufw", { MX
, EM
, Ib
}, PREFIX_OPCODE
},
3982 { "pshufhw",{ XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3983 { "pshufd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3984 { "pshuflw",{ XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3987 /* PREFIX_0F73_REG_3 */
3991 { "psrldq", { XS
, Ib
}, 0 },
3994 /* PREFIX_0F73_REG_7 */
3998 { "pslldq", { XS
, Ib
}, 0 },
4003 {"vmread", { Em
, Gm
}, 0 },
4005 {"extrq", { XS
, Ib
, Ib
}, 0 },
4006 {"insertq", { XM
, XS
, Ib
, Ib
}, 0 },
4011 {"vmwrite", { Gm
, Em
}, 0 },
4013 {"extrq", { XM
, XS
}, 0 },
4014 {"insertq", { XM
, XS
}, 0 },
4021 { "haddpd", { XM
, EXx
}, PREFIX_OPCODE
},
4022 { "haddps", { XM
, EXx
}, PREFIX_OPCODE
},
4029 { "hsubpd", { XM
, EXx
}, PREFIX_OPCODE
},
4030 { "hsubps", { XM
, EXx
}, PREFIX_OPCODE
},
4035 { "movK", { Edq
, MX
}, PREFIX_OPCODE
},
4036 { "movq", { XM
, EXq
}, PREFIX_OPCODE
},
4037 { "movK", { Edq
, XM
}, PREFIX_OPCODE
},
4042 { "movq", { EMS
, MX
}, PREFIX_OPCODE
},
4043 { "movdqu", { EXxS
, XM
}, PREFIX_OPCODE
},
4044 { "movdqa", { EXxS
, XM
}, PREFIX_OPCODE
},
4047 /* PREFIX_0FAE_REG_0 */
4050 { "rdfsbase", { Ev
}, 0 },
4053 /* PREFIX_0FAE_REG_1 */
4056 { "rdgsbase", { Ev
}, 0 },
4059 /* PREFIX_0FAE_REG_2 */
4062 { "wrfsbase", { Ev
}, 0 },
4065 /* PREFIX_0FAE_REG_3 */
4068 { "wrgsbase", { Ev
}, 0 },
4071 /* PREFIX_MOD_0_0FAE_REG_4 */
4073 { "xsave", { FXSAVE
}, 0 },
4074 { "ptwrite%LQ", { Edq
}, 0 },
4077 /* PREFIX_MOD_3_0FAE_REG_4 */
4080 { "ptwrite%LQ", { Edq
}, 0 },
4083 /* PREFIX_0FAE_REG_6 */
4085 { "xsaveopt", { FXSAVE
}, 0 },
4087 { "clwb", { Mb
}, 0 },
4090 /* PREFIX_0FAE_REG_7 */
4092 { "clflush", { Mb
}, 0 },
4094 { "clflushopt", { Mb
}, 0 },
4100 { "popcntS", { Gv
, Ev
}, 0 },
4105 { "bsfS", { Gv
, Ev
}, 0 },
4106 { "tzcntS", { Gv
, Ev
}, 0 },
4107 { "bsfS", { Gv
, Ev
}, 0 },
4112 { "bsrS", { Gv
, Ev
}, 0 },
4113 { "lzcntS", { Gv
, Ev
}, 0 },
4114 { "bsrS", { Gv
, Ev
}, 0 },
4119 { "cmpps", { XM
, EXx
, CMP
}, PREFIX_OPCODE
},
4120 { "cmpss", { XM
, EXd
, CMP
}, PREFIX_OPCODE
},
4121 { "cmppd", { XM
, EXx
, CMP
}, PREFIX_OPCODE
},
4122 { "cmpsd", { XM
, EXq
, CMP
}, PREFIX_OPCODE
},
4125 /* PREFIX_MOD_0_0FC3 */
4127 { "movntiS", { Ev
, Gv
}, PREFIX_OPCODE
},
4130 /* PREFIX_MOD_0_0FC7_REG_6 */
4132 { "vmptrld",{ Mq
}, 0 },
4133 { "vmxon", { Mq
}, 0 },
4134 { "vmclear",{ Mq
}, 0 },
4137 /* PREFIX_MOD_3_0FC7_REG_6 */
4139 { "rdrand", { Ev
}, 0 },
4141 { "rdrand", { Ev
}, 0 }
4144 /* PREFIX_MOD_3_0FC7_REG_7 */
4146 { "rdseed", { Ev
}, 0 },
4147 { "rdpid", { Em
}, 0 },
4148 { "rdseed", { Ev
}, 0 },
4155 { "addsubpd", { XM
, EXx
}, 0 },
4156 { "addsubps", { XM
, EXx
}, 0 },
4162 { "movq2dq",{ XM
, MS
}, 0 },
4163 { "movq", { EXqS
, XM
}, 0 },
4164 { "movdq2q",{ MX
, XS
}, 0 },
4170 { "cvtdq2pd", { XM
, EXq
}, PREFIX_OPCODE
},
4171 { "cvttpd2dq", { XM
, EXx
}, PREFIX_OPCODE
},
4172 { "cvtpd2dq", { XM
, EXx
}, PREFIX_OPCODE
},
4177 { "movntq", { Mq
, MX
}, PREFIX_OPCODE
},
4179 { MOD_TABLE (MOD_0FE7_PREFIX_2
) },
4187 { MOD_TABLE (MOD_0FF0_PREFIX_3
) },
4192 { "maskmovq", { MX
, MS
}, PREFIX_OPCODE
},
4194 { "maskmovdqu", { XM
, XS
}, PREFIX_OPCODE
},
4201 { "pblendvb", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4208 { "blendvps", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4215 { "blendvpd", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4222 { "ptest", { XM
, EXx
}, PREFIX_OPCODE
},
4229 { "pmovsxbw", { XM
, EXq
}, PREFIX_OPCODE
},
4236 { "pmovsxbd", { XM
, EXd
}, PREFIX_OPCODE
},
4243 { "pmovsxbq", { XM
, EXw
}, PREFIX_OPCODE
},
4250 { "pmovsxwd", { XM
, EXq
}, PREFIX_OPCODE
},
4257 { "pmovsxwq", { XM
, EXd
}, PREFIX_OPCODE
},
4264 { "pmovsxdq", { XM
, EXq
}, PREFIX_OPCODE
},
4271 { "pmuldq", { XM
, EXx
}, PREFIX_OPCODE
},
4278 { "pcmpeqq", { XM
, EXx
}, PREFIX_OPCODE
},
4285 { MOD_TABLE (MOD_0F382A_PREFIX_2
) },
4292 { "packusdw", { XM
, EXx
}, PREFIX_OPCODE
},
4299 { "pmovzxbw", { XM
, EXq
}, PREFIX_OPCODE
},
4306 { "pmovzxbd", { XM
, EXd
}, PREFIX_OPCODE
},
4313 { "pmovzxbq", { XM
, EXw
}, PREFIX_OPCODE
},
4320 { "pmovzxwd", { XM
, EXq
}, PREFIX_OPCODE
},
4327 { "pmovzxwq", { XM
, EXd
}, PREFIX_OPCODE
},
4334 { "pmovzxdq", { XM
, EXq
}, PREFIX_OPCODE
},
4341 { "pcmpgtq", { XM
, EXx
}, PREFIX_OPCODE
},
4348 { "pminsb", { XM
, EXx
}, PREFIX_OPCODE
},
4355 { "pminsd", { XM
, EXx
}, PREFIX_OPCODE
},
4362 { "pminuw", { XM
, EXx
}, PREFIX_OPCODE
},
4369 { "pminud", { XM
, EXx
}, PREFIX_OPCODE
},
4376 { "pmaxsb", { XM
, EXx
}, PREFIX_OPCODE
},
4383 { "pmaxsd", { XM
, EXx
}, PREFIX_OPCODE
},
4390 { "pmaxuw", { XM
, EXx
}, PREFIX_OPCODE
},
4397 { "pmaxud", { XM
, EXx
}, PREFIX_OPCODE
},
4404 { "pmulld", { XM
, EXx
}, PREFIX_OPCODE
},
4411 { "phminposuw", { XM
, EXx
}, PREFIX_OPCODE
},
4418 { "invept", { Gm
, Mo
}, PREFIX_OPCODE
},
4425 { "invvpid", { Gm
, Mo
}, PREFIX_OPCODE
},
4432 { "invpcid", { Gm
, M
}, PREFIX_OPCODE
},
4437 { "sha1nexte", { XM
, EXxmm
}, PREFIX_OPCODE
},
4442 { "sha1msg1", { XM
, EXxmm
}, PREFIX_OPCODE
},
4447 { "sha1msg2", { XM
, EXxmm
}, PREFIX_OPCODE
},
4452 { "sha256rnds2", { XM
, EXxmm
, XMM0
}, PREFIX_OPCODE
},
4457 { "sha256msg1", { XM
, EXxmm
}, PREFIX_OPCODE
},
4462 { "sha256msg2", { XM
, EXxmm
}, PREFIX_OPCODE
},
4469 { "aesimc", { XM
, EXx
}, PREFIX_OPCODE
},
4476 { "aesenc", { XM
, EXx
}, PREFIX_OPCODE
},
4483 { "aesenclast", { XM
, EXx
}, PREFIX_OPCODE
},
4490 { "aesdec", { XM
, EXx
}, PREFIX_OPCODE
},
4497 { "aesdeclast", { XM
, EXx
}, PREFIX_OPCODE
},
4502 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4504 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4505 { "crc32", { Gdq
, { CRC32_Fixup
, b_mode
} }, PREFIX_OPCODE
},
4510 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
}, PREFIX_OPCODE
},
4512 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
}, PREFIX_OPCODE
},
4513 { "crc32", { Gdq
, { CRC32_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4519 { "adoxS", { Gdq
, Edq
}, PREFIX_OPCODE
},
4520 { "adcxS", { Gdq
, Edq
}, PREFIX_OPCODE
},
4528 { "roundps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4535 { "roundpd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4542 { "roundss", { XM
, EXd
, Ib
}, PREFIX_OPCODE
},
4549 { "roundsd", { XM
, EXq
, Ib
}, PREFIX_OPCODE
},
4556 { "blendps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4563 { "blendpd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4570 { "pblendw", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4577 { "pextrb", { Edqb
, XM
, Ib
}, PREFIX_OPCODE
},
4584 { "pextrw", { Edqw
, XM
, Ib
}, PREFIX_OPCODE
},
4591 { "pextrK", { Edq
, XM
, Ib
}, PREFIX_OPCODE
},
4598 { "extractps", { Edqd
, XM
, Ib
}, PREFIX_OPCODE
},
4605 { "pinsrb", { XM
, Edqb
, Ib
}, PREFIX_OPCODE
},
4612 { "insertps", { XM
, EXd
, Ib
}, PREFIX_OPCODE
},
4619 { "pinsrK", { XM
, Edq
, Ib
}, PREFIX_OPCODE
},
4626 { "dpps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4633 { "dppd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4640 { "mpsadbw", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4647 { "pclmulqdq", { XM
, EXx
, PCLMUL
}, PREFIX_OPCODE
},
4654 { "pcmpestrm", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, PREFIX_OPCODE
},
4661 { "pcmpestri", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, PREFIX_OPCODE
},
4668 { "pcmpistrm", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4675 { "pcmpistri", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4680 { "sha1rnds4", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4687 { "aeskeygenassist", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4690 /* PREFIX_VEX_0F10 */
4692 { VEX_W_TABLE (VEX_W_0F10_P_0
) },
4693 { VEX_LEN_TABLE (VEX_LEN_0F10_P_1
) },
4694 { VEX_W_TABLE (VEX_W_0F10_P_2
) },
4695 { VEX_LEN_TABLE (VEX_LEN_0F10_P_3
) },
4698 /* PREFIX_VEX_0F11 */
4700 { VEX_W_TABLE (VEX_W_0F11_P_0
) },
4701 { VEX_LEN_TABLE (VEX_LEN_0F11_P_1
) },
4702 { VEX_W_TABLE (VEX_W_0F11_P_2
) },
4703 { VEX_LEN_TABLE (VEX_LEN_0F11_P_3
) },
4706 /* PREFIX_VEX_0F12 */
4708 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0
) },
4709 { VEX_W_TABLE (VEX_W_0F12_P_1
) },
4710 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2
) },
4711 { VEX_W_TABLE (VEX_W_0F12_P_3
) },
4714 /* PREFIX_VEX_0F16 */
4716 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0
) },
4717 { VEX_W_TABLE (VEX_W_0F16_P_1
) },
4718 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2
) },
4721 /* PREFIX_VEX_0F2A */
4724 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1
) },
4726 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3
) },
4729 /* PREFIX_VEX_0F2C */
4732 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1
) },
4734 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3
) },
4737 /* PREFIX_VEX_0F2D */
4740 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1
) },
4742 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3
) },
4745 /* PREFIX_VEX_0F2E */
4747 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0
) },
4749 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2
) },
4752 /* PREFIX_VEX_0F2F */
4754 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0
) },
4756 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2
) },
4759 /* PREFIX_VEX_0F41 */
4761 { VEX_LEN_TABLE (VEX_LEN_0F41_P_0
) },
4763 { VEX_LEN_TABLE (VEX_LEN_0F41_P_2
) },
4766 /* PREFIX_VEX_0F42 */
4768 { VEX_LEN_TABLE (VEX_LEN_0F42_P_0
) },
4770 { VEX_LEN_TABLE (VEX_LEN_0F42_P_2
) },
4773 /* PREFIX_VEX_0F44 */
4775 { VEX_LEN_TABLE (VEX_LEN_0F44_P_0
) },
4777 { VEX_LEN_TABLE (VEX_LEN_0F44_P_2
) },
4780 /* PREFIX_VEX_0F45 */
4782 { VEX_LEN_TABLE (VEX_LEN_0F45_P_0
) },
4784 { VEX_LEN_TABLE (VEX_LEN_0F45_P_2
) },
4787 /* PREFIX_VEX_0F46 */
4789 { VEX_LEN_TABLE (VEX_LEN_0F46_P_0
) },
4791 { VEX_LEN_TABLE (VEX_LEN_0F46_P_2
) },
4794 /* PREFIX_VEX_0F47 */
4796 { VEX_LEN_TABLE (VEX_LEN_0F47_P_0
) },
4798 { VEX_LEN_TABLE (VEX_LEN_0F47_P_2
) },
4801 /* PREFIX_VEX_0F4A */
4803 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0
) },
4805 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2
) },
4808 /* PREFIX_VEX_0F4B */
4810 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0
) },
4812 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2
) },
4815 /* PREFIX_VEX_0F51 */
4817 { VEX_W_TABLE (VEX_W_0F51_P_0
) },
4818 { VEX_LEN_TABLE (VEX_LEN_0F51_P_1
) },
4819 { VEX_W_TABLE (VEX_W_0F51_P_2
) },
4820 { VEX_LEN_TABLE (VEX_LEN_0F51_P_3
) },
4823 /* PREFIX_VEX_0F52 */
4825 { VEX_W_TABLE (VEX_W_0F52_P_0
) },
4826 { VEX_LEN_TABLE (VEX_LEN_0F52_P_1
) },
4829 /* PREFIX_VEX_0F53 */
4831 { VEX_W_TABLE (VEX_W_0F53_P_0
) },
4832 { VEX_LEN_TABLE (VEX_LEN_0F53_P_1
) },
4835 /* PREFIX_VEX_0F58 */
4837 { VEX_W_TABLE (VEX_W_0F58_P_0
) },
4838 { VEX_LEN_TABLE (VEX_LEN_0F58_P_1
) },
4839 { VEX_W_TABLE (VEX_W_0F58_P_2
) },
4840 { VEX_LEN_TABLE (VEX_LEN_0F58_P_3
) },
4843 /* PREFIX_VEX_0F59 */
4845 { VEX_W_TABLE (VEX_W_0F59_P_0
) },
4846 { VEX_LEN_TABLE (VEX_LEN_0F59_P_1
) },
4847 { VEX_W_TABLE (VEX_W_0F59_P_2
) },
4848 { VEX_LEN_TABLE (VEX_LEN_0F59_P_3
) },
4851 /* PREFIX_VEX_0F5A */
4853 { VEX_W_TABLE (VEX_W_0F5A_P_0
) },
4854 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1
) },
4855 { "vcvtpd2ps%XY", { XMM
, EXx
}, 0 },
4856 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3
) },
4859 /* PREFIX_VEX_0F5B */
4861 { VEX_W_TABLE (VEX_W_0F5B_P_0
) },
4862 { VEX_W_TABLE (VEX_W_0F5B_P_1
) },
4863 { VEX_W_TABLE (VEX_W_0F5B_P_2
) },
4866 /* PREFIX_VEX_0F5C */
4868 { VEX_W_TABLE (VEX_W_0F5C_P_0
) },
4869 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1
) },
4870 { VEX_W_TABLE (VEX_W_0F5C_P_2
) },
4871 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3
) },
4874 /* PREFIX_VEX_0F5D */
4876 { VEX_W_TABLE (VEX_W_0F5D_P_0
) },
4877 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1
) },
4878 { VEX_W_TABLE (VEX_W_0F5D_P_2
) },
4879 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3
) },
4882 /* PREFIX_VEX_0F5E */
4884 { VEX_W_TABLE (VEX_W_0F5E_P_0
) },
4885 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1
) },
4886 { VEX_W_TABLE (VEX_W_0F5E_P_2
) },
4887 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3
) },
4890 /* PREFIX_VEX_0F5F */
4892 { VEX_W_TABLE (VEX_W_0F5F_P_0
) },
4893 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1
) },
4894 { VEX_W_TABLE (VEX_W_0F5F_P_2
) },
4895 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3
) },
4898 /* PREFIX_VEX_0F60 */
4902 { VEX_W_TABLE (VEX_W_0F60_P_2
) },
4905 /* PREFIX_VEX_0F61 */
4909 { VEX_W_TABLE (VEX_W_0F61_P_2
) },
4912 /* PREFIX_VEX_0F62 */
4916 { VEX_W_TABLE (VEX_W_0F62_P_2
) },
4919 /* PREFIX_VEX_0F63 */
4923 { VEX_W_TABLE (VEX_W_0F63_P_2
) },
4926 /* PREFIX_VEX_0F64 */
4930 { VEX_W_TABLE (VEX_W_0F64_P_2
) },
4933 /* PREFIX_VEX_0F65 */
4937 { VEX_W_TABLE (VEX_W_0F65_P_2
) },
4940 /* PREFIX_VEX_0F66 */
4944 { VEX_W_TABLE (VEX_W_0F66_P_2
) },
4947 /* PREFIX_VEX_0F67 */
4951 { VEX_W_TABLE (VEX_W_0F67_P_2
) },
4954 /* PREFIX_VEX_0F68 */
4958 { VEX_W_TABLE (VEX_W_0F68_P_2
) },
4961 /* PREFIX_VEX_0F69 */
4965 { VEX_W_TABLE (VEX_W_0F69_P_2
) },
4968 /* PREFIX_VEX_0F6A */
4972 { VEX_W_TABLE (VEX_W_0F6A_P_2
) },
4975 /* PREFIX_VEX_0F6B */
4979 { VEX_W_TABLE (VEX_W_0F6B_P_2
) },
4982 /* PREFIX_VEX_0F6C */
4986 { VEX_W_TABLE (VEX_W_0F6C_P_2
) },
4989 /* PREFIX_VEX_0F6D */
4993 { VEX_W_TABLE (VEX_W_0F6D_P_2
) },
4996 /* PREFIX_VEX_0F6E */
5000 { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2
) },
5003 /* PREFIX_VEX_0F6F */
5006 { VEX_W_TABLE (VEX_W_0F6F_P_1
) },
5007 { VEX_W_TABLE (VEX_W_0F6F_P_2
) },
5010 /* PREFIX_VEX_0F70 */
5013 { VEX_W_TABLE (VEX_W_0F70_P_1
) },
5014 { VEX_W_TABLE (VEX_W_0F70_P_2
) },
5015 { VEX_W_TABLE (VEX_W_0F70_P_3
) },
5018 /* PREFIX_VEX_0F71_REG_2 */
5022 { VEX_W_TABLE (VEX_W_0F71_R_2_P_2
) },
5025 /* PREFIX_VEX_0F71_REG_4 */
5029 { VEX_W_TABLE (VEX_W_0F71_R_4_P_2
) },
5032 /* PREFIX_VEX_0F71_REG_6 */
5036 { VEX_W_TABLE (VEX_W_0F71_R_6_P_2
) },
5039 /* PREFIX_VEX_0F72_REG_2 */
5043 { VEX_W_TABLE (VEX_W_0F72_R_2_P_2
) },
5046 /* PREFIX_VEX_0F72_REG_4 */
5050 { VEX_W_TABLE (VEX_W_0F72_R_4_P_2
) },
5053 /* PREFIX_VEX_0F72_REG_6 */
5057 { VEX_W_TABLE (VEX_W_0F72_R_6_P_2
) },
5060 /* PREFIX_VEX_0F73_REG_2 */
5064 { VEX_W_TABLE (VEX_W_0F73_R_2_P_2
) },
5067 /* PREFIX_VEX_0F73_REG_3 */
5071 { VEX_W_TABLE (VEX_W_0F73_R_3_P_2
) },
5074 /* PREFIX_VEX_0F73_REG_6 */
5078 { VEX_W_TABLE (VEX_W_0F73_R_6_P_2
) },
5081 /* PREFIX_VEX_0F73_REG_7 */
5085 { VEX_W_TABLE (VEX_W_0F73_R_7_P_2
) },
5088 /* PREFIX_VEX_0F74 */
5092 { VEX_W_TABLE (VEX_W_0F74_P_2
) },
5095 /* PREFIX_VEX_0F75 */
5099 { VEX_W_TABLE (VEX_W_0F75_P_2
) },
5102 /* PREFIX_VEX_0F76 */
5106 { VEX_W_TABLE (VEX_W_0F76_P_2
) },
5109 /* PREFIX_VEX_0F77 */
5111 { VEX_W_TABLE (VEX_W_0F77_P_0
) },
5114 /* PREFIX_VEX_0F7C */
5118 { VEX_W_TABLE (VEX_W_0F7C_P_2
) },
5119 { VEX_W_TABLE (VEX_W_0F7C_P_3
) },
5122 /* PREFIX_VEX_0F7D */
5126 { VEX_W_TABLE (VEX_W_0F7D_P_2
) },
5127 { VEX_W_TABLE (VEX_W_0F7D_P_3
) },
5130 /* PREFIX_VEX_0F7E */
5133 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1
) },
5134 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2
) },
5137 /* PREFIX_VEX_0F7F */
5140 { VEX_W_TABLE (VEX_W_0F7F_P_1
) },
5141 { VEX_W_TABLE (VEX_W_0F7F_P_2
) },
5144 /* PREFIX_VEX_0F90 */
5146 { VEX_LEN_TABLE (VEX_LEN_0F90_P_0
) },
5148 { VEX_LEN_TABLE (VEX_LEN_0F90_P_2
) },
5151 /* PREFIX_VEX_0F91 */
5153 { VEX_LEN_TABLE (VEX_LEN_0F91_P_0
) },
5155 { VEX_LEN_TABLE (VEX_LEN_0F91_P_2
) },
5158 /* PREFIX_VEX_0F92 */
5160 { VEX_LEN_TABLE (VEX_LEN_0F92_P_0
) },
5162 { VEX_LEN_TABLE (VEX_LEN_0F92_P_2
) },
5163 { VEX_LEN_TABLE (VEX_LEN_0F92_P_3
) },
5166 /* PREFIX_VEX_0F93 */
5168 { VEX_LEN_TABLE (VEX_LEN_0F93_P_0
) },
5170 { VEX_LEN_TABLE (VEX_LEN_0F93_P_2
) },
5171 { VEX_LEN_TABLE (VEX_LEN_0F93_P_3
) },
5174 /* PREFIX_VEX_0F98 */
5176 { VEX_LEN_TABLE (VEX_LEN_0F98_P_0
) },
5178 { VEX_LEN_TABLE (VEX_LEN_0F98_P_2
) },
5181 /* PREFIX_VEX_0F99 */
5183 { VEX_LEN_TABLE (VEX_LEN_0F99_P_0
) },
5185 { VEX_LEN_TABLE (VEX_LEN_0F99_P_2
) },
5188 /* PREFIX_VEX_0FC2 */
5190 { VEX_W_TABLE (VEX_W_0FC2_P_0
) },
5191 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1
) },
5192 { VEX_W_TABLE (VEX_W_0FC2_P_2
) },
5193 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3
) },
5196 /* PREFIX_VEX_0FC4 */
5200 { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2
) },
5203 /* PREFIX_VEX_0FC5 */
5207 { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2
) },
5210 /* PREFIX_VEX_0FD0 */
5214 { VEX_W_TABLE (VEX_W_0FD0_P_2
) },
5215 { VEX_W_TABLE (VEX_W_0FD0_P_3
) },
5218 /* PREFIX_VEX_0FD1 */
5222 { VEX_W_TABLE (VEX_W_0FD1_P_2
) },
5225 /* PREFIX_VEX_0FD2 */
5229 { VEX_W_TABLE (VEX_W_0FD2_P_2
) },
5232 /* PREFIX_VEX_0FD3 */
5236 { VEX_W_TABLE (VEX_W_0FD3_P_2
) },
5239 /* PREFIX_VEX_0FD4 */
5243 { VEX_W_TABLE (VEX_W_0FD4_P_2
) },
5246 /* PREFIX_VEX_0FD5 */
5250 { VEX_W_TABLE (VEX_W_0FD5_P_2
) },
5253 /* PREFIX_VEX_0FD6 */
5257 { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2
) },
5260 /* PREFIX_VEX_0FD7 */
5264 { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2
) },
5267 /* PREFIX_VEX_0FD8 */
5271 { VEX_W_TABLE (VEX_W_0FD8_P_2
) },
5274 /* PREFIX_VEX_0FD9 */
5278 { VEX_W_TABLE (VEX_W_0FD9_P_2
) },
5281 /* PREFIX_VEX_0FDA */
5285 { VEX_W_TABLE (VEX_W_0FDA_P_2
) },
5288 /* PREFIX_VEX_0FDB */
5292 { VEX_W_TABLE (VEX_W_0FDB_P_2
) },
5295 /* PREFIX_VEX_0FDC */
5299 { VEX_W_TABLE (VEX_W_0FDC_P_2
) },
5302 /* PREFIX_VEX_0FDD */
5306 { VEX_W_TABLE (VEX_W_0FDD_P_2
) },
5309 /* PREFIX_VEX_0FDE */
5313 { VEX_W_TABLE (VEX_W_0FDE_P_2
) },
5316 /* PREFIX_VEX_0FDF */
5320 { VEX_W_TABLE (VEX_W_0FDF_P_2
) },
5323 /* PREFIX_VEX_0FE0 */
5327 { VEX_W_TABLE (VEX_W_0FE0_P_2
) },
5330 /* PREFIX_VEX_0FE1 */
5334 { VEX_W_TABLE (VEX_W_0FE1_P_2
) },
5337 /* PREFIX_VEX_0FE2 */
5341 { VEX_W_TABLE (VEX_W_0FE2_P_2
) },
5344 /* PREFIX_VEX_0FE3 */
5348 { VEX_W_TABLE (VEX_W_0FE3_P_2
) },
5351 /* PREFIX_VEX_0FE4 */
5355 { VEX_W_TABLE (VEX_W_0FE4_P_2
) },
5358 /* PREFIX_VEX_0FE5 */
5362 { VEX_W_TABLE (VEX_W_0FE5_P_2
) },
5365 /* PREFIX_VEX_0FE6 */
5368 { VEX_W_TABLE (VEX_W_0FE6_P_1
) },
5369 { VEX_W_TABLE (VEX_W_0FE6_P_2
) },
5370 { VEX_W_TABLE (VEX_W_0FE6_P_3
) },
5373 /* PREFIX_VEX_0FE7 */
5377 { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2
) },
5380 /* PREFIX_VEX_0FE8 */
5384 { VEX_W_TABLE (VEX_W_0FE8_P_2
) },
5387 /* PREFIX_VEX_0FE9 */
5391 { VEX_W_TABLE (VEX_W_0FE9_P_2
) },
5394 /* PREFIX_VEX_0FEA */
5398 { VEX_W_TABLE (VEX_W_0FEA_P_2
) },
5401 /* PREFIX_VEX_0FEB */
5405 { VEX_W_TABLE (VEX_W_0FEB_P_2
) },
5408 /* PREFIX_VEX_0FEC */
5412 { VEX_W_TABLE (VEX_W_0FEC_P_2
) },
5415 /* PREFIX_VEX_0FED */
5419 { VEX_W_TABLE (VEX_W_0FED_P_2
) },
5422 /* PREFIX_VEX_0FEE */
5426 { VEX_W_TABLE (VEX_W_0FEE_P_2
) },
5429 /* PREFIX_VEX_0FEF */
5433 { VEX_W_TABLE (VEX_W_0FEF_P_2
) },
5436 /* PREFIX_VEX_0FF0 */
5441 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3
) },
5444 /* PREFIX_VEX_0FF1 */
5448 { VEX_W_TABLE (VEX_W_0FF1_P_2
) },
5451 /* PREFIX_VEX_0FF2 */
5455 { VEX_W_TABLE (VEX_W_0FF2_P_2
) },
5458 /* PREFIX_VEX_0FF3 */
5462 { VEX_W_TABLE (VEX_W_0FF3_P_2
) },
5465 /* PREFIX_VEX_0FF4 */
5469 { VEX_W_TABLE (VEX_W_0FF4_P_2
) },
5472 /* PREFIX_VEX_0FF5 */
5476 { VEX_W_TABLE (VEX_W_0FF5_P_2
) },
5479 /* PREFIX_VEX_0FF6 */
5483 { VEX_W_TABLE (VEX_W_0FF6_P_2
) },
5486 /* PREFIX_VEX_0FF7 */
5490 { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2
) },
5493 /* PREFIX_VEX_0FF8 */
5497 { VEX_W_TABLE (VEX_W_0FF8_P_2
) },
5500 /* PREFIX_VEX_0FF9 */
5504 { VEX_W_TABLE (VEX_W_0FF9_P_2
) },
5507 /* PREFIX_VEX_0FFA */
5511 { VEX_W_TABLE (VEX_W_0FFA_P_2
) },
5514 /* PREFIX_VEX_0FFB */
5518 { VEX_W_TABLE (VEX_W_0FFB_P_2
) },
5521 /* PREFIX_VEX_0FFC */
5525 { VEX_W_TABLE (VEX_W_0FFC_P_2
) },
5528 /* PREFIX_VEX_0FFD */
5532 { VEX_W_TABLE (VEX_W_0FFD_P_2
) },
5535 /* PREFIX_VEX_0FFE */
5539 { VEX_W_TABLE (VEX_W_0FFE_P_2
) },
5542 /* PREFIX_VEX_0F3800 */
5546 { VEX_W_TABLE (VEX_W_0F3800_P_2
) },
5549 /* PREFIX_VEX_0F3801 */
5553 { VEX_W_TABLE (VEX_W_0F3801_P_2
) },
5556 /* PREFIX_VEX_0F3802 */
5560 { VEX_W_TABLE (VEX_W_0F3802_P_2
) },
5563 /* PREFIX_VEX_0F3803 */
5567 { VEX_W_TABLE (VEX_W_0F3803_P_2
) },
5570 /* PREFIX_VEX_0F3804 */
5574 { VEX_W_TABLE (VEX_W_0F3804_P_2
) },
5577 /* PREFIX_VEX_0F3805 */
5581 { VEX_W_TABLE (VEX_W_0F3805_P_2
) },
5584 /* PREFIX_VEX_0F3806 */
5588 { VEX_W_TABLE (VEX_W_0F3806_P_2
) },
5591 /* PREFIX_VEX_0F3807 */
5595 { VEX_W_TABLE (VEX_W_0F3807_P_2
) },
5598 /* PREFIX_VEX_0F3808 */
5602 { VEX_W_TABLE (VEX_W_0F3808_P_2
) },
5605 /* PREFIX_VEX_0F3809 */
5609 { VEX_W_TABLE (VEX_W_0F3809_P_2
) },
5612 /* PREFIX_VEX_0F380A */
5616 { VEX_W_TABLE (VEX_W_0F380A_P_2
) },
5619 /* PREFIX_VEX_0F380B */
5623 { VEX_W_TABLE (VEX_W_0F380B_P_2
) },
5626 /* PREFIX_VEX_0F380C */
5630 { VEX_W_TABLE (VEX_W_0F380C_P_2
) },
5633 /* PREFIX_VEX_0F380D */
5637 { VEX_W_TABLE (VEX_W_0F380D_P_2
) },
5640 /* PREFIX_VEX_0F380E */
5644 { VEX_W_TABLE (VEX_W_0F380E_P_2
) },
5647 /* PREFIX_VEX_0F380F */
5651 { VEX_W_TABLE (VEX_W_0F380F_P_2
) },
5654 /* PREFIX_VEX_0F3813 */
5658 { "vcvtph2ps", { XM
, EXxmmq
}, 0 },
5661 /* PREFIX_VEX_0F3816 */
5665 { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2
) },
5668 /* PREFIX_VEX_0F3817 */
5672 { VEX_W_TABLE (VEX_W_0F3817_P_2
) },
5675 /* PREFIX_VEX_0F3818 */
5679 { VEX_W_TABLE (VEX_W_0F3818_P_2
) },
5682 /* PREFIX_VEX_0F3819 */
5686 { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2
) },
5689 /* PREFIX_VEX_0F381A */
5693 { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2
) },
5696 /* PREFIX_VEX_0F381C */
5700 { VEX_W_TABLE (VEX_W_0F381C_P_2
) },
5703 /* PREFIX_VEX_0F381D */
5707 { VEX_W_TABLE (VEX_W_0F381D_P_2
) },
5710 /* PREFIX_VEX_0F381E */
5714 { VEX_W_TABLE (VEX_W_0F381E_P_2
) },
5717 /* PREFIX_VEX_0F3820 */
5721 { VEX_W_TABLE (VEX_W_0F3820_P_2
) },
5724 /* PREFIX_VEX_0F3821 */
5728 { VEX_W_TABLE (VEX_W_0F3821_P_2
) },
5731 /* PREFIX_VEX_0F3822 */
5735 { VEX_W_TABLE (VEX_W_0F3822_P_2
) },
5738 /* PREFIX_VEX_0F3823 */
5742 { VEX_W_TABLE (VEX_W_0F3823_P_2
) },
5745 /* PREFIX_VEX_0F3824 */
5749 { VEX_W_TABLE (VEX_W_0F3824_P_2
) },
5752 /* PREFIX_VEX_0F3825 */
5756 { VEX_W_TABLE (VEX_W_0F3825_P_2
) },
5759 /* PREFIX_VEX_0F3828 */
5763 { VEX_W_TABLE (VEX_W_0F3828_P_2
) },
5766 /* PREFIX_VEX_0F3829 */
5770 { VEX_W_TABLE (VEX_W_0F3829_P_2
) },
5773 /* PREFIX_VEX_0F382A */
5777 { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2
) },
5780 /* PREFIX_VEX_0F382B */
5784 { VEX_W_TABLE (VEX_W_0F382B_P_2
) },
5787 /* PREFIX_VEX_0F382C */
5791 { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2
) },
5794 /* PREFIX_VEX_0F382D */
5798 { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2
) },
5801 /* PREFIX_VEX_0F382E */
5805 { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2
) },
5808 /* PREFIX_VEX_0F382F */
5812 { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2
) },
5815 /* PREFIX_VEX_0F3830 */
5819 { VEX_W_TABLE (VEX_W_0F3830_P_2
) },
5822 /* PREFIX_VEX_0F3831 */
5826 { VEX_W_TABLE (VEX_W_0F3831_P_2
) },
5829 /* PREFIX_VEX_0F3832 */
5833 { VEX_W_TABLE (VEX_W_0F3832_P_2
) },
5836 /* PREFIX_VEX_0F3833 */
5840 { VEX_W_TABLE (VEX_W_0F3833_P_2
) },
5843 /* PREFIX_VEX_0F3834 */
5847 { VEX_W_TABLE (VEX_W_0F3834_P_2
) },
5850 /* PREFIX_VEX_0F3835 */
5854 { VEX_W_TABLE (VEX_W_0F3835_P_2
) },
5857 /* PREFIX_VEX_0F3836 */
5861 { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2
) },
5864 /* PREFIX_VEX_0F3837 */
5868 { VEX_W_TABLE (VEX_W_0F3837_P_2
) },
5871 /* PREFIX_VEX_0F3838 */
5875 { VEX_W_TABLE (VEX_W_0F3838_P_2
) },
5878 /* PREFIX_VEX_0F3839 */
5882 { VEX_W_TABLE (VEX_W_0F3839_P_2
) },
5885 /* PREFIX_VEX_0F383A */
5889 { VEX_W_TABLE (VEX_W_0F383A_P_2
) },
5892 /* PREFIX_VEX_0F383B */
5896 { VEX_W_TABLE (VEX_W_0F383B_P_2
) },
5899 /* PREFIX_VEX_0F383C */
5903 { VEX_W_TABLE (VEX_W_0F383C_P_2
) },
5906 /* PREFIX_VEX_0F383D */
5910 { VEX_W_TABLE (VEX_W_0F383D_P_2
) },
5913 /* PREFIX_VEX_0F383E */
5917 { VEX_W_TABLE (VEX_W_0F383E_P_2
) },
5920 /* PREFIX_VEX_0F383F */
5924 { VEX_W_TABLE (VEX_W_0F383F_P_2
) },
5927 /* PREFIX_VEX_0F3840 */
5931 { VEX_W_TABLE (VEX_W_0F3840_P_2
) },
5934 /* PREFIX_VEX_0F3841 */
5938 { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2
) },
5941 /* PREFIX_VEX_0F3845 */
5945 { "vpsrlv%LW", { XM
, Vex
, EXx
}, 0 },
5948 /* PREFIX_VEX_0F3846 */
5952 { VEX_W_TABLE (VEX_W_0F3846_P_2
) },
5955 /* PREFIX_VEX_0F3847 */
5959 { "vpsllv%LW", { XM
, Vex
, EXx
}, 0 },
5962 /* PREFIX_VEX_0F3858 */
5966 { VEX_W_TABLE (VEX_W_0F3858_P_2
) },
5969 /* PREFIX_VEX_0F3859 */
5973 { VEX_W_TABLE (VEX_W_0F3859_P_2
) },
5976 /* PREFIX_VEX_0F385A */
5980 { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2
) },
5983 /* PREFIX_VEX_0F3878 */
5987 { VEX_W_TABLE (VEX_W_0F3878_P_2
) },
5990 /* PREFIX_VEX_0F3879 */
5994 { VEX_W_TABLE (VEX_W_0F3879_P_2
) },
5997 /* PREFIX_VEX_0F388C */
6001 { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2
) },
6004 /* PREFIX_VEX_0F388E */
6008 { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2
) },
6011 /* PREFIX_VEX_0F3890 */
6015 { "vpgatherd%LW", { XM
, MVexVSIBDWpX
, Vex
}, 0 },
6018 /* PREFIX_VEX_0F3891 */
6022 { "vpgatherq%LW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
}, 0 },
6025 /* PREFIX_VEX_0F3892 */
6029 { "vgatherdp%XW", { XM
, MVexVSIBDWpX
, Vex
}, 0 },
6032 /* PREFIX_VEX_0F3893 */
6036 { "vgatherqp%XW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
}, 0 },
6039 /* PREFIX_VEX_0F3896 */
6043 { "vfmaddsub132p%XW", { XM
, Vex
, EXx
}, 0 },
6046 /* PREFIX_VEX_0F3897 */
6050 { "vfmsubadd132p%XW", { XM
, Vex
, EXx
}, 0 },
6053 /* PREFIX_VEX_0F3898 */
6057 { "vfmadd132p%XW", { XM
, Vex
, EXx
}, 0 },
6060 /* PREFIX_VEX_0F3899 */
6064 { "vfmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6067 /* PREFIX_VEX_0F389A */
6071 { "vfmsub132p%XW", { XM
, Vex
, EXx
}, 0 },
6074 /* PREFIX_VEX_0F389B */
6078 { "vfmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6081 /* PREFIX_VEX_0F389C */
6085 { "vfnmadd132p%XW", { XM
, Vex
, EXx
}, 0 },
6088 /* PREFIX_VEX_0F389D */
6092 { "vfnmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6095 /* PREFIX_VEX_0F389E */
6099 { "vfnmsub132p%XW", { XM
, Vex
, EXx
}, 0 },
6102 /* PREFIX_VEX_0F389F */
6106 { "vfnmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6109 /* PREFIX_VEX_0F38A6 */
6113 { "vfmaddsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6117 /* PREFIX_VEX_0F38A7 */
6121 { "vfmsubadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6124 /* PREFIX_VEX_0F38A8 */
6128 { "vfmadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6131 /* PREFIX_VEX_0F38A9 */
6135 { "vfmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6138 /* PREFIX_VEX_0F38AA */
6142 { "vfmsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6145 /* PREFIX_VEX_0F38AB */
6149 { "vfmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6152 /* PREFIX_VEX_0F38AC */
6156 { "vfnmadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6159 /* PREFIX_VEX_0F38AD */
6163 { "vfnmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6166 /* PREFIX_VEX_0F38AE */
6170 { "vfnmsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6173 /* PREFIX_VEX_0F38AF */
6177 { "vfnmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6180 /* PREFIX_VEX_0F38B6 */
6184 { "vfmaddsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6187 /* PREFIX_VEX_0F38B7 */
6191 { "vfmsubadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6194 /* PREFIX_VEX_0F38B8 */
6198 { "vfmadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6201 /* PREFIX_VEX_0F38B9 */
6205 { "vfmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6208 /* PREFIX_VEX_0F38BA */
6212 { "vfmsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6215 /* PREFIX_VEX_0F38BB */
6219 { "vfmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6222 /* PREFIX_VEX_0F38BC */
6226 { "vfnmadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6229 /* PREFIX_VEX_0F38BD */
6233 { "vfnmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6236 /* PREFIX_VEX_0F38BE */
6240 { "vfnmsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6243 /* PREFIX_VEX_0F38BF */
6247 { "vfnmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6250 /* PREFIX_VEX_0F38DB */
6254 { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2
) },
6257 /* PREFIX_VEX_0F38DC */
6261 { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2
) },
6264 /* PREFIX_VEX_0F38DD */
6268 { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2
) },
6271 /* PREFIX_VEX_0F38DE */
6275 { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2
) },
6278 /* PREFIX_VEX_0F38DF */
6282 { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2
) },
6285 /* PREFIX_VEX_0F38F2 */
6287 { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0
) },
6290 /* PREFIX_VEX_0F38F3_REG_1 */
6292 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0
) },
6295 /* PREFIX_VEX_0F38F3_REG_2 */
6297 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0
) },
6300 /* PREFIX_VEX_0F38F3_REG_3 */
6302 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0
) },
6305 /* PREFIX_VEX_0F38F5 */
6307 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0
) },
6308 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1
) },
6310 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3
) },
6313 /* PREFIX_VEX_0F38F6 */
6318 { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3
) },
6321 /* PREFIX_VEX_0F38F7 */
6323 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0
) },
6324 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1
) },
6325 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2
) },
6326 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3
) },
6329 /* PREFIX_VEX_0F3A00 */
6333 { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2
) },
6336 /* PREFIX_VEX_0F3A01 */
6340 { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2
) },
6343 /* PREFIX_VEX_0F3A02 */
6347 { VEX_W_TABLE (VEX_W_0F3A02_P_2
) },
6350 /* PREFIX_VEX_0F3A04 */
6354 { VEX_W_TABLE (VEX_W_0F3A04_P_2
) },
6357 /* PREFIX_VEX_0F3A05 */
6361 { VEX_W_TABLE (VEX_W_0F3A05_P_2
) },
6364 /* PREFIX_VEX_0F3A06 */
6368 { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2
) },
6371 /* PREFIX_VEX_0F3A08 */
6375 { VEX_W_TABLE (VEX_W_0F3A08_P_2
) },
6378 /* PREFIX_VEX_0F3A09 */
6382 { VEX_W_TABLE (VEX_W_0F3A09_P_2
) },
6385 /* PREFIX_VEX_0F3A0A */
6389 { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2
) },
6392 /* PREFIX_VEX_0F3A0B */
6396 { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2
) },
6399 /* PREFIX_VEX_0F3A0C */
6403 { VEX_W_TABLE (VEX_W_0F3A0C_P_2
) },
6406 /* PREFIX_VEX_0F3A0D */
6410 { VEX_W_TABLE (VEX_W_0F3A0D_P_2
) },
6413 /* PREFIX_VEX_0F3A0E */
6417 { VEX_W_TABLE (VEX_W_0F3A0E_P_2
) },
6420 /* PREFIX_VEX_0F3A0F */
6424 { VEX_W_TABLE (VEX_W_0F3A0F_P_2
) },
6427 /* PREFIX_VEX_0F3A14 */
6431 { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2
) },
6434 /* PREFIX_VEX_0F3A15 */
6438 { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2
) },
6441 /* PREFIX_VEX_0F3A16 */
6445 { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2
) },
6448 /* PREFIX_VEX_0F3A17 */
6452 { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2
) },
6455 /* PREFIX_VEX_0F3A18 */
6459 { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2
) },
6462 /* PREFIX_VEX_0F3A19 */
6466 { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2
) },
6469 /* PREFIX_VEX_0F3A1D */
6473 { "vcvtps2ph", { EXxmmq
, XM
, Ib
}, 0 },
6476 /* PREFIX_VEX_0F3A20 */
6480 { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2
) },
6483 /* PREFIX_VEX_0F3A21 */
6487 { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2
) },
6490 /* PREFIX_VEX_0F3A22 */
6494 { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2
) },
6497 /* PREFIX_VEX_0F3A30 */
6501 { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2
) },
6504 /* PREFIX_VEX_0F3A31 */
6508 { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2
) },
6511 /* PREFIX_VEX_0F3A32 */
6515 { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2
) },
6518 /* PREFIX_VEX_0F3A33 */
6522 { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2
) },
6525 /* PREFIX_VEX_0F3A38 */
6529 { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2
) },
6532 /* PREFIX_VEX_0F3A39 */
6536 { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2
) },
6539 /* PREFIX_VEX_0F3A40 */
6543 { VEX_W_TABLE (VEX_W_0F3A40_P_2
) },
6546 /* PREFIX_VEX_0F3A41 */
6550 { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2
) },
6553 /* PREFIX_VEX_0F3A42 */
6557 { VEX_W_TABLE (VEX_W_0F3A42_P_2
) },
6560 /* PREFIX_VEX_0F3A44 */
6564 { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2
) },
6567 /* PREFIX_VEX_0F3A46 */
6571 { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2
) },
6574 /* PREFIX_VEX_0F3A48 */
6578 { VEX_W_TABLE (VEX_W_0F3A48_P_2
) },
6581 /* PREFIX_VEX_0F3A49 */
6585 { VEX_W_TABLE (VEX_W_0F3A49_P_2
) },
6588 /* PREFIX_VEX_0F3A4A */
6592 { VEX_W_TABLE (VEX_W_0F3A4A_P_2
) },
6595 /* PREFIX_VEX_0F3A4B */
6599 { VEX_W_TABLE (VEX_W_0F3A4B_P_2
) },
6602 /* PREFIX_VEX_0F3A4C */
6606 { VEX_W_TABLE (VEX_W_0F3A4C_P_2
) },
6609 /* PREFIX_VEX_0F3A5C */
6613 { "vfmaddsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6616 /* PREFIX_VEX_0F3A5D */
6620 { "vfmaddsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6623 /* PREFIX_VEX_0F3A5E */
6627 { "vfmsubaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6630 /* PREFIX_VEX_0F3A5F */
6634 { "vfmsubaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6637 /* PREFIX_VEX_0F3A60 */
6641 { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2
) },
6645 /* PREFIX_VEX_0F3A61 */
6649 { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2
) },
6652 /* PREFIX_VEX_0F3A62 */
6656 { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2
) },
6659 /* PREFIX_VEX_0F3A63 */
6663 { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2
) },
6666 /* PREFIX_VEX_0F3A68 */
6670 { "vfmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6673 /* PREFIX_VEX_0F3A69 */
6677 { "vfmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6680 /* PREFIX_VEX_0F3A6A */
6684 { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2
) },
6687 /* PREFIX_VEX_0F3A6B */
6691 { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2
) },
6694 /* PREFIX_VEX_0F3A6C */
6698 { "vfmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6701 /* PREFIX_VEX_0F3A6D */
6705 { "vfmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6708 /* PREFIX_VEX_0F3A6E */
6712 { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2
) },
6715 /* PREFIX_VEX_0F3A6F */
6719 { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2
) },
6722 /* PREFIX_VEX_0F3A78 */
6726 { "vfnmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6729 /* PREFIX_VEX_0F3A79 */
6733 { "vfnmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6736 /* PREFIX_VEX_0F3A7A */
6740 { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2
) },
6743 /* PREFIX_VEX_0F3A7B */
6747 { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2
) },
6750 /* PREFIX_VEX_0F3A7C */
6754 { "vfnmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6758 /* PREFIX_VEX_0F3A7D */
6762 { "vfnmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
6765 /* PREFIX_VEX_0F3A7E */
6769 { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2
) },
6772 /* PREFIX_VEX_0F3A7F */
6776 { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2
) },
6779 /* PREFIX_VEX_0F3ADF */
6783 { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2
) },
6786 /* PREFIX_VEX_0F3AF0 */
6791 { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3
) },
6794 #define NEED_PREFIX_TABLE
6795 #include "i386-dis-evex.h"
6796 #undef NEED_PREFIX_TABLE
6799 static const struct dis386 x86_64_table
[][2] = {
6802 { "pushP", { es
}, 0 },
6807 { "popP", { es
}, 0 },
6812 { "pushP", { cs
}, 0 },
6817 { "pushP", { ss
}, 0 },
6822 { "popP", { ss
}, 0 },
6827 { "pushP", { ds
}, 0 },
6832 { "popP", { ds
}, 0 },
6837 { "daa", { XX
}, 0 },
6842 { "das", { XX
}, 0 },
6847 { "aaa", { XX
}, 0 },
6852 { "aas", { XX
}, 0 },
6857 { "pushaP", { XX
}, 0 },
6862 { "popaP", { XX
}, 0 },
6867 { MOD_TABLE (MOD_62_32BIT
) },
6868 { EVEX_TABLE (EVEX_0F
) },
6873 { "arpl", { Ew
, Gw
}, 0 },
6874 { "movs{lq|xd}", { Gv
, Ed
}, 0 },
6879 { "ins{R|}", { Yzr
, indirDX
}, 0 },
6880 { "ins{G|}", { Yzr
, indirDX
}, 0 },
6885 { "outs{R|}", { indirDXr
, Xz
}, 0 },
6886 { "outs{G|}", { indirDXr
, Xz
}, 0 },
6891 /* Opcode 0x82 is an alias of of opcode 0x80 in 32-bit mode. */
6892 { REG_TABLE (REG_80
) },
6897 { "Jcall{T|}", { Ap
}, 0 },
6902 { MOD_TABLE (MOD_C4_32BIT
) },
6903 { VEX_C4_TABLE (VEX_0F
) },
6908 { MOD_TABLE (MOD_C5_32BIT
) },
6909 { VEX_C5_TABLE (VEX_0F
) },
6914 { "into", { XX
}, 0 },
6919 { "aam", { Ib
}, 0 },
6924 { "aad", { Ib
}, 0 },
6929 { "callP", { Jv
, BND
}, 0 },
6930 { "call@", { Jv
, BND
}, 0 }
6935 { "jmpP", { Jv
, BND
}, 0 },
6936 { "jmp@", { Jv
, BND
}, 0 }
6941 { "Jjmp{T|}", { Ap
}, 0 },
6944 /* X86_64_0F01_REG_0 */
6946 { "sgdt{Q|IQ}", { M
}, 0 },
6947 { "sgdt", { M
}, 0 },
6950 /* X86_64_0F01_REG_1 */
6952 { "sidt{Q|IQ}", { M
}, 0 },
6953 { "sidt", { M
}, 0 },
6956 /* X86_64_0F01_REG_2 */
6958 { "lgdt{Q|Q}", { M
}, 0 },
6959 { "lgdt", { M
}, 0 },
6962 /* X86_64_0F01_REG_3 */
6964 { "lidt{Q|Q}", { M
}, 0 },
6965 { "lidt", { M
}, 0 },
6969 static const struct dis386 three_byte_table
[][256] = {
6971 /* THREE_BYTE_0F38 */
6974 { "pshufb", { MX
, EM
}, PREFIX_OPCODE
},
6975 { "phaddw", { MX
, EM
}, PREFIX_OPCODE
},
6976 { "phaddd", { MX
, EM
}, PREFIX_OPCODE
},
6977 { "phaddsw", { MX
, EM
}, PREFIX_OPCODE
},
6978 { "pmaddubsw", { MX
, EM
}, PREFIX_OPCODE
},
6979 { "phsubw", { MX
, EM
}, PREFIX_OPCODE
},
6980 { "phsubd", { MX
, EM
}, PREFIX_OPCODE
},
6981 { "phsubsw", { MX
, EM
}, PREFIX_OPCODE
},
6983 { "psignb", { MX
, EM
}, PREFIX_OPCODE
},
6984 { "psignw", { MX
, EM
}, PREFIX_OPCODE
},
6985 { "psignd", { MX
, EM
}, PREFIX_OPCODE
},
6986 { "pmulhrsw", { MX
, EM
}, PREFIX_OPCODE
},
6992 { PREFIX_TABLE (PREFIX_0F3810
) },
6996 { PREFIX_TABLE (PREFIX_0F3814
) },
6997 { PREFIX_TABLE (PREFIX_0F3815
) },
6999 { PREFIX_TABLE (PREFIX_0F3817
) },
7005 { "pabsb", { MX
, EM
}, PREFIX_OPCODE
},
7006 { "pabsw", { MX
, EM
}, PREFIX_OPCODE
},
7007 { "pabsd", { MX
, EM
}, PREFIX_OPCODE
},
7010 { PREFIX_TABLE (PREFIX_0F3820
) },
7011 { PREFIX_TABLE (PREFIX_0F3821
) },
7012 { PREFIX_TABLE (PREFIX_0F3822
) },
7013 { PREFIX_TABLE (PREFIX_0F3823
) },
7014 { PREFIX_TABLE (PREFIX_0F3824
) },
7015 { PREFIX_TABLE (PREFIX_0F3825
) },
7019 { PREFIX_TABLE (PREFIX_0F3828
) },
7020 { PREFIX_TABLE (PREFIX_0F3829
) },
7021 { PREFIX_TABLE (PREFIX_0F382A
) },
7022 { PREFIX_TABLE (PREFIX_0F382B
) },
7028 { PREFIX_TABLE (PREFIX_0F3830
) },
7029 { PREFIX_TABLE (PREFIX_0F3831
) },
7030 { PREFIX_TABLE (PREFIX_0F3832
) },
7031 { PREFIX_TABLE (PREFIX_0F3833
) },
7032 { PREFIX_TABLE (PREFIX_0F3834
) },
7033 { PREFIX_TABLE (PREFIX_0F3835
) },
7035 { PREFIX_TABLE (PREFIX_0F3837
) },
7037 { PREFIX_TABLE (PREFIX_0F3838
) },
7038 { PREFIX_TABLE (PREFIX_0F3839
) },
7039 { PREFIX_TABLE (PREFIX_0F383A
) },
7040 { PREFIX_TABLE (PREFIX_0F383B
) },
7041 { PREFIX_TABLE (PREFIX_0F383C
) },
7042 { PREFIX_TABLE (PREFIX_0F383D
) },
7043 { PREFIX_TABLE (PREFIX_0F383E
) },
7044 { PREFIX_TABLE (PREFIX_0F383F
) },
7046 { PREFIX_TABLE (PREFIX_0F3840
) },
7047 { PREFIX_TABLE (PREFIX_0F3841
) },
7118 { PREFIX_TABLE (PREFIX_0F3880
) },
7119 { PREFIX_TABLE (PREFIX_0F3881
) },
7120 { PREFIX_TABLE (PREFIX_0F3882
) },
7199 { PREFIX_TABLE (PREFIX_0F38C8
) },
7200 { PREFIX_TABLE (PREFIX_0F38C9
) },
7201 { PREFIX_TABLE (PREFIX_0F38CA
) },
7202 { PREFIX_TABLE (PREFIX_0F38CB
) },
7203 { PREFIX_TABLE (PREFIX_0F38CC
) },
7204 { PREFIX_TABLE (PREFIX_0F38CD
) },
7220 { PREFIX_TABLE (PREFIX_0F38DB
) },
7221 { PREFIX_TABLE (PREFIX_0F38DC
) },
7222 { PREFIX_TABLE (PREFIX_0F38DD
) },
7223 { PREFIX_TABLE (PREFIX_0F38DE
) },
7224 { PREFIX_TABLE (PREFIX_0F38DF
) },
7244 { PREFIX_TABLE (PREFIX_0F38F0
) },
7245 { PREFIX_TABLE (PREFIX_0F38F1
) },
7250 { PREFIX_TABLE (PREFIX_0F38F6
) },
7262 /* THREE_BYTE_0F3A */
7274 { PREFIX_TABLE (PREFIX_0F3A08
) },
7275 { PREFIX_TABLE (PREFIX_0F3A09
) },
7276 { PREFIX_TABLE (PREFIX_0F3A0A
) },
7277 { PREFIX_TABLE (PREFIX_0F3A0B
) },
7278 { PREFIX_TABLE (PREFIX_0F3A0C
) },
7279 { PREFIX_TABLE (PREFIX_0F3A0D
) },
7280 { PREFIX_TABLE (PREFIX_0F3A0E
) },
7281 { "palignr", { MX
, EM
, Ib
}, PREFIX_OPCODE
},
7287 { PREFIX_TABLE (PREFIX_0F3A14
) },
7288 { PREFIX_TABLE (PREFIX_0F3A15
) },
7289 { PREFIX_TABLE (PREFIX_0F3A16
) },
7290 { PREFIX_TABLE (PREFIX_0F3A17
) },
7301 { PREFIX_TABLE (PREFIX_0F3A20
) },
7302 { PREFIX_TABLE (PREFIX_0F3A21
) },
7303 { PREFIX_TABLE (PREFIX_0F3A22
) },
7337 { PREFIX_TABLE (PREFIX_0F3A40
) },
7338 { PREFIX_TABLE (PREFIX_0F3A41
) },
7339 { PREFIX_TABLE (PREFIX_0F3A42
) },
7341 { PREFIX_TABLE (PREFIX_0F3A44
) },
7373 { PREFIX_TABLE (PREFIX_0F3A60
) },
7374 { PREFIX_TABLE (PREFIX_0F3A61
) },
7375 { PREFIX_TABLE (PREFIX_0F3A62
) },
7376 { PREFIX_TABLE (PREFIX_0F3A63
) },
7494 { PREFIX_TABLE (PREFIX_0F3ACC
) },
7515 { PREFIX_TABLE (PREFIX_0F3ADF
) },
7555 static const struct dis386 xop_table
[][256] = {
7708 { "vpmacssww", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
7709 { "vpmacsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
7710 { "vpmacssdql", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
7718 { "vpmacssdd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
7719 { "vpmacssdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
7726 { "vpmacsww", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
7727 { "vpmacswd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
7728 { "vpmacsdql", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
7736 { "vpmacsdd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
7737 { "vpmacsdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
7741 { "vpcmov", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
7742 { "vpperm", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
7745 { "vpmadcsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
7763 { "vpmadcswd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
}, 0 },
7775 { "vprotb", { XM
, Vex_2src_1
, Ib
}, 0 },
7776 { "vprotw", { XM
, Vex_2src_1
, Ib
}, 0 },
7777 { "vprotd", { XM
, Vex_2src_1
, Ib
}, 0 },
7778 { "vprotq", { XM
, Vex_2src_1
, Ib
}, 0 },
7788 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC
) },
7789 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD
) },
7790 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE
) },
7791 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF
) },
7824 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC
) },
7825 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED
) },
7826 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE
) },
7827 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF
) },
7851 { REG_TABLE (REG_XOP_TBM_01
) },
7852 { REG_TABLE (REG_XOP_TBM_02
) },
7870 { REG_TABLE (REG_XOP_LWPCB
) },
7994 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80
) },
7995 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81
) },
7996 { "vfrczss", { XM
, EXd
}, 0 },
7997 { "vfrczsd", { XM
, EXq
}, 0 },
8012 { "vprotb", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8013 { "vprotw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8014 { "vprotd", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8015 { "vprotq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8016 { "vpshlb", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8017 { "vpshlw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8018 { "vpshld", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8019 { "vpshlq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8021 { "vpshab", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8022 { "vpshaw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8023 { "vpshad", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8024 { "vpshaq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8067 { "vphaddbw", { XM
, EXxmm
}, 0 },
8068 { "vphaddbd", { XM
, EXxmm
}, 0 },
8069 { "vphaddbq", { XM
, EXxmm
}, 0 },
8072 { "vphaddwd", { XM
, EXxmm
}, 0 },
8073 { "vphaddwq", { XM
, EXxmm
}, 0 },
8078 { "vphadddq", { XM
, EXxmm
}, 0 },
8085 { "vphaddubw", { XM
, EXxmm
}, 0 },
8086 { "vphaddubd", { XM
, EXxmm
}, 0 },
8087 { "vphaddubq", { XM
, EXxmm
}, 0 },
8090 { "vphadduwd", { XM
, EXxmm
}, 0 },
8091 { "vphadduwq", { XM
, EXxmm
}, 0 },
8096 { "vphaddudq", { XM
, EXxmm
}, 0 },
8103 { "vphsubbw", { XM
, EXxmm
}, 0 },
8104 { "vphsubwd", { XM
, EXxmm
}, 0 },
8105 { "vphsubdq", { XM
, EXxmm
}, 0 },
8159 { "bextr", { Gv
, Ev
, Iq
}, 0 },
8161 { REG_TABLE (REG_XOP_LWP
) },
8431 static const struct dis386 vex_table
[][256] = {
8453 { PREFIX_TABLE (PREFIX_VEX_0F10
) },
8454 { PREFIX_TABLE (PREFIX_VEX_0F11
) },
8455 { PREFIX_TABLE (PREFIX_VEX_0F12
) },
8456 { MOD_TABLE (MOD_VEX_0F13
) },
8457 { VEX_W_TABLE (VEX_W_0F14
) },
8458 { VEX_W_TABLE (VEX_W_0F15
) },
8459 { PREFIX_TABLE (PREFIX_VEX_0F16
) },
8460 { MOD_TABLE (MOD_VEX_0F17
) },
8480 { VEX_W_TABLE (VEX_W_0F28
) },
8481 { VEX_W_TABLE (VEX_W_0F29
) },
8482 { PREFIX_TABLE (PREFIX_VEX_0F2A
) },
8483 { MOD_TABLE (MOD_VEX_0F2B
) },
8484 { PREFIX_TABLE (PREFIX_VEX_0F2C
) },
8485 { PREFIX_TABLE (PREFIX_VEX_0F2D
) },
8486 { PREFIX_TABLE (PREFIX_VEX_0F2E
) },
8487 { PREFIX_TABLE (PREFIX_VEX_0F2F
) },
8508 { PREFIX_TABLE (PREFIX_VEX_0F41
) },
8509 { PREFIX_TABLE (PREFIX_VEX_0F42
) },
8511 { PREFIX_TABLE (PREFIX_VEX_0F44
) },
8512 { PREFIX_TABLE (PREFIX_VEX_0F45
) },
8513 { PREFIX_TABLE (PREFIX_VEX_0F46
) },
8514 { PREFIX_TABLE (PREFIX_VEX_0F47
) },
8518 { PREFIX_TABLE (PREFIX_VEX_0F4A
) },
8519 { PREFIX_TABLE (PREFIX_VEX_0F4B
) },
8525 { MOD_TABLE (MOD_VEX_0F50
) },
8526 { PREFIX_TABLE (PREFIX_VEX_0F51
) },
8527 { PREFIX_TABLE (PREFIX_VEX_0F52
) },
8528 { PREFIX_TABLE (PREFIX_VEX_0F53
) },
8529 { "vandpX", { XM
, Vex
, EXx
}, 0 },
8530 { "vandnpX", { XM
, Vex
, EXx
}, 0 },
8531 { "vorpX", { XM
, Vex
, EXx
}, 0 },
8532 { "vxorpX", { XM
, Vex
, EXx
}, 0 },
8534 { PREFIX_TABLE (PREFIX_VEX_0F58
) },
8535 { PREFIX_TABLE (PREFIX_VEX_0F59
) },
8536 { PREFIX_TABLE (PREFIX_VEX_0F5A
) },
8537 { PREFIX_TABLE (PREFIX_VEX_0F5B
) },
8538 { PREFIX_TABLE (PREFIX_VEX_0F5C
) },
8539 { PREFIX_TABLE (PREFIX_VEX_0F5D
) },
8540 { PREFIX_TABLE (PREFIX_VEX_0F5E
) },
8541 { PREFIX_TABLE (PREFIX_VEX_0F5F
) },
8543 { PREFIX_TABLE (PREFIX_VEX_0F60
) },
8544 { PREFIX_TABLE (PREFIX_VEX_0F61
) },
8545 { PREFIX_TABLE (PREFIX_VEX_0F62
) },
8546 { PREFIX_TABLE (PREFIX_VEX_0F63
) },
8547 { PREFIX_TABLE (PREFIX_VEX_0F64
) },
8548 { PREFIX_TABLE (PREFIX_VEX_0F65
) },
8549 { PREFIX_TABLE (PREFIX_VEX_0F66
) },
8550 { PREFIX_TABLE (PREFIX_VEX_0F67
) },
8552 { PREFIX_TABLE (PREFIX_VEX_0F68
) },
8553 { PREFIX_TABLE (PREFIX_VEX_0F69
) },
8554 { PREFIX_TABLE (PREFIX_VEX_0F6A
) },
8555 { PREFIX_TABLE (PREFIX_VEX_0F6B
) },
8556 { PREFIX_TABLE (PREFIX_VEX_0F6C
) },
8557 { PREFIX_TABLE (PREFIX_VEX_0F6D
) },
8558 { PREFIX_TABLE (PREFIX_VEX_0F6E
) },
8559 { PREFIX_TABLE (PREFIX_VEX_0F6F
) },
8561 { PREFIX_TABLE (PREFIX_VEX_0F70
) },
8562 { REG_TABLE (REG_VEX_0F71
) },
8563 { REG_TABLE (REG_VEX_0F72
) },
8564 { REG_TABLE (REG_VEX_0F73
) },
8565 { PREFIX_TABLE (PREFIX_VEX_0F74
) },
8566 { PREFIX_TABLE (PREFIX_VEX_0F75
) },
8567 { PREFIX_TABLE (PREFIX_VEX_0F76
) },
8568 { PREFIX_TABLE (PREFIX_VEX_0F77
) },
8574 { PREFIX_TABLE (PREFIX_VEX_0F7C
) },
8575 { PREFIX_TABLE (PREFIX_VEX_0F7D
) },
8576 { PREFIX_TABLE (PREFIX_VEX_0F7E
) },
8577 { PREFIX_TABLE (PREFIX_VEX_0F7F
) },
8597 { PREFIX_TABLE (PREFIX_VEX_0F90
) },
8598 { PREFIX_TABLE (PREFIX_VEX_0F91
) },
8599 { PREFIX_TABLE (PREFIX_VEX_0F92
) },
8600 { PREFIX_TABLE (PREFIX_VEX_0F93
) },
8606 { PREFIX_TABLE (PREFIX_VEX_0F98
) },
8607 { PREFIX_TABLE (PREFIX_VEX_0F99
) },
8630 { REG_TABLE (REG_VEX_0FAE
) },
8653 { PREFIX_TABLE (PREFIX_VEX_0FC2
) },
8655 { PREFIX_TABLE (PREFIX_VEX_0FC4
) },
8656 { PREFIX_TABLE (PREFIX_VEX_0FC5
) },
8657 { "vshufpX", { XM
, Vex
, EXx
, Ib
}, 0 },
8669 { PREFIX_TABLE (PREFIX_VEX_0FD0
) },
8670 { PREFIX_TABLE (PREFIX_VEX_0FD1
) },
8671 { PREFIX_TABLE (PREFIX_VEX_0FD2
) },
8672 { PREFIX_TABLE (PREFIX_VEX_0FD3
) },
8673 { PREFIX_TABLE (PREFIX_VEX_0FD4
) },
8674 { PREFIX_TABLE (PREFIX_VEX_0FD5
) },
8675 { PREFIX_TABLE (PREFIX_VEX_0FD6
) },
8676 { PREFIX_TABLE (PREFIX_VEX_0FD7
) },
8678 { PREFIX_TABLE (PREFIX_VEX_0FD8
) },
8679 { PREFIX_TABLE (PREFIX_VEX_0FD9
) },
8680 { PREFIX_TABLE (PREFIX_VEX_0FDA
) },
8681 { PREFIX_TABLE (PREFIX_VEX_0FDB
) },
8682 { PREFIX_TABLE (PREFIX_VEX_0FDC
) },
8683 { PREFIX_TABLE (PREFIX_VEX_0FDD
) },
8684 { PREFIX_TABLE (PREFIX_VEX_0FDE
) },
8685 { PREFIX_TABLE (PREFIX_VEX_0FDF
) },
8687 { PREFIX_TABLE (PREFIX_VEX_0FE0
) },
8688 { PREFIX_TABLE (PREFIX_VEX_0FE1
) },
8689 { PREFIX_TABLE (PREFIX_VEX_0FE2
) },
8690 { PREFIX_TABLE (PREFIX_VEX_0FE3
) },
8691 { PREFIX_TABLE (PREFIX_VEX_0FE4
) },
8692 { PREFIX_TABLE (PREFIX_VEX_0FE5
) },
8693 { PREFIX_TABLE (PREFIX_VEX_0FE6
) },
8694 { PREFIX_TABLE (PREFIX_VEX_0FE7
) },
8696 { PREFIX_TABLE (PREFIX_VEX_0FE8
) },
8697 { PREFIX_TABLE (PREFIX_VEX_0FE9
) },
8698 { PREFIX_TABLE (PREFIX_VEX_0FEA
) },
8699 { PREFIX_TABLE (PREFIX_VEX_0FEB
) },
8700 { PREFIX_TABLE (PREFIX_VEX_0FEC
) },
8701 { PREFIX_TABLE (PREFIX_VEX_0FED
) },
8702 { PREFIX_TABLE (PREFIX_VEX_0FEE
) },
8703 { PREFIX_TABLE (PREFIX_VEX_0FEF
) },
8705 { PREFIX_TABLE (PREFIX_VEX_0FF0
) },
8706 { PREFIX_TABLE (PREFIX_VEX_0FF1
) },
8707 { PREFIX_TABLE (PREFIX_VEX_0FF2
) },
8708 { PREFIX_TABLE (PREFIX_VEX_0FF3
) },
8709 { PREFIX_TABLE (PREFIX_VEX_0FF4
) },
8710 { PREFIX_TABLE (PREFIX_VEX_0FF5
) },
8711 { PREFIX_TABLE (PREFIX_VEX_0FF6
) },
8712 { PREFIX_TABLE (PREFIX_VEX_0FF7
) },
8714 { PREFIX_TABLE (PREFIX_VEX_0FF8
) },
8715 { PREFIX_TABLE (PREFIX_VEX_0FF9
) },
8716 { PREFIX_TABLE (PREFIX_VEX_0FFA
) },
8717 { PREFIX_TABLE (PREFIX_VEX_0FFB
) },
8718 { PREFIX_TABLE (PREFIX_VEX_0FFC
) },
8719 { PREFIX_TABLE (PREFIX_VEX_0FFD
) },
8720 { PREFIX_TABLE (PREFIX_VEX_0FFE
) },
8726 { PREFIX_TABLE (PREFIX_VEX_0F3800
) },
8727 { PREFIX_TABLE (PREFIX_VEX_0F3801
) },
8728 { PREFIX_TABLE (PREFIX_VEX_0F3802
) },
8729 { PREFIX_TABLE (PREFIX_VEX_0F3803
) },
8730 { PREFIX_TABLE (PREFIX_VEX_0F3804
) },
8731 { PREFIX_TABLE (PREFIX_VEX_0F3805
) },
8732 { PREFIX_TABLE (PREFIX_VEX_0F3806
) },
8733 { PREFIX_TABLE (PREFIX_VEX_0F3807
) },
8735 { PREFIX_TABLE (PREFIX_VEX_0F3808
) },
8736 { PREFIX_TABLE (PREFIX_VEX_0F3809
) },
8737 { PREFIX_TABLE (PREFIX_VEX_0F380A
) },
8738 { PREFIX_TABLE (PREFIX_VEX_0F380B
) },
8739 { PREFIX_TABLE (PREFIX_VEX_0F380C
) },
8740 { PREFIX_TABLE (PREFIX_VEX_0F380D
) },
8741 { PREFIX_TABLE (PREFIX_VEX_0F380E
) },
8742 { PREFIX_TABLE (PREFIX_VEX_0F380F
) },
8747 { PREFIX_TABLE (PREFIX_VEX_0F3813
) },
8750 { PREFIX_TABLE (PREFIX_VEX_0F3816
) },
8751 { PREFIX_TABLE (PREFIX_VEX_0F3817
) },
8753 { PREFIX_TABLE (PREFIX_VEX_0F3818
) },
8754 { PREFIX_TABLE (PREFIX_VEX_0F3819
) },
8755 { PREFIX_TABLE (PREFIX_VEX_0F381A
) },
8757 { PREFIX_TABLE (PREFIX_VEX_0F381C
) },
8758 { PREFIX_TABLE (PREFIX_VEX_0F381D
) },
8759 { PREFIX_TABLE (PREFIX_VEX_0F381E
) },
8762 { PREFIX_TABLE (PREFIX_VEX_0F3820
) },
8763 { PREFIX_TABLE (PREFIX_VEX_0F3821
) },
8764 { PREFIX_TABLE (PREFIX_VEX_0F3822
) },
8765 { PREFIX_TABLE (PREFIX_VEX_0F3823
) },
8766 { PREFIX_TABLE (PREFIX_VEX_0F3824
) },
8767 { PREFIX_TABLE (PREFIX_VEX_0F3825
) },
8771 { PREFIX_TABLE (PREFIX_VEX_0F3828
) },
8772 { PREFIX_TABLE (PREFIX_VEX_0F3829
) },
8773 { PREFIX_TABLE (PREFIX_VEX_0F382A
) },
8774 { PREFIX_TABLE (PREFIX_VEX_0F382B
) },
8775 { PREFIX_TABLE (PREFIX_VEX_0F382C
) },
8776 { PREFIX_TABLE (PREFIX_VEX_0F382D
) },
8777 { PREFIX_TABLE (PREFIX_VEX_0F382E
) },
8778 { PREFIX_TABLE (PREFIX_VEX_0F382F
) },
8780 { PREFIX_TABLE (PREFIX_VEX_0F3830
) },
8781 { PREFIX_TABLE (PREFIX_VEX_0F3831
) },
8782 { PREFIX_TABLE (PREFIX_VEX_0F3832
) },
8783 { PREFIX_TABLE (PREFIX_VEX_0F3833
) },
8784 { PREFIX_TABLE (PREFIX_VEX_0F3834
) },
8785 { PREFIX_TABLE (PREFIX_VEX_0F3835
) },
8786 { PREFIX_TABLE (PREFIX_VEX_0F3836
) },
8787 { PREFIX_TABLE (PREFIX_VEX_0F3837
) },
8789 { PREFIX_TABLE (PREFIX_VEX_0F3838
) },
8790 { PREFIX_TABLE (PREFIX_VEX_0F3839
) },
8791 { PREFIX_TABLE (PREFIX_VEX_0F383A
) },
8792 { PREFIX_TABLE (PREFIX_VEX_0F383B
) },
8793 { PREFIX_TABLE (PREFIX_VEX_0F383C
) },
8794 { PREFIX_TABLE (PREFIX_VEX_0F383D
) },
8795 { PREFIX_TABLE (PREFIX_VEX_0F383E
) },
8796 { PREFIX_TABLE (PREFIX_VEX_0F383F
) },
8798 { PREFIX_TABLE (PREFIX_VEX_0F3840
) },
8799 { PREFIX_TABLE (PREFIX_VEX_0F3841
) },
8803 { PREFIX_TABLE (PREFIX_VEX_0F3845
) },
8804 { PREFIX_TABLE (PREFIX_VEX_0F3846
) },
8805 { PREFIX_TABLE (PREFIX_VEX_0F3847
) },
8825 { PREFIX_TABLE (PREFIX_VEX_0F3858
) },
8826 { PREFIX_TABLE (PREFIX_VEX_0F3859
) },
8827 { PREFIX_TABLE (PREFIX_VEX_0F385A
) },
8861 { PREFIX_TABLE (PREFIX_VEX_0F3878
) },
8862 { PREFIX_TABLE (PREFIX_VEX_0F3879
) },
8883 { PREFIX_TABLE (PREFIX_VEX_0F388C
) },
8885 { PREFIX_TABLE (PREFIX_VEX_0F388E
) },
8888 { PREFIX_TABLE (PREFIX_VEX_0F3890
) },
8889 { PREFIX_TABLE (PREFIX_VEX_0F3891
) },
8890 { PREFIX_TABLE (PREFIX_VEX_0F3892
) },
8891 { PREFIX_TABLE (PREFIX_VEX_0F3893
) },
8894 { PREFIX_TABLE (PREFIX_VEX_0F3896
) },
8895 { PREFIX_TABLE (PREFIX_VEX_0F3897
) },
8897 { PREFIX_TABLE (PREFIX_VEX_0F3898
) },
8898 { PREFIX_TABLE (PREFIX_VEX_0F3899
) },
8899 { PREFIX_TABLE (PREFIX_VEX_0F389A
) },
8900 { PREFIX_TABLE (PREFIX_VEX_0F389B
) },
8901 { PREFIX_TABLE (PREFIX_VEX_0F389C
) },
8902 { PREFIX_TABLE (PREFIX_VEX_0F389D
) },
8903 { PREFIX_TABLE (PREFIX_VEX_0F389E
) },
8904 { PREFIX_TABLE (PREFIX_VEX_0F389F
) },
8912 { PREFIX_TABLE (PREFIX_VEX_0F38A6
) },
8913 { PREFIX_TABLE (PREFIX_VEX_0F38A7
) },
8915 { PREFIX_TABLE (PREFIX_VEX_0F38A8
) },
8916 { PREFIX_TABLE (PREFIX_VEX_0F38A9
) },
8917 { PREFIX_TABLE (PREFIX_VEX_0F38AA
) },
8918 { PREFIX_TABLE (PREFIX_VEX_0F38AB
) },
8919 { PREFIX_TABLE (PREFIX_VEX_0F38AC
) },
8920 { PREFIX_TABLE (PREFIX_VEX_0F38AD
) },
8921 { PREFIX_TABLE (PREFIX_VEX_0F38AE
) },
8922 { PREFIX_TABLE (PREFIX_VEX_0F38AF
) },
8930 { PREFIX_TABLE (PREFIX_VEX_0F38B6
) },
8931 { PREFIX_TABLE (PREFIX_VEX_0F38B7
) },
8933 { PREFIX_TABLE (PREFIX_VEX_0F38B8
) },
8934 { PREFIX_TABLE (PREFIX_VEX_0F38B9
) },
8935 { PREFIX_TABLE (PREFIX_VEX_0F38BA
) },
8936 { PREFIX_TABLE (PREFIX_VEX_0F38BB
) },
8937 { PREFIX_TABLE (PREFIX_VEX_0F38BC
) },
8938 { PREFIX_TABLE (PREFIX_VEX_0F38BD
) },
8939 { PREFIX_TABLE (PREFIX_VEX_0F38BE
) },
8940 { PREFIX_TABLE (PREFIX_VEX_0F38BF
) },
8972 { PREFIX_TABLE (PREFIX_VEX_0F38DB
) },
8973 { PREFIX_TABLE (PREFIX_VEX_0F38DC
) },
8974 { PREFIX_TABLE (PREFIX_VEX_0F38DD
) },
8975 { PREFIX_TABLE (PREFIX_VEX_0F38DE
) },
8976 { PREFIX_TABLE (PREFIX_VEX_0F38DF
) },
8998 { PREFIX_TABLE (PREFIX_VEX_0F38F2
) },
8999 { REG_TABLE (REG_VEX_0F38F3
) },
9001 { PREFIX_TABLE (PREFIX_VEX_0F38F5
) },
9002 { PREFIX_TABLE (PREFIX_VEX_0F38F6
) },
9003 { PREFIX_TABLE (PREFIX_VEX_0F38F7
) },
9017 { PREFIX_TABLE (PREFIX_VEX_0F3A00
) },
9018 { PREFIX_TABLE (PREFIX_VEX_0F3A01
) },
9019 { PREFIX_TABLE (PREFIX_VEX_0F3A02
) },
9021 { PREFIX_TABLE (PREFIX_VEX_0F3A04
) },
9022 { PREFIX_TABLE (PREFIX_VEX_0F3A05
) },
9023 { PREFIX_TABLE (PREFIX_VEX_0F3A06
) },
9026 { PREFIX_TABLE (PREFIX_VEX_0F3A08
) },
9027 { PREFIX_TABLE (PREFIX_VEX_0F3A09
) },
9028 { PREFIX_TABLE (PREFIX_VEX_0F3A0A
) },
9029 { PREFIX_TABLE (PREFIX_VEX_0F3A0B
) },
9030 { PREFIX_TABLE (PREFIX_VEX_0F3A0C
) },
9031 { PREFIX_TABLE (PREFIX_VEX_0F3A0D
) },
9032 { PREFIX_TABLE (PREFIX_VEX_0F3A0E
) },
9033 { PREFIX_TABLE (PREFIX_VEX_0F3A0F
) },
9039 { PREFIX_TABLE (PREFIX_VEX_0F3A14
) },
9040 { PREFIX_TABLE (PREFIX_VEX_0F3A15
) },
9041 { PREFIX_TABLE (PREFIX_VEX_0F3A16
) },
9042 { PREFIX_TABLE (PREFIX_VEX_0F3A17
) },
9044 { PREFIX_TABLE (PREFIX_VEX_0F3A18
) },
9045 { PREFIX_TABLE (PREFIX_VEX_0F3A19
) },
9049 { PREFIX_TABLE (PREFIX_VEX_0F3A1D
) },
9053 { PREFIX_TABLE (PREFIX_VEX_0F3A20
) },
9054 { PREFIX_TABLE (PREFIX_VEX_0F3A21
) },
9055 { PREFIX_TABLE (PREFIX_VEX_0F3A22
) },
9071 { PREFIX_TABLE (PREFIX_VEX_0F3A30
) },
9072 { PREFIX_TABLE (PREFIX_VEX_0F3A31
) },
9073 { PREFIX_TABLE (PREFIX_VEX_0F3A32
) },
9074 { PREFIX_TABLE (PREFIX_VEX_0F3A33
) },
9080 { PREFIX_TABLE (PREFIX_VEX_0F3A38
) },
9081 { PREFIX_TABLE (PREFIX_VEX_0F3A39
) },
9089 { PREFIX_TABLE (PREFIX_VEX_0F3A40
) },
9090 { PREFIX_TABLE (PREFIX_VEX_0F3A41
) },
9091 { PREFIX_TABLE (PREFIX_VEX_0F3A42
) },
9093 { PREFIX_TABLE (PREFIX_VEX_0F3A44
) },
9095 { PREFIX_TABLE (PREFIX_VEX_0F3A46
) },
9098 { PREFIX_TABLE (PREFIX_VEX_0F3A48
) },
9099 { PREFIX_TABLE (PREFIX_VEX_0F3A49
) },
9100 { PREFIX_TABLE (PREFIX_VEX_0F3A4A
) },
9101 { PREFIX_TABLE (PREFIX_VEX_0F3A4B
) },
9102 { PREFIX_TABLE (PREFIX_VEX_0F3A4C
) },
9120 { PREFIX_TABLE (PREFIX_VEX_0F3A5C
) },
9121 { PREFIX_TABLE (PREFIX_VEX_0F3A5D
) },
9122 { PREFIX_TABLE (PREFIX_VEX_0F3A5E
) },
9123 { PREFIX_TABLE (PREFIX_VEX_0F3A5F
) },
9125 { PREFIX_TABLE (PREFIX_VEX_0F3A60
) },
9126 { PREFIX_TABLE (PREFIX_VEX_0F3A61
) },
9127 { PREFIX_TABLE (PREFIX_VEX_0F3A62
) },
9128 { PREFIX_TABLE (PREFIX_VEX_0F3A63
) },
9134 { PREFIX_TABLE (PREFIX_VEX_0F3A68
) },
9135 { PREFIX_TABLE (PREFIX_VEX_0F3A69
) },
9136 { PREFIX_TABLE (PREFIX_VEX_0F3A6A
) },
9137 { PREFIX_TABLE (PREFIX_VEX_0F3A6B
) },
9138 { PREFIX_TABLE (PREFIX_VEX_0F3A6C
) },
9139 { PREFIX_TABLE (PREFIX_VEX_0F3A6D
) },
9140 { PREFIX_TABLE (PREFIX_VEX_0F3A6E
) },
9141 { PREFIX_TABLE (PREFIX_VEX_0F3A6F
) },
9152 { PREFIX_TABLE (PREFIX_VEX_0F3A78
) },
9153 { PREFIX_TABLE (PREFIX_VEX_0F3A79
) },
9154 { PREFIX_TABLE (PREFIX_VEX_0F3A7A
) },
9155 { PREFIX_TABLE (PREFIX_VEX_0F3A7B
) },
9156 { PREFIX_TABLE (PREFIX_VEX_0F3A7C
) },
9157 { PREFIX_TABLE (PREFIX_VEX_0F3A7D
) },
9158 { PREFIX_TABLE (PREFIX_VEX_0F3A7E
) },
9159 { PREFIX_TABLE (PREFIX_VEX_0F3A7F
) },
9267 { PREFIX_TABLE (PREFIX_VEX_0F3ADF
) },
9287 { PREFIX_TABLE (PREFIX_VEX_0F3AF0
) },
9307 #define NEED_OPCODE_TABLE
9308 #include "i386-dis-evex.h"
9309 #undef NEED_OPCODE_TABLE
9310 static const struct dis386 vex_len_table
[][2] = {
9311 /* VEX_LEN_0F10_P_1 */
9313 { VEX_W_TABLE (VEX_W_0F10_P_1
) },
9314 { VEX_W_TABLE (VEX_W_0F10_P_1
) },
9317 /* VEX_LEN_0F10_P_3 */
9319 { VEX_W_TABLE (VEX_W_0F10_P_3
) },
9320 { VEX_W_TABLE (VEX_W_0F10_P_3
) },
9323 /* VEX_LEN_0F11_P_1 */
9325 { VEX_W_TABLE (VEX_W_0F11_P_1
) },
9326 { VEX_W_TABLE (VEX_W_0F11_P_1
) },
9329 /* VEX_LEN_0F11_P_3 */
9331 { VEX_W_TABLE (VEX_W_0F11_P_3
) },
9332 { VEX_W_TABLE (VEX_W_0F11_P_3
) },
9335 /* VEX_LEN_0F12_P_0_M_0 */
9337 { VEX_W_TABLE (VEX_W_0F12_P_0_M_0
) },
9340 /* VEX_LEN_0F12_P_0_M_1 */
9342 { VEX_W_TABLE (VEX_W_0F12_P_0_M_1
) },
9345 /* VEX_LEN_0F12_P_2 */
9347 { VEX_W_TABLE (VEX_W_0F12_P_2
) },
9350 /* VEX_LEN_0F13_M_0 */
9352 { VEX_W_TABLE (VEX_W_0F13_M_0
) },
9355 /* VEX_LEN_0F16_P_0_M_0 */
9357 { VEX_W_TABLE (VEX_W_0F16_P_0_M_0
) },
9360 /* VEX_LEN_0F16_P_0_M_1 */
9362 { VEX_W_TABLE (VEX_W_0F16_P_0_M_1
) },
9365 /* VEX_LEN_0F16_P_2 */
9367 { VEX_W_TABLE (VEX_W_0F16_P_2
) },
9370 /* VEX_LEN_0F17_M_0 */
9372 { VEX_W_TABLE (VEX_W_0F17_M_0
) },
9375 /* VEX_LEN_0F2A_P_1 */
9377 { "vcvtsi2ss%LQ", { XMScalar
, VexScalar
, Ev
}, 0 },
9378 { "vcvtsi2ss%LQ", { XMScalar
, VexScalar
, Ev
}, 0 },
9381 /* VEX_LEN_0F2A_P_3 */
9383 { "vcvtsi2sd%LQ", { XMScalar
, VexScalar
, Ev
}, 0 },
9384 { "vcvtsi2sd%LQ", { XMScalar
, VexScalar
, Ev
}, 0 },
9387 /* VEX_LEN_0F2C_P_1 */
9389 { "vcvttss2siY", { Gv
, EXdScalar
}, 0 },
9390 { "vcvttss2siY", { Gv
, EXdScalar
}, 0 },
9393 /* VEX_LEN_0F2C_P_3 */
9395 { "vcvttsd2siY", { Gv
, EXqScalar
}, 0 },
9396 { "vcvttsd2siY", { Gv
, EXqScalar
}, 0 },
9399 /* VEX_LEN_0F2D_P_1 */
9401 { "vcvtss2siY", { Gv
, EXdScalar
}, 0 },
9402 { "vcvtss2siY", { Gv
, EXdScalar
}, 0 },
9405 /* VEX_LEN_0F2D_P_3 */
9407 { "vcvtsd2siY", { Gv
, EXqScalar
}, 0 },
9408 { "vcvtsd2siY", { Gv
, EXqScalar
}, 0 },
9411 /* VEX_LEN_0F2E_P_0 */
9413 { VEX_W_TABLE (VEX_W_0F2E_P_0
) },
9414 { VEX_W_TABLE (VEX_W_0F2E_P_0
) },
9417 /* VEX_LEN_0F2E_P_2 */
9419 { VEX_W_TABLE (VEX_W_0F2E_P_2
) },
9420 { VEX_W_TABLE (VEX_W_0F2E_P_2
) },
9423 /* VEX_LEN_0F2F_P_0 */
9425 { VEX_W_TABLE (VEX_W_0F2F_P_0
) },
9426 { VEX_W_TABLE (VEX_W_0F2F_P_0
) },
9429 /* VEX_LEN_0F2F_P_2 */
9431 { VEX_W_TABLE (VEX_W_0F2F_P_2
) },
9432 { VEX_W_TABLE (VEX_W_0F2F_P_2
) },
9435 /* VEX_LEN_0F41_P_0 */
9438 { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1
) },
9440 /* VEX_LEN_0F41_P_2 */
9443 { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1
) },
9445 /* VEX_LEN_0F42_P_0 */
9448 { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1
) },
9450 /* VEX_LEN_0F42_P_2 */
9453 { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1
) },
9455 /* VEX_LEN_0F44_P_0 */
9457 { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0
) },
9459 /* VEX_LEN_0F44_P_2 */
9461 { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0
) },
9463 /* VEX_LEN_0F45_P_0 */
9466 { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1
) },
9468 /* VEX_LEN_0F45_P_2 */
9471 { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1
) },
9473 /* VEX_LEN_0F46_P_0 */
9476 { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1
) },
9478 /* VEX_LEN_0F46_P_2 */
9481 { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1
) },
9483 /* VEX_LEN_0F47_P_0 */
9486 { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1
) },
9488 /* VEX_LEN_0F47_P_2 */
9491 { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1
) },
9493 /* VEX_LEN_0F4A_P_0 */
9496 { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1
) },
9498 /* VEX_LEN_0F4A_P_2 */
9501 { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1
) },
9503 /* VEX_LEN_0F4B_P_0 */
9506 { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1
) },
9508 /* VEX_LEN_0F4B_P_2 */
9511 { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1
) },
9514 /* VEX_LEN_0F51_P_1 */
9516 { VEX_W_TABLE (VEX_W_0F51_P_1
) },
9517 { VEX_W_TABLE (VEX_W_0F51_P_1
) },
9520 /* VEX_LEN_0F51_P_3 */
9522 { VEX_W_TABLE (VEX_W_0F51_P_3
) },
9523 { VEX_W_TABLE (VEX_W_0F51_P_3
) },
9526 /* VEX_LEN_0F52_P_1 */
9528 { VEX_W_TABLE (VEX_W_0F52_P_1
) },
9529 { VEX_W_TABLE (VEX_W_0F52_P_1
) },
9532 /* VEX_LEN_0F53_P_1 */
9534 { VEX_W_TABLE (VEX_W_0F53_P_1
) },
9535 { VEX_W_TABLE (VEX_W_0F53_P_1
) },
9538 /* VEX_LEN_0F58_P_1 */
9540 { VEX_W_TABLE (VEX_W_0F58_P_1
) },
9541 { VEX_W_TABLE (VEX_W_0F58_P_1
) },
9544 /* VEX_LEN_0F58_P_3 */
9546 { VEX_W_TABLE (VEX_W_0F58_P_3
) },
9547 { VEX_W_TABLE (VEX_W_0F58_P_3
) },
9550 /* VEX_LEN_0F59_P_1 */
9552 { VEX_W_TABLE (VEX_W_0F59_P_1
) },
9553 { VEX_W_TABLE (VEX_W_0F59_P_1
) },
9556 /* VEX_LEN_0F59_P_3 */
9558 { VEX_W_TABLE (VEX_W_0F59_P_3
) },
9559 { VEX_W_TABLE (VEX_W_0F59_P_3
) },
9562 /* VEX_LEN_0F5A_P_1 */
9564 { VEX_W_TABLE (VEX_W_0F5A_P_1
) },
9565 { VEX_W_TABLE (VEX_W_0F5A_P_1
) },
9568 /* VEX_LEN_0F5A_P_3 */
9570 { VEX_W_TABLE (VEX_W_0F5A_P_3
) },
9571 { VEX_W_TABLE (VEX_W_0F5A_P_3
) },
9574 /* VEX_LEN_0F5C_P_1 */
9576 { VEX_W_TABLE (VEX_W_0F5C_P_1
) },
9577 { VEX_W_TABLE (VEX_W_0F5C_P_1
) },
9580 /* VEX_LEN_0F5C_P_3 */
9582 { VEX_W_TABLE (VEX_W_0F5C_P_3
) },
9583 { VEX_W_TABLE (VEX_W_0F5C_P_3
) },
9586 /* VEX_LEN_0F5D_P_1 */
9588 { VEX_W_TABLE (VEX_W_0F5D_P_1
) },
9589 { VEX_W_TABLE (VEX_W_0F5D_P_1
) },
9592 /* VEX_LEN_0F5D_P_3 */
9594 { VEX_W_TABLE (VEX_W_0F5D_P_3
) },
9595 { VEX_W_TABLE (VEX_W_0F5D_P_3
) },
9598 /* VEX_LEN_0F5E_P_1 */
9600 { VEX_W_TABLE (VEX_W_0F5E_P_1
) },
9601 { VEX_W_TABLE (VEX_W_0F5E_P_1
) },
9604 /* VEX_LEN_0F5E_P_3 */
9606 { VEX_W_TABLE (VEX_W_0F5E_P_3
) },
9607 { VEX_W_TABLE (VEX_W_0F5E_P_3
) },
9610 /* VEX_LEN_0F5F_P_1 */
9612 { VEX_W_TABLE (VEX_W_0F5F_P_1
) },
9613 { VEX_W_TABLE (VEX_W_0F5F_P_1
) },
9616 /* VEX_LEN_0F5F_P_3 */
9618 { VEX_W_TABLE (VEX_W_0F5F_P_3
) },
9619 { VEX_W_TABLE (VEX_W_0F5F_P_3
) },
9622 /* VEX_LEN_0F6E_P_2 */
9624 { "vmovK", { XMScalar
, Edq
}, 0 },
9625 { "vmovK", { XMScalar
, Edq
}, 0 },
9628 /* VEX_LEN_0F7E_P_1 */
9630 { VEX_W_TABLE (VEX_W_0F7E_P_1
) },
9631 { VEX_W_TABLE (VEX_W_0F7E_P_1
) },
9634 /* VEX_LEN_0F7E_P_2 */
9636 { "vmovK", { Edq
, XMScalar
}, 0 },
9637 { "vmovK", { Edq
, XMScalar
}, 0 },
9640 /* VEX_LEN_0F90_P_0 */
9642 { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0
) },
9645 /* VEX_LEN_0F90_P_2 */
9647 { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0
) },
9650 /* VEX_LEN_0F91_P_0 */
9652 { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0
) },
9655 /* VEX_LEN_0F91_P_2 */
9657 { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0
) },
9660 /* VEX_LEN_0F92_P_0 */
9662 { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0
) },
9665 /* VEX_LEN_0F92_P_2 */
9667 { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0
) },
9670 /* VEX_LEN_0F92_P_3 */
9672 { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0
) },
9675 /* VEX_LEN_0F93_P_0 */
9677 { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0
) },
9680 /* VEX_LEN_0F93_P_2 */
9682 { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0
) },
9685 /* VEX_LEN_0F93_P_3 */
9687 { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0
) },
9690 /* VEX_LEN_0F98_P_0 */
9692 { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0
) },
9695 /* VEX_LEN_0F98_P_2 */
9697 { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0
) },
9700 /* VEX_LEN_0F99_P_0 */
9702 { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0
) },
9705 /* VEX_LEN_0F99_P_2 */
9707 { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0
) },
9710 /* VEX_LEN_0FAE_R_2_M_0 */
9712 { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0
) },
9715 /* VEX_LEN_0FAE_R_3_M_0 */
9717 { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0
) },
9720 /* VEX_LEN_0FC2_P_1 */
9722 { VEX_W_TABLE (VEX_W_0FC2_P_1
) },
9723 { VEX_W_TABLE (VEX_W_0FC2_P_1
) },
9726 /* VEX_LEN_0FC2_P_3 */
9728 { VEX_W_TABLE (VEX_W_0FC2_P_3
) },
9729 { VEX_W_TABLE (VEX_W_0FC2_P_3
) },
9732 /* VEX_LEN_0FC4_P_2 */
9734 { VEX_W_TABLE (VEX_W_0FC4_P_2
) },
9737 /* VEX_LEN_0FC5_P_2 */
9739 { VEX_W_TABLE (VEX_W_0FC5_P_2
) },
9742 /* VEX_LEN_0FD6_P_2 */
9744 { VEX_W_TABLE (VEX_W_0FD6_P_2
) },
9745 { VEX_W_TABLE (VEX_W_0FD6_P_2
) },
9748 /* VEX_LEN_0FF7_P_2 */
9750 { VEX_W_TABLE (VEX_W_0FF7_P_2
) },
9753 /* VEX_LEN_0F3816_P_2 */
9756 { VEX_W_TABLE (VEX_W_0F3816_P_2
) },
9759 /* VEX_LEN_0F3819_P_2 */
9762 { VEX_W_TABLE (VEX_W_0F3819_P_2
) },
9765 /* VEX_LEN_0F381A_P_2_M_0 */
9768 { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0
) },
9771 /* VEX_LEN_0F3836_P_2 */
9774 { VEX_W_TABLE (VEX_W_0F3836_P_2
) },
9777 /* VEX_LEN_0F3841_P_2 */
9779 { VEX_W_TABLE (VEX_W_0F3841_P_2
) },
9782 /* VEX_LEN_0F385A_P_2_M_0 */
9785 { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0
) },
9788 /* VEX_LEN_0F38DB_P_2 */
9790 { VEX_W_TABLE (VEX_W_0F38DB_P_2
) },
9793 /* VEX_LEN_0F38DC_P_2 */
9795 { VEX_W_TABLE (VEX_W_0F38DC_P_2
) },
9798 /* VEX_LEN_0F38DD_P_2 */
9800 { VEX_W_TABLE (VEX_W_0F38DD_P_2
) },
9803 /* VEX_LEN_0F38DE_P_2 */
9805 { VEX_W_TABLE (VEX_W_0F38DE_P_2
) },
9808 /* VEX_LEN_0F38DF_P_2 */
9810 { VEX_W_TABLE (VEX_W_0F38DF_P_2
) },
9813 /* VEX_LEN_0F38F2_P_0 */
9815 { "andnS", { Gdq
, VexGdq
, Edq
}, 0 },
9818 /* VEX_LEN_0F38F3_R_1_P_0 */
9820 { "blsrS", { VexGdq
, Edq
}, 0 },
9823 /* VEX_LEN_0F38F3_R_2_P_0 */
9825 { "blsmskS", { VexGdq
, Edq
}, 0 },
9828 /* VEX_LEN_0F38F3_R_3_P_0 */
9830 { "blsiS", { VexGdq
, Edq
}, 0 },
9833 /* VEX_LEN_0F38F5_P_0 */
9835 { "bzhiS", { Gdq
, Edq
, VexGdq
}, 0 },
9838 /* VEX_LEN_0F38F5_P_1 */
9840 { "pextS", { Gdq
, VexGdq
, Edq
}, 0 },
9843 /* VEX_LEN_0F38F5_P_3 */
9845 { "pdepS", { Gdq
, VexGdq
, Edq
}, 0 },
9848 /* VEX_LEN_0F38F6_P_3 */
9850 { "mulxS", { Gdq
, VexGdq
, Edq
}, 0 },
9853 /* VEX_LEN_0F38F7_P_0 */
9855 { "bextrS", { Gdq
, Edq
, VexGdq
}, 0 },
9858 /* VEX_LEN_0F38F7_P_1 */
9860 { "sarxS", { Gdq
, Edq
, VexGdq
}, 0 },
9863 /* VEX_LEN_0F38F7_P_2 */
9865 { "shlxS", { Gdq
, Edq
, VexGdq
}, 0 },
9868 /* VEX_LEN_0F38F7_P_3 */
9870 { "shrxS", { Gdq
, Edq
, VexGdq
}, 0 },
9873 /* VEX_LEN_0F3A00_P_2 */
9876 { VEX_W_TABLE (VEX_W_0F3A00_P_2
) },
9879 /* VEX_LEN_0F3A01_P_2 */
9882 { VEX_W_TABLE (VEX_W_0F3A01_P_2
) },
9885 /* VEX_LEN_0F3A06_P_2 */
9888 { VEX_W_TABLE (VEX_W_0F3A06_P_2
) },
9891 /* VEX_LEN_0F3A0A_P_2 */
9893 { VEX_W_TABLE (VEX_W_0F3A0A_P_2
) },
9894 { VEX_W_TABLE (VEX_W_0F3A0A_P_2
) },
9897 /* VEX_LEN_0F3A0B_P_2 */
9899 { VEX_W_TABLE (VEX_W_0F3A0B_P_2
) },
9900 { VEX_W_TABLE (VEX_W_0F3A0B_P_2
) },
9903 /* VEX_LEN_0F3A14_P_2 */
9905 { VEX_W_TABLE (VEX_W_0F3A14_P_2
) },
9908 /* VEX_LEN_0F3A15_P_2 */
9910 { VEX_W_TABLE (VEX_W_0F3A15_P_2
) },
9913 /* VEX_LEN_0F3A16_P_2 */
9915 { "vpextrK", { Edq
, XM
, Ib
}, 0 },
9918 /* VEX_LEN_0F3A17_P_2 */
9920 { "vextractps", { Edqd
, XM
, Ib
}, 0 },
9923 /* VEX_LEN_0F3A18_P_2 */
9926 { VEX_W_TABLE (VEX_W_0F3A18_P_2
) },
9929 /* VEX_LEN_0F3A19_P_2 */
9932 { VEX_W_TABLE (VEX_W_0F3A19_P_2
) },
9935 /* VEX_LEN_0F3A20_P_2 */
9937 { VEX_W_TABLE (VEX_W_0F3A20_P_2
) },
9940 /* VEX_LEN_0F3A21_P_2 */
9942 { VEX_W_TABLE (VEX_W_0F3A21_P_2
) },
9945 /* VEX_LEN_0F3A22_P_2 */
9947 { "vpinsrK", { XM
, Vex128
, Edq
, Ib
}, 0 },
9950 /* VEX_LEN_0F3A30_P_2 */
9952 { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0
) },
9955 /* VEX_LEN_0F3A31_P_2 */
9957 { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0
) },
9960 /* VEX_LEN_0F3A32_P_2 */
9962 { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0
) },
9965 /* VEX_LEN_0F3A33_P_2 */
9967 { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0
) },
9970 /* VEX_LEN_0F3A38_P_2 */
9973 { VEX_W_TABLE (VEX_W_0F3A38_P_2
) },
9976 /* VEX_LEN_0F3A39_P_2 */
9979 { VEX_W_TABLE (VEX_W_0F3A39_P_2
) },
9982 /* VEX_LEN_0F3A41_P_2 */
9984 { VEX_W_TABLE (VEX_W_0F3A41_P_2
) },
9987 /* VEX_LEN_0F3A44_P_2 */
9989 { VEX_W_TABLE (VEX_W_0F3A44_P_2
) },
9992 /* VEX_LEN_0F3A46_P_2 */
9995 { VEX_W_TABLE (VEX_W_0F3A46_P_2
) },
9998 /* VEX_LEN_0F3A60_P_2 */
10000 { "vpcmpestrm", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, 0 },
10003 /* VEX_LEN_0F3A61_P_2 */
10005 { "vpcmpestri", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, 0 },
10008 /* VEX_LEN_0F3A62_P_2 */
10010 { VEX_W_TABLE (VEX_W_0F3A62_P_2
) },
10013 /* VEX_LEN_0F3A63_P_2 */
10015 { VEX_W_TABLE (VEX_W_0F3A63_P_2
) },
10018 /* VEX_LEN_0F3A6A_P_2 */
10020 { "vfmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
, VexI4
}, 0 },
10023 /* VEX_LEN_0F3A6B_P_2 */
10025 { "vfmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
, VexI4
}, 0 },
10028 /* VEX_LEN_0F3A6E_P_2 */
10030 { "vfmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
, VexI4
}, 0 },
10033 /* VEX_LEN_0F3A6F_P_2 */
10035 { "vfmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
, VexI4
}, 0 },
10038 /* VEX_LEN_0F3A7A_P_2 */
10040 { "vfnmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
, VexI4
}, 0 },
10043 /* VEX_LEN_0F3A7B_P_2 */
10045 { "vfnmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
, VexI4
}, 0 },
10048 /* VEX_LEN_0F3A7E_P_2 */
10050 { "vfnmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
, VexI4
}, 0 },
10053 /* VEX_LEN_0F3A7F_P_2 */
10055 { "vfnmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
, VexI4
}, 0 },
10058 /* VEX_LEN_0F3ADF_P_2 */
10060 { VEX_W_TABLE (VEX_W_0F3ADF_P_2
) },
10063 /* VEX_LEN_0F3AF0_P_3 */
10065 { "rorxS", { Gdq
, Edq
, Ib
}, 0 },
10068 /* VEX_LEN_0FXOP_08_CC */
10070 { "vpcomb", { XM
, Vex128
, EXx
, Ib
}, 0 },
10073 /* VEX_LEN_0FXOP_08_CD */
10075 { "vpcomw", { XM
, Vex128
, EXx
, Ib
}, 0 },
10078 /* VEX_LEN_0FXOP_08_CE */
10080 { "vpcomd", { XM
, Vex128
, EXx
, Ib
}, 0 },
10083 /* VEX_LEN_0FXOP_08_CF */
10085 { "vpcomq", { XM
, Vex128
, EXx
, Ib
}, 0 },
10088 /* VEX_LEN_0FXOP_08_EC */
10090 { "vpcomub", { XM
, Vex128
, EXx
, Ib
}, 0 },
10093 /* VEX_LEN_0FXOP_08_ED */
10095 { "vpcomuw", { XM
, Vex128
, EXx
, Ib
}, 0 },
10098 /* VEX_LEN_0FXOP_08_EE */
10100 { "vpcomud", { XM
, Vex128
, EXx
, Ib
}, 0 },
10103 /* VEX_LEN_0FXOP_08_EF */
10105 { "vpcomuq", { XM
, Vex128
, EXx
, Ib
}, 0 },
10108 /* VEX_LEN_0FXOP_09_80 */
10110 { "vfrczps", { XM
, EXxmm
}, 0 },
10111 { "vfrczps", { XM
, EXymmq
}, 0 },
10114 /* VEX_LEN_0FXOP_09_81 */
10116 { "vfrczpd", { XM
, EXxmm
}, 0 },
10117 { "vfrczpd", { XM
, EXymmq
}, 0 },
10121 static const struct dis386 vex_w_table
[][2] = {
10123 /* VEX_W_0F10_P_0 */
10124 { "vmovups", { XM
, EXx
}, 0 },
10127 /* VEX_W_0F10_P_1 */
10128 { "vmovss", { XMVexScalar
, VexScalar
, EXdScalar
}, 0 },
10131 /* VEX_W_0F10_P_2 */
10132 { "vmovupd", { XM
, EXx
}, 0 },
10135 /* VEX_W_0F10_P_3 */
10136 { "vmovsd", { XMVexScalar
, VexScalar
, EXqScalar
}, 0 },
10139 /* VEX_W_0F11_P_0 */
10140 { "vmovups", { EXxS
, XM
}, 0 },
10143 /* VEX_W_0F11_P_1 */
10144 { "vmovss", { EXdVexScalarS
, VexScalar
, XMScalar
}, 0 },
10147 /* VEX_W_0F11_P_2 */
10148 { "vmovupd", { EXxS
, XM
}, 0 },
10151 /* VEX_W_0F11_P_3 */
10152 { "vmovsd", { EXqVexScalarS
, VexScalar
, XMScalar
}, 0 },
10155 /* VEX_W_0F12_P_0_M_0 */
10156 { "vmovlps", { XM
, Vex128
, EXq
}, 0 },
10159 /* VEX_W_0F12_P_0_M_1 */
10160 { "vmovhlps", { XM
, Vex128
, EXq
}, 0 },
10163 /* VEX_W_0F12_P_1 */
10164 { "vmovsldup", { XM
, EXx
}, 0 },
10167 /* VEX_W_0F12_P_2 */
10168 { "vmovlpd", { XM
, Vex128
, EXq
}, 0 },
10171 /* VEX_W_0F12_P_3 */
10172 { "vmovddup", { XM
, EXymmq
}, 0 },
10175 /* VEX_W_0F13_M_0 */
10176 { "vmovlpX", { EXq
, XM
}, 0 },
10180 { "vunpcklpX", { XM
, Vex
, EXx
}, 0 },
10184 { "vunpckhpX", { XM
, Vex
, EXx
}, 0 },
10187 /* VEX_W_0F16_P_0_M_0 */
10188 { "vmovhps", { XM
, Vex128
, EXq
}, 0 },
10191 /* VEX_W_0F16_P_0_M_1 */
10192 { "vmovlhps", { XM
, Vex128
, EXq
}, 0 },
10195 /* VEX_W_0F16_P_1 */
10196 { "vmovshdup", { XM
, EXx
}, 0 },
10199 /* VEX_W_0F16_P_2 */
10200 { "vmovhpd", { XM
, Vex128
, EXq
}, 0 },
10203 /* VEX_W_0F17_M_0 */
10204 { "vmovhpX", { EXq
, XM
}, 0 },
10208 { "vmovapX", { XM
, EXx
}, 0 },
10212 { "vmovapX", { EXxS
, XM
}, 0 },
10215 /* VEX_W_0F2B_M_0 */
10216 { "vmovntpX", { Mx
, XM
}, 0 },
10219 /* VEX_W_0F2E_P_0 */
10220 { "vucomiss", { XMScalar
, EXdScalar
}, 0 },
10223 /* VEX_W_0F2E_P_2 */
10224 { "vucomisd", { XMScalar
, EXqScalar
}, 0 },
10227 /* VEX_W_0F2F_P_0 */
10228 { "vcomiss", { XMScalar
, EXdScalar
}, 0 },
10231 /* VEX_W_0F2F_P_2 */
10232 { "vcomisd", { XMScalar
, EXqScalar
}, 0 },
10235 /* VEX_W_0F41_P_0_LEN_1 */
10236 { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1
) },
10237 { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1
) },
10240 /* VEX_W_0F41_P_2_LEN_1 */
10241 { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1
) },
10242 { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1
) }
10245 /* VEX_W_0F42_P_0_LEN_1 */
10246 { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1
) },
10247 { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1
) },
10250 /* VEX_W_0F42_P_2_LEN_1 */
10251 { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1
) },
10252 { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1
) },
10255 /* VEX_W_0F44_P_0_LEN_0 */
10256 { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1
) },
10257 { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1
) },
10260 /* VEX_W_0F44_P_2_LEN_0 */
10261 { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1
) },
10262 { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1
) },
10265 /* VEX_W_0F45_P_0_LEN_1 */
10266 { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1
) },
10267 { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1
) },
10270 /* VEX_W_0F45_P_2_LEN_1 */
10271 { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1
) },
10272 { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1
) },
10275 /* VEX_W_0F46_P_0_LEN_1 */
10276 { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1
) },
10277 { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1
) },
10280 /* VEX_W_0F46_P_2_LEN_1 */
10281 { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1
) },
10282 { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1
) },
10285 /* VEX_W_0F47_P_0_LEN_1 */
10286 { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1
) },
10287 { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1
) },
10290 /* VEX_W_0F47_P_2_LEN_1 */
10291 { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1
) },
10292 { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1
) },
10295 /* VEX_W_0F4A_P_0_LEN_1 */
10296 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1
) },
10297 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1
) },
10300 /* VEX_W_0F4A_P_2_LEN_1 */
10301 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1
) },
10302 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1
) },
10305 /* VEX_W_0F4B_P_0_LEN_1 */
10306 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1
) },
10307 { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1
) },
10310 /* VEX_W_0F4B_P_2_LEN_1 */
10311 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1
) },
10314 /* VEX_W_0F50_M_0 */
10315 { "vmovmskpX", { Gdq
, XS
}, 0 },
10318 /* VEX_W_0F51_P_0 */
10319 { "vsqrtps", { XM
, EXx
}, 0 },
10322 /* VEX_W_0F51_P_1 */
10323 { "vsqrtss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10326 /* VEX_W_0F51_P_2 */
10327 { "vsqrtpd", { XM
, EXx
}, 0 },
10330 /* VEX_W_0F51_P_3 */
10331 { "vsqrtsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10334 /* VEX_W_0F52_P_0 */
10335 { "vrsqrtps", { XM
, EXx
}, 0 },
10338 /* VEX_W_0F52_P_1 */
10339 { "vrsqrtss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10342 /* VEX_W_0F53_P_0 */
10343 { "vrcpps", { XM
, EXx
}, 0 },
10346 /* VEX_W_0F53_P_1 */
10347 { "vrcpss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10350 /* VEX_W_0F58_P_0 */
10351 { "vaddps", { XM
, Vex
, EXx
}, 0 },
10354 /* VEX_W_0F58_P_1 */
10355 { "vaddss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10358 /* VEX_W_0F58_P_2 */
10359 { "vaddpd", { XM
, Vex
, EXx
}, 0 },
10362 /* VEX_W_0F58_P_3 */
10363 { "vaddsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10366 /* VEX_W_0F59_P_0 */
10367 { "vmulps", { XM
, Vex
, EXx
}, 0 },
10370 /* VEX_W_0F59_P_1 */
10371 { "vmulss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10374 /* VEX_W_0F59_P_2 */
10375 { "vmulpd", { XM
, Vex
, EXx
}, 0 },
10378 /* VEX_W_0F59_P_3 */
10379 { "vmulsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10382 /* VEX_W_0F5A_P_0 */
10383 { "vcvtps2pd", { XM
, EXxmmq
}, 0 },
10386 /* VEX_W_0F5A_P_1 */
10387 { "vcvtss2sd", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10390 /* VEX_W_0F5A_P_3 */
10391 { "vcvtsd2ss", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10394 /* VEX_W_0F5B_P_0 */
10395 { "vcvtdq2ps", { XM
, EXx
}, 0 },
10398 /* VEX_W_0F5B_P_1 */
10399 { "vcvttps2dq", { XM
, EXx
}, 0 },
10402 /* VEX_W_0F5B_P_2 */
10403 { "vcvtps2dq", { XM
, EXx
}, 0 },
10406 /* VEX_W_0F5C_P_0 */
10407 { "vsubps", { XM
, Vex
, EXx
}, 0 },
10410 /* VEX_W_0F5C_P_1 */
10411 { "vsubss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10414 /* VEX_W_0F5C_P_2 */
10415 { "vsubpd", { XM
, Vex
, EXx
}, 0 },
10418 /* VEX_W_0F5C_P_3 */
10419 { "vsubsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10422 /* VEX_W_0F5D_P_0 */
10423 { "vminps", { XM
, Vex
, EXx
}, 0 },
10426 /* VEX_W_0F5D_P_1 */
10427 { "vminss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10430 /* VEX_W_0F5D_P_2 */
10431 { "vminpd", { XM
, Vex
, EXx
}, 0 },
10434 /* VEX_W_0F5D_P_3 */
10435 { "vminsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10438 /* VEX_W_0F5E_P_0 */
10439 { "vdivps", { XM
, Vex
, EXx
}, 0 },
10442 /* VEX_W_0F5E_P_1 */
10443 { "vdivss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10446 /* VEX_W_0F5E_P_2 */
10447 { "vdivpd", { XM
, Vex
, EXx
}, 0 },
10450 /* VEX_W_0F5E_P_3 */
10451 { "vdivsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10454 /* VEX_W_0F5F_P_0 */
10455 { "vmaxps", { XM
, Vex
, EXx
}, 0 },
10458 /* VEX_W_0F5F_P_1 */
10459 { "vmaxss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10462 /* VEX_W_0F5F_P_2 */
10463 { "vmaxpd", { XM
, Vex
, EXx
}, 0 },
10466 /* VEX_W_0F5F_P_3 */
10467 { "vmaxsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10470 /* VEX_W_0F60_P_2 */
10471 { "vpunpcklbw", { XM
, Vex
, EXx
}, 0 },
10474 /* VEX_W_0F61_P_2 */
10475 { "vpunpcklwd", { XM
, Vex
, EXx
}, 0 },
10478 /* VEX_W_0F62_P_2 */
10479 { "vpunpckldq", { XM
, Vex
, EXx
}, 0 },
10482 /* VEX_W_0F63_P_2 */
10483 { "vpacksswb", { XM
, Vex
, EXx
}, 0 },
10486 /* VEX_W_0F64_P_2 */
10487 { "vpcmpgtb", { XM
, Vex
, EXx
}, 0 },
10490 /* VEX_W_0F65_P_2 */
10491 { "vpcmpgtw", { XM
, Vex
, EXx
}, 0 },
10494 /* VEX_W_0F66_P_2 */
10495 { "vpcmpgtd", { XM
, Vex
, EXx
}, 0 },
10498 /* VEX_W_0F67_P_2 */
10499 { "vpackuswb", { XM
, Vex
, EXx
}, 0 },
10502 /* VEX_W_0F68_P_2 */
10503 { "vpunpckhbw", { XM
, Vex
, EXx
}, 0 },
10506 /* VEX_W_0F69_P_2 */
10507 { "vpunpckhwd", { XM
, Vex
, EXx
}, 0 },
10510 /* VEX_W_0F6A_P_2 */
10511 { "vpunpckhdq", { XM
, Vex
, EXx
}, 0 },
10514 /* VEX_W_0F6B_P_2 */
10515 { "vpackssdw", { XM
, Vex
, EXx
}, 0 },
10518 /* VEX_W_0F6C_P_2 */
10519 { "vpunpcklqdq", { XM
, Vex
, EXx
}, 0 },
10522 /* VEX_W_0F6D_P_2 */
10523 { "vpunpckhqdq", { XM
, Vex
, EXx
}, 0 },
10526 /* VEX_W_0F6F_P_1 */
10527 { "vmovdqu", { XM
, EXx
}, 0 },
10530 /* VEX_W_0F6F_P_2 */
10531 { "vmovdqa", { XM
, EXx
}, 0 },
10534 /* VEX_W_0F70_P_1 */
10535 { "vpshufhw", { XM
, EXx
, Ib
}, 0 },
10538 /* VEX_W_0F70_P_2 */
10539 { "vpshufd", { XM
, EXx
, Ib
}, 0 },
10542 /* VEX_W_0F70_P_3 */
10543 { "vpshuflw", { XM
, EXx
, Ib
}, 0 },
10546 /* VEX_W_0F71_R_2_P_2 */
10547 { "vpsrlw", { Vex
, XS
, Ib
}, 0 },
10550 /* VEX_W_0F71_R_4_P_2 */
10551 { "vpsraw", { Vex
, XS
, Ib
}, 0 },
10554 /* VEX_W_0F71_R_6_P_2 */
10555 { "vpsllw", { Vex
, XS
, Ib
}, 0 },
10558 /* VEX_W_0F72_R_2_P_2 */
10559 { "vpsrld", { Vex
, XS
, Ib
}, 0 },
10562 /* VEX_W_0F72_R_4_P_2 */
10563 { "vpsrad", { Vex
, XS
, Ib
}, 0 },
10566 /* VEX_W_0F72_R_6_P_2 */
10567 { "vpslld", { Vex
, XS
, Ib
}, 0 },
10570 /* VEX_W_0F73_R_2_P_2 */
10571 { "vpsrlq", { Vex
, XS
, Ib
}, 0 },
10574 /* VEX_W_0F73_R_3_P_2 */
10575 { "vpsrldq", { Vex
, XS
, Ib
}, 0 },
10578 /* VEX_W_0F73_R_6_P_2 */
10579 { "vpsllq", { Vex
, XS
, Ib
}, 0 },
10582 /* VEX_W_0F73_R_7_P_2 */
10583 { "vpslldq", { Vex
, XS
, Ib
}, 0 },
10586 /* VEX_W_0F74_P_2 */
10587 { "vpcmpeqb", { XM
, Vex
, EXx
}, 0 },
10590 /* VEX_W_0F75_P_2 */
10591 { "vpcmpeqw", { XM
, Vex
, EXx
}, 0 },
10594 /* VEX_W_0F76_P_2 */
10595 { "vpcmpeqd", { XM
, Vex
, EXx
}, 0 },
10598 /* VEX_W_0F77_P_0 */
10599 { "", { VZERO
}, 0 },
10602 /* VEX_W_0F7C_P_2 */
10603 { "vhaddpd", { XM
, Vex
, EXx
}, 0 },
10606 /* VEX_W_0F7C_P_3 */
10607 { "vhaddps", { XM
, Vex
, EXx
}, 0 },
10610 /* VEX_W_0F7D_P_2 */
10611 { "vhsubpd", { XM
, Vex
, EXx
}, 0 },
10614 /* VEX_W_0F7D_P_3 */
10615 { "vhsubps", { XM
, Vex
, EXx
}, 0 },
10618 /* VEX_W_0F7E_P_1 */
10619 { "vmovq", { XMScalar
, EXqScalar
}, 0 },
10622 /* VEX_W_0F7F_P_1 */
10623 { "vmovdqu", { EXxS
, XM
}, 0 },
10626 /* VEX_W_0F7F_P_2 */
10627 { "vmovdqa", { EXxS
, XM
}, 0 },
10630 /* VEX_W_0F90_P_0_LEN_0 */
10631 { "kmovw", { MaskG
, MaskE
}, 0 },
10632 { "kmovq", { MaskG
, MaskE
}, 0 },
10635 /* VEX_W_0F90_P_2_LEN_0 */
10636 { "kmovb", { MaskG
, MaskBDE
}, 0 },
10637 { "kmovd", { MaskG
, MaskBDE
}, 0 },
10640 /* VEX_W_0F91_P_0_LEN_0 */
10641 { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0
) },
10642 { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0
) },
10645 /* VEX_W_0F91_P_2_LEN_0 */
10646 { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0
) },
10647 { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0
) },
10650 /* VEX_W_0F92_P_0_LEN_0 */
10651 { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0
) },
10654 /* VEX_W_0F92_P_2_LEN_0 */
10655 { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0
) },
10658 /* VEX_W_0F92_P_3_LEN_0 */
10659 { MOD_TABLE (MOD_VEX_W_0_0F92_P_3_LEN_0
) },
10660 { MOD_TABLE (MOD_VEX_W_1_0F92_P_3_LEN_0
) },
10663 /* VEX_W_0F93_P_0_LEN_0 */
10664 { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0
) },
10667 /* VEX_W_0F93_P_2_LEN_0 */
10668 { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0
) },
10671 /* VEX_W_0F93_P_3_LEN_0 */
10672 { MOD_TABLE (MOD_VEX_W_0_0F93_P_3_LEN_0
) },
10673 { MOD_TABLE (MOD_VEX_W_1_0F93_P_3_LEN_0
) },
10676 /* VEX_W_0F98_P_0_LEN_0 */
10677 { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0
) },
10678 { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0
) },
10681 /* VEX_W_0F98_P_2_LEN_0 */
10682 { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0
) },
10683 { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0
) },
10686 /* VEX_W_0F99_P_0_LEN_0 */
10687 { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0
) },
10688 { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0
) },
10691 /* VEX_W_0F99_P_2_LEN_0 */
10692 { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0
) },
10693 { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0
) },
10696 /* VEX_W_0FAE_R_2_M_0 */
10697 { "vldmxcsr", { Md
}, 0 },
10700 /* VEX_W_0FAE_R_3_M_0 */
10701 { "vstmxcsr", { Md
}, 0 },
10704 /* VEX_W_0FC2_P_0 */
10705 { "vcmpps", { XM
, Vex
, EXx
, VCMP
}, 0 },
10708 /* VEX_W_0FC2_P_1 */
10709 { "vcmpss", { XMScalar
, VexScalar
, EXdScalar
, VCMP
}, 0 },
10712 /* VEX_W_0FC2_P_2 */
10713 { "vcmppd", { XM
, Vex
, EXx
, VCMP
}, 0 },
10716 /* VEX_W_0FC2_P_3 */
10717 { "vcmpsd", { XMScalar
, VexScalar
, EXqScalar
, VCMP
}, 0 },
10720 /* VEX_W_0FC4_P_2 */
10721 { "vpinsrw", { XM
, Vex128
, Edqw
, Ib
}, 0 },
10724 /* VEX_W_0FC5_P_2 */
10725 { "vpextrw", { Gdq
, XS
, Ib
}, 0 },
10728 /* VEX_W_0FD0_P_2 */
10729 { "vaddsubpd", { XM
, Vex
, EXx
}, 0 },
10732 /* VEX_W_0FD0_P_3 */
10733 { "vaddsubps", { XM
, Vex
, EXx
}, 0 },
10736 /* VEX_W_0FD1_P_2 */
10737 { "vpsrlw", { XM
, Vex
, EXxmm
}, 0 },
10740 /* VEX_W_0FD2_P_2 */
10741 { "vpsrld", { XM
, Vex
, EXxmm
}, 0 },
10744 /* VEX_W_0FD3_P_2 */
10745 { "vpsrlq", { XM
, Vex
, EXxmm
}, 0 },
10748 /* VEX_W_0FD4_P_2 */
10749 { "vpaddq", { XM
, Vex
, EXx
}, 0 },
10752 /* VEX_W_0FD5_P_2 */
10753 { "vpmullw", { XM
, Vex
, EXx
}, 0 },
10756 /* VEX_W_0FD6_P_2 */
10757 { "vmovq", { EXqScalarS
, XMScalar
}, 0 },
10760 /* VEX_W_0FD7_P_2_M_1 */
10761 { "vpmovmskb", { Gdq
, XS
}, 0 },
10764 /* VEX_W_0FD8_P_2 */
10765 { "vpsubusb", { XM
, Vex
, EXx
}, 0 },
10768 /* VEX_W_0FD9_P_2 */
10769 { "vpsubusw", { XM
, Vex
, EXx
}, 0 },
10772 /* VEX_W_0FDA_P_2 */
10773 { "vpminub", { XM
, Vex
, EXx
}, 0 },
10776 /* VEX_W_0FDB_P_2 */
10777 { "vpand", { XM
, Vex
, EXx
}, 0 },
10780 /* VEX_W_0FDC_P_2 */
10781 { "vpaddusb", { XM
, Vex
, EXx
}, 0 },
10784 /* VEX_W_0FDD_P_2 */
10785 { "vpaddusw", { XM
, Vex
, EXx
}, 0 },
10788 /* VEX_W_0FDE_P_2 */
10789 { "vpmaxub", { XM
, Vex
, EXx
}, 0 },
10792 /* VEX_W_0FDF_P_2 */
10793 { "vpandn", { XM
, Vex
, EXx
}, 0 },
10796 /* VEX_W_0FE0_P_2 */
10797 { "vpavgb", { XM
, Vex
, EXx
}, 0 },
10800 /* VEX_W_0FE1_P_2 */
10801 { "vpsraw", { XM
, Vex
, EXxmm
}, 0 },
10804 /* VEX_W_0FE2_P_2 */
10805 { "vpsrad", { XM
, Vex
, EXxmm
}, 0 },
10808 /* VEX_W_0FE3_P_2 */
10809 { "vpavgw", { XM
, Vex
, EXx
}, 0 },
10812 /* VEX_W_0FE4_P_2 */
10813 { "vpmulhuw", { XM
, Vex
, EXx
}, 0 },
10816 /* VEX_W_0FE5_P_2 */
10817 { "vpmulhw", { XM
, Vex
, EXx
}, 0 },
10820 /* VEX_W_0FE6_P_1 */
10821 { "vcvtdq2pd", { XM
, EXxmmq
}, 0 },
10824 /* VEX_W_0FE6_P_2 */
10825 { "vcvttpd2dq%XY", { XMM
, EXx
}, 0 },
10828 /* VEX_W_0FE6_P_3 */
10829 { "vcvtpd2dq%XY", { XMM
, EXx
}, 0 },
10832 /* VEX_W_0FE7_P_2_M_0 */
10833 { "vmovntdq", { Mx
, XM
}, 0 },
10836 /* VEX_W_0FE8_P_2 */
10837 { "vpsubsb", { XM
, Vex
, EXx
}, 0 },
10840 /* VEX_W_0FE9_P_2 */
10841 { "vpsubsw", { XM
, Vex
, EXx
}, 0 },
10844 /* VEX_W_0FEA_P_2 */
10845 { "vpminsw", { XM
, Vex
, EXx
}, 0 },
10848 /* VEX_W_0FEB_P_2 */
10849 { "vpor", { XM
, Vex
, EXx
}, 0 },
10852 /* VEX_W_0FEC_P_2 */
10853 { "vpaddsb", { XM
, Vex
, EXx
}, 0 },
10856 /* VEX_W_0FED_P_2 */
10857 { "vpaddsw", { XM
, Vex
, EXx
}, 0 },
10860 /* VEX_W_0FEE_P_2 */
10861 { "vpmaxsw", { XM
, Vex
, EXx
}, 0 },
10864 /* VEX_W_0FEF_P_2 */
10865 { "vpxor", { XM
, Vex
, EXx
}, 0 },
10868 /* VEX_W_0FF0_P_3_M_0 */
10869 { "vlddqu", { XM
, M
}, 0 },
10872 /* VEX_W_0FF1_P_2 */
10873 { "vpsllw", { XM
, Vex
, EXxmm
}, 0 },
10876 /* VEX_W_0FF2_P_2 */
10877 { "vpslld", { XM
, Vex
, EXxmm
}, 0 },
10880 /* VEX_W_0FF3_P_2 */
10881 { "vpsllq", { XM
, Vex
, EXxmm
}, 0 },
10884 /* VEX_W_0FF4_P_2 */
10885 { "vpmuludq", { XM
, Vex
, EXx
}, 0 },
10888 /* VEX_W_0FF5_P_2 */
10889 { "vpmaddwd", { XM
, Vex
, EXx
}, 0 },
10892 /* VEX_W_0FF6_P_2 */
10893 { "vpsadbw", { XM
, Vex
, EXx
}, 0 },
10896 /* VEX_W_0FF7_P_2 */
10897 { "vmaskmovdqu", { XM
, XS
}, 0 },
10900 /* VEX_W_0FF8_P_2 */
10901 { "vpsubb", { XM
, Vex
, EXx
}, 0 },
10904 /* VEX_W_0FF9_P_2 */
10905 { "vpsubw", { XM
, Vex
, EXx
}, 0 },
10908 /* VEX_W_0FFA_P_2 */
10909 { "vpsubd", { XM
, Vex
, EXx
}, 0 },
10912 /* VEX_W_0FFB_P_2 */
10913 { "vpsubq", { XM
, Vex
, EXx
}, 0 },
10916 /* VEX_W_0FFC_P_2 */
10917 { "vpaddb", { XM
, Vex
, EXx
}, 0 },
10920 /* VEX_W_0FFD_P_2 */
10921 { "vpaddw", { XM
, Vex
, EXx
}, 0 },
10924 /* VEX_W_0FFE_P_2 */
10925 { "vpaddd", { XM
, Vex
, EXx
}, 0 },
10928 /* VEX_W_0F3800_P_2 */
10929 { "vpshufb", { XM
, Vex
, EXx
}, 0 },
10932 /* VEX_W_0F3801_P_2 */
10933 { "vphaddw", { XM
, Vex
, EXx
}, 0 },
10936 /* VEX_W_0F3802_P_2 */
10937 { "vphaddd", { XM
, Vex
, EXx
}, 0 },
10940 /* VEX_W_0F3803_P_2 */
10941 { "vphaddsw", { XM
, Vex
, EXx
}, 0 },
10944 /* VEX_W_0F3804_P_2 */
10945 { "vpmaddubsw", { XM
, Vex
, EXx
}, 0 },
10948 /* VEX_W_0F3805_P_2 */
10949 { "vphsubw", { XM
, Vex
, EXx
}, 0 },
10952 /* VEX_W_0F3806_P_2 */
10953 { "vphsubd", { XM
, Vex
, EXx
}, 0 },
10956 /* VEX_W_0F3807_P_2 */
10957 { "vphsubsw", { XM
, Vex
, EXx
}, 0 },
10960 /* VEX_W_0F3808_P_2 */
10961 { "vpsignb", { XM
, Vex
, EXx
}, 0 },
10964 /* VEX_W_0F3809_P_2 */
10965 { "vpsignw", { XM
, Vex
, EXx
}, 0 },
10968 /* VEX_W_0F380A_P_2 */
10969 { "vpsignd", { XM
, Vex
, EXx
}, 0 },
10972 /* VEX_W_0F380B_P_2 */
10973 { "vpmulhrsw", { XM
, Vex
, EXx
}, 0 },
10976 /* VEX_W_0F380C_P_2 */
10977 { "vpermilps", { XM
, Vex
, EXx
}, 0 },
10980 /* VEX_W_0F380D_P_2 */
10981 { "vpermilpd", { XM
, Vex
, EXx
}, 0 },
10984 /* VEX_W_0F380E_P_2 */
10985 { "vtestps", { XM
, EXx
}, 0 },
10988 /* VEX_W_0F380F_P_2 */
10989 { "vtestpd", { XM
, EXx
}, 0 },
10992 /* VEX_W_0F3816_P_2 */
10993 { "vpermps", { XM
, Vex
, EXx
}, 0 },
10996 /* VEX_W_0F3817_P_2 */
10997 { "vptest", { XM
, EXx
}, 0 },
11000 /* VEX_W_0F3818_P_2 */
11001 { "vbroadcastss", { XM
, EXxmm_md
}, 0 },
11004 /* VEX_W_0F3819_P_2 */
11005 { "vbroadcastsd", { XM
, EXxmm_mq
}, 0 },
11008 /* VEX_W_0F381A_P_2_M_0 */
11009 { "vbroadcastf128", { XM
, Mxmm
}, 0 },
11012 /* VEX_W_0F381C_P_2 */
11013 { "vpabsb", { XM
, EXx
}, 0 },
11016 /* VEX_W_0F381D_P_2 */
11017 { "vpabsw", { XM
, EXx
}, 0 },
11020 /* VEX_W_0F381E_P_2 */
11021 { "vpabsd", { XM
, EXx
}, 0 },
11024 /* VEX_W_0F3820_P_2 */
11025 { "vpmovsxbw", { XM
, EXxmmq
}, 0 },
11028 /* VEX_W_0F3821_P_2 */
11029 { "vpmovsxbd", { XM
, EXxmmqd
}, 0 },
11032 /* VEX_W_0F3822_P_2 */
11033 { "vpmovsxbq", { XM
, EXxmmdw
}, 0 },
11036 /* VEX_W_0F3823_P_2 */
11037 { "vpmovsxwd", { XM
, EXxmmq
}, 0 },
11040 /* VEX_W_0F3824_P_2 */
11041 { "vpmovsxwq", { XM
, EXxmmqd
}, 0 },
11044 /* VEX_W_0F3825_P_2 */
11045 { "vpmovsxdq", { XM
, EXxmmq
}, 0 },
11048 /* VEX_W_0F3828_P_2 */
11049 { "vpmuldq", { XM
, Vex
, EXx
}, 0 },
11052 /* VEX_W_0F3829_P_2 */
11053 { "vpcmpeqq", { XM
, Vex
, EXx
}, 0 },
11056 /* VEX_W_0F382A_P_2_M_0 */
11057 { "vmovntdqa", { XM
, Mx
}, 0 },
11060 /* VEX_W_0F382B_P_2 */
11061 { "vpackusdw", { XM
, Vex
, EXx
}, 0 },
11064 /* VEX_W_0F382C_P_2_M_0 */
11065 { "vmaskmovps", { XM
, Vex
, Mx
}, 0 },
11068 /* VEX_W_0F382D_P_2_M_0 */
11069 { "vmaskmovpd", { XM
, Vex
, Mx
}, 0 },
11072 /* VEX_W_0F382E_P_2_M_0 */
11073 { "vmaskmovps", { Mx
, Vex
, XM
}, 0 },
11076 /* VEX_W_0F382F_P_2_M_0 */
11077 { "vmaskmovpd", { Mx
, Vex
, XM
}, 0 },
11080 /* VEX_W_0F3830_P_2 */
11081 { "vpmovzxbw", { XM
, EXxmmq
}, 0 },
11084 /* VEX_W_0F3831_P_2 */
11085 { "vpmovzxbd", { XM
, EXxmmqd
}, 0 },
11088 /* VEX_W_0F3832_P_2 */
11089 { "vpmovzxbq", { XM
, EXxmmdw
}, 0 },
11092 /* VEX_W_0F3833_P_2 */
11093 { "vpmovzxwd", { XM
, EXxmmq
}, 0 },
11096 /* VEX_W_0F3834_P_2 */
11097 { "vpmovzxwq", { XM
, EXxmmqd
}, 0 },
11100 /* VEX_W_0F3835_P_2 */
11101 { "vpmovzxdq", { XM
, EXxmmq
}, 0 },
11104 /* VEX_W_0F3836_P_2 */
11105 { "vpermd", { XM
, Vex
, EXx
}, 0 },
11108 /* VEX_W_0F3837_P_2 */
11109 { "vpcmpgtq", { XM
, Vex
, EXx
}, 0 },
11112 /* VEX_W_0F3838_P_2 */
11113 { "vpminsb", { XM
, Vex
, EXx
}, 0 },
11116 /* VEX_W_0F3839_P_2 */
11117 { "vpminsd", { XM
, Vex
, EXx
}, 0 },
11120 /* VEX_W_0F383A_P_2 */
11121 { "vpminuw", { XM
, Vex
, EXx
}, 0 },
11124 /* VEX_W_0F383B_P_2 */
11125 { "vpminud", { XM
, Vex
, EXx
}, 0 },
11128 /* VEX_W_0F383C_P_2 */
11129 { "vpmaxsb", { XM
, Vex
, EXx
}, 0 },
11132 /* VEX_W_0F383D_P_2 */
11133 { "vpmaxsd", { XM
, Vex
, EXx
}, 0 },
11136 /* VEX_W_0F383E_P_2 */
11137 { "vpmaxuw", { XM
, Vex
, EXx
}, 0 },
11140 /* VEX_W_0F383F_P_2 */
11141 { "vpmaxud", { XM
, Vex
, EXx
}, 0 },
11144 /* VEX_W_0F3840_P_2 */
11145 { "vpmulld", { XM
, Vex
, EXx
}, 0 },
11148 /* VEX_W_0F3841_P_2 */
11149 { "vphminposuw", { XM
, EXx
}, 0 },
11152 /* VEX_W_0F3846_P_2 */
11153 { "vpsravd", { XM
, Vex
, EXx
}, 0 },
11156 /* VEX_W_0F3858_P_2 */
11157 { "vpbroadcastd", { XM
, EXxmm_md
}, 0 },
11160 /* VEX_W_0F3859_P_2 */
11161 { "vpbroadcastq", { XM
, EXxmm_mq
}, 0 },
11164 /* VEX_W_0F385A_P_2_M_0 */
11165 { "vbroadcasti128", { XM
, Mxmm
}, 0 },
11168 /* VEX_W_0F3878_P_2 */
11169 { "vpbroadcastb", { XM
, EXxmm_mb
}, 0 },
11172 /* VEX_W_0F3879_P_2 */
11173 { "vpbroadcastw", { XM
, EXxmm_mw
}, 0 },
11176 /* VEX_W_0F38DB_P_2 */
11177 { "vaesimc", { XM
, EXx
}, 0 },
11180 /* VEX_W_0F38DC_P_2 */
11181 { "vaesenc", { XM
, Vex128
, EXx
}, 0 },
11184 /* VEX_W_0F38DD_P_2 */
11185 { "vaesenclast", { XM
, Vex128
, EXx
}, 0 },
11188 /* VEX_W_0F38DE_P_2 */
11189 { "vaesdec", { XM
, Vex128
, EXx
}, 0 },
11192 /* VEX_W_0F38DF_P_2 */
11193 { "vaesdeclast", { XM
, Vex128
, EXx
}, 0 },
11196 /* VEX_W_0F3A00_P_2 */
11198 { "vpermq", { XM
, EXx
, Ib
}, 0 },
11201 /* VEX_W_0F3A01_P_2 */
11203 { "vpermpd", { XM
, EXx
, Ib
}, 0 },
11206 /* VEX_W_0F3A02_P_2 */
11207 { "vpblendd", { XM
, Vex
, EXx
, Ib
}, 0 },
11210 /* VEX_W_0F3A04_P_2 */
11211 { "vpermilps", { XM
, EXx
, Ib
}, 0 },
11214 /* VEX_W_0F3A05_P_2 */
11215 { "vpermilpd", { XM
, EXx
, Ib
}, 0 },
11218 /* VEX_W_0F3A06_P_2 */
11219 { "vperm2f128", { XM
, Vex256
, EXx
, Ib
}, 0 },
11222 /* VEX_W_0F3A08_P_2 */
11223 { "vroundps", { XM
, EXx
, Ib
}, 0 },
11226 /* VEX_W_0F3A09_P_2 */
11227 { "vroundpd", { XM
, EXx
, Ib
}, 0 },
11230 /* VEX_W_0F3A0A_P_2 */
11231 { "vroundss", { XMScalar
, VexScalar
, EXdScalar
, Ib
}, 0 },
11234 /* VEX_W_0F3A0B_P_2 */
11235 { "vroundsd", { XMScalar
, VexScalar
, EXqScalar
, Ib
}, 0 },
11238 /* VEX_W_0F3A0C_P_2 */
11239 { "vblendps", { XM
, Vex
, EXx
, Ib
}, 0 },
11242 /* VEX_W_0F3A0D_P_2 */
11243 { "vblendpd", { XM
, Vex
, EXx
, Ib
}, 0 },
11246 /* VEX_W_0F3A0E_P_2 */
11247 { "vpblendw", { XM
, Vex
, EXx
, Ib
}, 0 },
11250 /* VEX_W_0F3A0F_P_2 */
11251 { "vpalignr", { XM
, Vex
, EXx
, Ib
}, 0 },
11254 /* VEX_W_0F3A14_P_2 */
11255 { "vpextrb", { Edqb
, XM
, Ib
}, 0 },
11258 /* VEX_W_0F3A15_P_2 */
11259 { "vpextrw", { Edqw
, XM
, Ib
}, 0 },
11262 /* VEX_W_0F3A18_P_2 */
11263 { "vinsertf128", { XM
, Vex256
, EXxmm
, Ib
}, 0 },
11266 /* VEX_W_0F3A19_P_2 */
11267 { "vextractf128", { EXxmm
, XM
, Ib
}, 0 },
11270 /* VEX_W_0F3A20_P_2 */
11271 { "vpinsrb", { XM
, Vex128
, Edqb
, Ib
}, 0 },
11274 /* VEX_W_0F3A21_P_2 */
11275 { "vinsertps", { XM
, Vex128
, EXd
, Ib
}, 0 },
11278 /* VEX_W_0F3A30_P_2_LEN_0 */
11279 { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0
) },
11280 { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0
) },
11283 /* VEX_W_0F3A31_P_2_LEN_0 */
11284 { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0
) },
11285 { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0
) },
11288 /* VEX_W_0F3A32_P_2_LEN_0 */
11289 { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0
) },
11290 { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0
) },
11293 /* VEX_W_0F3A33_P_2_LEN_0 */
11294 { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0
) },
11295 { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0
) },
11298 /* VEX_W_0F3A38_P_2 */
11299 { "vinserti128", { XM
, Vex256
, EXxmm
, Ib
}, 0 },
11302 /* VEX_W_0F3A39_P_2 */
11303 { "vextracti128", { EXxmm
, XM
, Ib
}, 0 },
11306 /* VEX_W_0F3A40_P_2 */
11307 { "vdpps", { XM
, Vex
, EXx
, Ib
}, 0 },
11310 /* VEX_W_0F3A41_P_2 */
11311 { "vdppd", { XM
, Vex128
, EXx
, Ib
}, 0 },
11314 /* VEX_W_0F3A42_P_2 */
11315 { "vmpsadbw", { XM
, Vex
, EXx
, Ib
}, 0 },
11318 /* VEX_W_0F3A44_P_2 */
11319 { "vpclmulqdq", { XM
, Vex128
, EXx
, PCLMUL
}, 0 },
11322 /* VEX_W_0F3A46_P_2 */
11323 { "vperm2i128", { XM
, Vex256
, EXx
, Ib
}, 0 },
11326 /* VEX_W_0F3A48_P_2 */
11327 { "vpermil2ps", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
11328 { "vpermil2ps", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
11331 /* VEX_W_0F3A49_P_2 */
11332 { "vpermil2pd", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
11333 { "vpermil2pd", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
11336 /* VEX_W_0F3A4A_P_2 */
11337 { "vblendvps", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
11340 /* VEX_W_0F3A4B_P_2 */
11341 { "vblendvpd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
11344 /* VEX_W_0F3A4C_P_2 */
11345 { "vpblendvb", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
11348 /* VEX_W_0F3A62_P_2 */
11349 { "vpcmpistrm", { XM
, EXx
, Ib
}, 0 },
11352 /* VEX_W_0F3A63_P_2 */
11353 { "vpcmpistri", { XM
, EXx
, Ib
}, 0 },
11356 /* VEX_W_0F3ADF_P_2 */
11357 { "vaeskeygenassist", { XM
, EXx
, Ib
}, 0 },
11359 #define NEED_VEX_W_TABLE
11360 #include "i386-dis-evex.h"
11361 #undef NEED_VEX_W_TABLE
11364 static const struct dis386 mod_table
[][2] = {
11367 { "leaS", { Gv
, M
}, 0 },
11372 { RM_TABLE (RM_C6_REG_7
) },
11377 { RM_TABLE (RM_C7_REG_7
) },
11381 { "Jcall^", { indirEp
}, 0 },
11385 { "Jjmp^", { indirEp
}, 0 },
11388 /* MOD_0F01_REG_0 */
11389 { X86_64_TABLE (X86_64_0F01_REG_0
) },
11390 { RM_TABLE (RM_0F01_REG_0
) },
11393 /* MOD_0F01_REG_1 */
11394 { X86_64_TABLE (X86_64_0F01_REG_1
) },
11395 { RM_TABLE (RM_0F01_REG_1
) },
11398 /* MOD_0F01_REG_2 */
11399 { X86_64_TABLE (X86_64_0F01_REG_2
) },
11400 { RM_TABLE (RM_0F01_REG_2
) },
11403 /* MOD_0F01_REG_3 */
11404 { X86_64_TABLE (X86_64_0F01_REG_3
) },
11405 { RM_TABLE (RM_0F01_REG_3
) },
11408 /* MOD_0F01_REG_5 */
11410 { RM_TABLE (RM_0F01_REG_5
) },
11413 /* MOD_0F01_REG_7 */
11414 { "invlpg", { Mb
}, 0 },
11415 { RM_TABLE (RM_0F01_REG_7
) },
11418 /* MOD_0F12_PREFIX_0 */
11419 { "movlps", { XM
, EXq
}, PREFIX_OPCODE
},
11420 { "movhlps", { XM
, EXq
}, PREFIX_OPCODE
},
11424 { "movlpX", { EXq
, XM
}, PREFIX_OPCODE
},
11427 /* MOD_0F16_PREFIX_0 */
11428 { "movhps", { XM
, EXq
}, 0 },
11429 { "movlhps", { XM
, EXq
}, 0 },
11433 { "movhpX", { EXq
, XM
}, PREFIX_OPCODE
},
11436 /* MOD_0F18_REG_0 */
11437 { "prefetchnta", { Mb
}, 0 },
11440 /* MOD_0F18_REG_1 */
11441 { "prefetcht0", { Mb
}, 0 },
11444 /* MOD_0F18_REG_2 */
11445 { "prefetcht1", { Mb
}, 0 },
11448 /* MOD_0F18_REG_3 */
11449 { "prefetcht2", { Mb
}, 0 },
11452 /* MOD_0F18_REG_4 */
11453 { "nop/reserved", { Mb
}, 0 },
11456 /* MOD_0F18_REG_5 */
11457 { "nop/reserved", { Mb
}, 0 },
11460 /* MOD_0F18_REG_6 */
11461 { "nop/reserved", { Mb
}, 0 },
11464 /* MOD_0F18_REG_7 */
11465 { "nop/reserved", { Mb
}, 0 },
11468 /* MOD_0F1A_PREFIX_0 */
11469 { "bndldx", { Gbnd
, Ev_bnd
}, 0 },
11470 { "nopQ", { Ev
}, 0 },
11473 /* MOD_0F1B_PREFIX_0 */
11474 { "bndstx", { Ev_bnd
, Gbnd
}, 0 },
11475 { "nopQ", { Ev
}, 0 },
11478 /* MOD_0F1B_PREFIX_1 */
11479 { "bndmk", { Gbnd
, Ev_bnd
}, 0 },
11480 { "nopQ", { Ev
}, 0 },
11485 { "movL", { Rd
, Td
}, 0 },
11490 { "movL", { Td
, Rd
}, 0 },
11493 /* MOD_0F2B_PREFIX_0 */
11494 {"movntps", { Mx
, XM
}, PREFIX_OPCODE
},
11497 /* MOD_0F2B_PREFIX_1 */
11498 {"movntss", { Md
, XM
}, PREFIX_OPCODE
},
11501 /* MOD_0F2B_PREFIX_2 */
11502 {"movntpd", { Mx
, XM
}, PREFIX_OPCODE
},
11505 /* MOD_0F2B_PREFIX_3 */
11506 {"movntsd", { Mq
, XM
}, PREFIX_OPCODE
},
11511 { "movmskpX", { Gdq
, XS
}, PREFIX_OPCODE
},
11514 /* MOD_0F71_REG_2 */
11516 { "psrlw", { MS
, Ib
}, 0 },
11519 /* MOD_0F71_REG_4 */
11521 { "psraw", { MS
, Ib
}, 0 },
11524 /* MOD_0F71_REG_6 */
11526 { "psllw", { MS
, Ib
}, 0 },
11529 /* MOD_0F72_REG_2 */
11531 { "psrld", { MS
, Ib
}, 0 },
11534 /* MOD_0F72_REG_4 */
11536 { "psrad", { MS
, Ib
}, 0 },
11539 /* MOD_0F72_REG_6 */
11541 { "pslld", { MS
, Ib
}, 0 },
11544 /* MOD_0F73_REG_2 */
11546 { "psrlq", { MS
, Ib
}, 0 },
11549 /* MOD_0F73_REG_3 */
11551 { PREFIX_TABLE (PREFIX_0F73_REG_3
) },
11554 /* MOD_0F73_REG_6 */
11556 { "psllq", { MS
, Ib
}, 0 },
11559 /* MOD_0F73_REG_7 */
11561 { PREFIX_TABLE (PREFIX_0F73_REG_7
) },
11564 /* MOD_0FAE_REG_0 */
11565 { "fxsave", { FXSAVE
}, 0 },
11566 { PREFIX_TABLE (PREFIX_0FAE_REG_0
) },
11569 /* MOD_0FAE_REG_1 */
11570 { "fxrstor", { FXSAVE
}, 0 },
11571 { PREFIX_TABLE (PREFIX_0FAE_REG_1
) },
11574 /* MOD_0FAE_REG_2 */
11575 { "ldmxcsr", { Md
}, 0 },
11576 { PREFIX_TABLE (PREFIX_0FAE_REG_2
) },
11579 /* MOD_0FAE_REG_3 */
11580 { "stmxcsr", { Md
}, 0 },
11581 { PREFIX_TABLE (PREFIX_0FAE_REG_3
) },
11584 /* MOD_0FAE_REG_4 */
11585 { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_4
) },
11586 { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_4
) },
11589 /* MOD_0FAE_REG_5 */
11590 { "xrstor", { FXSAVE
}, 0 },
11591 { RM_TABLE (RM_0FAE_REG_5
) },
11594 /* MOD_0FAE_REG_6 */
11595 { PREFIX_TABLE (PREFIX_0FAE_REG_6
) },
11596 { RM_TABLE (RM_0FAE_REG_6
) },
11599 /* MOD_0FAE_REG_7 */
11600 { PREFIX_TABLE (PREFIX_0FAE_REG_7
) },
11601 { RM_TABLE (RM_0FAE_REG_7
) },
11605 { "lssS", { Gv
, Mp
}, 0 },
11609 { "lfsS", { Gv
, Mp
}, 0 },
11613 { "lgsS", { Gv
, Mp
}, 0 },
11617 { PREFIX_TABLE (PREFIX_MOD_0_0FC3
) },
11620 /* MOD_0FC7_REG_3 */
11621 { "xrstors", { FXSAVE
}, 0 },
11624 /* MOD_0FC7_REG_4 */
11625 { "xsavec", { FXSAVE
}, 0 },
11628 /* MOD_0FC7_REG_5 */
11629 { "xsaves", { FXSAVE
}, 0 },
11632 /* MOD_0FC7_REG_6 */
11633 { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6
) },
11634 { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6
) }
11637 /* MOD_0FC7_REG_7 */
11638 { "vmptrst", { Mq
}, 0 },
11639 { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7
) }
11644 { "pmovmskb", { Gdq
, MS
}, 0 },
11647 /* MOD_0FE7_PREFIX_2 */
11648 { "movntdq", { Mx
, XM
}, 0 },
11651 /* MOD_0FF0_PREFIX_3 */
11652 { "lddqu", { XM
, M
}, 0 },
11655 /* MOD_0F382A_PREFIX_2 */
11656 { "movntdqa", { XM
, Mx
}, 0 },
11660 { "bound{S|}", { Gv
, Ma
}, 0 },
11661 { EVEX_TABLE (EVEX_0F
) },
11665 { "lesS", { Gv
, Mp
}, 0 },
11666 { VEX_C4_TABLE (VEX_0F
) },
11670 { "ldsS", { Gv
, Mp
}, 0 },
11671 { VEX_C5_TABLE (VEX_0F
) },
11674 /* MOD_VEX_0F12_PREFIX_0 */
11675 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0
) },
11676 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1
) },
11680 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0
) },
11683 /* MOD_VEX_0F16_PREFIX_0 */
11684 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0
) },
11685 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1
) },
11689 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0
) },
11693 { VEX_W_TABLE (VEX_W_0F2B_M_0
) },
11696 /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
11698 { "kandw", { MaskG
, MaskVex
, MaskR
}, 0 },
11701 /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
11703 { "kandq", { MaskG
, MaskVex
, MaskR
}, 0 },
11706 /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
11708 { "kandb", { MaskG
, MaskVex
, MaskR
}, 0 },
11711 /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
11713 { "kandd", { MaskG
, MaskVex
, MaskR
}, 0 },
11716 /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
11718 { "kandnw", { MaskG
, MaskVex
, MaskR
}, 0 },
11721 /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
11723 { "kandnq", { MaskG
, MaskVex
, MaskR
}, 0 },
11726 /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
11728 { "kandnb", { MaskG
, MaskVex
, MaskR
}, 0 },
11731 /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
11733 { "kandnd", { MaskG
, MaskVex
, MaskR
}, 0 },
11736 /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
11738 { "knotw", { MaskG
, MaskR
}, 0 },
11741 /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
11743 { "knotq", { MaskG
, MaskR
}, 0 },
11746 /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
11748 { "knotb", { MaskG
, MaskR
}, 0 },
11751 /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
11753 { "knotd", { MaskG
, MaskR
}, 0 },
11756 /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
11758 { "korw", { MaskG
, MaskVex
, MaskR
}, 0 },
11761 /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
11763 { "korq", { MaskG
, MaskVex
, MaskR
}, 0 },
11766 /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
11768 { "korb", { MaskG
, MaskVex
, MaskR
}, 0 },
11771 /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
11773 { "kord", { MaskG
, MaskVex
, MaskR
}, 0 },
11776 /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
11778 { "kxnorw", { MaskG
, MaskVex
, MaskR
}, 0 },
11781 /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
11783 { "kxnorq", { MaskG
, MaskVex
, MaskR
}, 0 },
11786 /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
11788 { "kxnorb", { MaskG
, MaskVex
, MaskR
}, 0 },
11791 /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
11793 { "kxnord", { MaskG
, MaskVex
, MaskR
}, 0 },
11796 /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
11798 { "kxorw", { MaskG
, MaskVex
, MaskR
}, 0 },
11801 /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
11803 { "kxorq", { MaskG
, MaskVex
, MaskR
}, 0 },
11806 /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
11808 { "kxorb", { MaskG
, MaskVex
, MaskR
}, 0 },
11811 /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
11813 { "kxord", { MaskG
, MaskVex
, MaskR
}, 0 },
11816 /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
11818 { "kaddw", { MaskG
, MaskVex
, MaskR
}, 0 },
11821 /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
11823 { "kaddq", { MaskG
, MaskVex
, MaskR
}, 0 },
11826 /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
11828 { "kaddb", { MaskG
, MaskVex
, MaskR
}, 0 },
11831 /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
11833 { "kaddd", { MaskG
, MaskVex
, MaskR
}, 0 },
11836 /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
11838 { "kunpckwd", { MaskG
, MaskVex
, MaskR
}, 0 },
11841 /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
11843 { "kunpckdq", { MaskG
, MaskVex
, MaskR
}, 0 },
11846 /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
11848 { "kunpckbw", { MaskG
, MaskVex
, MaskR
}, 0 },
11853 { VEX_W_TABLE (VEX_W_0F50_M_0
) },
11856 /* MOD_VEX_0F71_REG_2 */
11858 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2
) },
11861 /* MOD_VEX_0F71_REG_4 */
11863 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4
) },
11866 /* MOD_VEX_0F71_REG_6 */
11868 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6
) },
11871 /* MOD_VEX_0F72_REG_2 */
11873 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2
) },
11876 /* MOD_VEX_0F72_REG_4 */
11878 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4
) },
11881 /* MOD_VEX_0F72_REG_6 */
11883 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6
) },
11886 /* MOD_VEX_0F73_REG_2 */
11888 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2
) },
11891 /* MOD_VEX_0F73_REG_3 */
11893 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3
) },
11896 /* MOD_VEX_0F73_REG_6 */
11898 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6
) },
11901 /* MOD_VEX_0F73_REG_7 */
11903 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7
) },
11906 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
11907 { "kmovw", { Ew
, MaskG
}, 0 },
11911 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
11912 { "kmovq", { Eq
, MaskG
}, 0 },
11916 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
11917 { "kmovb", { Eb
, MaskG
}, 0 },
11921 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
11922 { "kmovd", { Ed
, MaskG
}, 0 },
11926 /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
11928 { "kmovw", { MaskG
, Rdq
}, 0 },
11931 /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
11933 { "kmovb", { MaskG
, Rdq
}, 0 },
11936 /* MOD_VEX_W_0_0F92_P_3_LEN_0 */
11938 { "kmovd", { MaskG
, Rdq
}, 0 },
11941 /* MOD_VEX_W_1_0F92_P_3_LEN_0 */
11943 { "kmovq", { MaskG
, Rdq
}, 0 },
11946 /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
11948 { "kmovw", { Gdq
, MaskR
}, 0 },
11951 /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
11953 { "kmovb", { Gdq
, MaskR
}, 0 },
11956 /* MOD_VEX_W_0_0F93_P_3_LEN_0 */
11958 { "kmovd", { Gdq
, MaskR
}, 0 },
11961 /* MOD_VEX_W_1_0F93_P_3_LEN_0 */
11963 { "kmovq", { Gdq
, MaskR
}, 0 },
11966 /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
11968 { "kortestw", { MaskG
, MaskR
}, 0 },
11971 /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
11973 { "kortestq", { MaskG
, MaskR
}, 0 },
11976 /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
11978 { "kortestb", { MaskG
, MaskR
}, 0 },
11981 /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
11983 { "kortestd", { MaskG
, MaskR
}, 0 },
11986 /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
11988 { "ktestw", { MaskG
, MaskR
}, 0 },
11991 /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
11993 { "ktestq", { MaskG
, MaskR
}, 0 },
11996 /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
11998 { "ktestb", { MaskG
, MaskR
}, 0 },
12001 /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
12003 { "ktestd", { MaskG
, MaskR
}, 0 },
12006 /* MOD_VEX_0FAE_REG_2 */
12007 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0
) },
12010 /* MOD_VEX_0FAE_REG_3 */
12011 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0
) },
12014 /* MOD_VEX_0FD7_PREFIX_2 */
12016 { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1
) },
12019 /* MOD_VEX_0FE7_PREFIX_2 */
12020 { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0
) },
12023 /* MOD_VEX_0FF0_PREFIX_3 */
12024 { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0
) },
12027 /* MOD_VEX_0F381A_PREFIX_2 */
12028 { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0
) },
12031 /* MOD_VEX_0F382A_PREFIX_2 */
12032 { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0
) },
12035 /* MOD_VEX_0F382C_PREFIX_2 */
12036 { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0
) },
12039 /* MOD_VEX_0F382D_PREFIX_2 */
12040 { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0
) },
12043 /* MOD_VEX_0F382E_PREFIX_2 */
12044 { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0
) },
12047 /* MOD_VEX_0F382F_PREFIX_2 */
12048 { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0
) },
12051 /* MOD_VEX_0F385A_PREFIX_2 */
12052 { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0
) },
12055 /* MOD_VEX_0F388C_PREFIX_2 */
12056 { "vpmaskmov%LW", { XM
, Vex
, Mx
}, 0 },
12059 /* MOD_VEX_0F388E_PREFIX_2 */
12060 { "vpmaskmov%LW", { Mx
, Vex
, XM
}, 0 },
12063 /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
12065 { "kshiftrb", { MaskG
, MaskR
, Ib
}, 0 },
12068 /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
12070 { "kshiftrw", { MaskG
, MaskR
, Ib
}, 0 },
12073 /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
12075 { "kshiftrd", { MaskG
, MaskR
, Ib
}, 0 },
12078 /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
12080 { "kshiftrq", { MaskG
, MaskR
, Ib
}, 0 },
12083 /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
12085 { "kshiftlb", { MaskG
, MaskR
, Ib
}, 0 },
12088 /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
12090 { "kshiftlw", { MaskG
, MaskR
, Ib
}, 0 },
12093 /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
12095 { "kshiftld", { MaskG
, MaskR
, Ib
}, 0 },
12098 /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
12100 { "kshiftlq", { MaskG
, MaskR
, Ib
}, 0 },
12102 #define NEED_MOD_TABLE
12103 #include "i386-dis-evex.h"
12104 #undef NEED_MOD_TABLE
12107 static const struct dis386 rm_table
[][8] = {
12110 { "xabort", { Skip_MODRM
, Ib
}, 0 },
12114 { "xbeginT", { Skip_MODRM
, Jv
}, 0 },
12117 /* RM_0F01_REG_0 */
12119 { "vmcall", { Skip_MODRM
}, 0 },
12120 { "vmlaunch", { Skip_MODRM
}, 0 },
12121 { "vmresume", { Skip_MODRM
}, 0 },
12122 { "vmxoff", { Skip_MODRM
}, 0 },
12125 /* RM_0F01_REG_1 */
12126 { "monitor", { { OP_Monitor
, 0 } }, 0 },
12127 { "mwait", { { OP_Mwait
, 0 } }, 0 },
12128 { "clac", { Skip_MODRM
}, 0 },
12129 { "stac", { Skip_MODRM
}, 0 },
12133 { "encls", { Skip_MODRM
}, 0 },
12136 /* RM_0F01_REG_2 */
12137 { "xgetbv", { Skip_MODRM
}, 0 },
12138 { "xsetbv", { Skip_MODRM
}, 0 },
12141 { "vmfunc", { Skip_MODRM
}, 0 },
12142 { "xend", { Skip_MODRM
}, 0 },
12143 { "xtest", { Skip_MODRM
}, 0 },
12144 { "enclu", { Skip_MODRM
}, 0 },
12147 /* RM_0F01_REG_3 */
12148 { "vmrun", { Skip_MODRM
}, 0 },
12149 { "vmmcall", { Skip_MODRM
}, 0 },
12150 { "vmload", { Skip_MODRM
}, 0 },
12151 { "vmsave", { Skip_MODRM
}, 0 },
12152 { "stgi", { Skip_MODRM
}, 0 },
12153 { "clgi", { Skip_MODRM
}, 0 },
12154 { "skinit", { Skip_MODRM
}, 0 },
12155 { "invlpga", { Skip_MODRM
}, 0 },
12158 /* RM_0F01_REG_5 */
12165 { "rdpkru", { Skip_MODRM
}, 0 },
12166 { "wrpkru", { Skip_MODRM
}, 0 },
12169 /* RM_0F01_REG_7 */
12170 { "swapgs", { Skip_MODRM
}, 0 },
12171 { "rdtscp", { Skip_MODRM
}, 0 },
12172 { "monitorx", { { OP_Monitor
, 0 } }, 0 },
12173 { "mwaitx", { { OP_Mwaitx
, 0 } }, 0 },
12174 { "clzero", { Skip_MODRM
}, 0 },
12177 /* RM_0FAE_REG_5 */
12178 { "lfence", { Skip_MODRM
}, 0 },
12181 /* RM_0FAE_REG_6 */
12182 { "mfence", { Skip_MODRM
}, 0 },
12185 /* RM_0FAE_REG_7 */
12186 { "sfence", { Skip_MODRM
}, 0 },
12191 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
12193 /* We use the high bit to indicate different name for the same
12195 #define REP_PREFIX (0xf3 | 0x100)
12196 #define XACQUIRE_PREFIX (0xf2 | 0x200)
12197 #define XRELEASE_PREFIX (0xf3 | 0x400)
12198 #define BND_PREFIX (0xf2 | 0x400)
12203 int newrex
, i
, length
;
12209 last_lock_prefix
= -1;
12210 last_repz_prefix
= -1;
12211 last_repnz_prefix
= -1;
12212 last_data_prefix
= -1;
12213 last_addr_prefix
= -1;
12214 last_rex_prefix
= -1;
12215 last_seg_prefix
= -1;
12217 active_seg_prefix
= 0;
12218 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
12219 all_prefixes
[i
] = 0;
12222 /* The maximum instruction length is 15bytes. */
12223 while (length
< MAX_CODE_LENGTH
- 1)
12225 FETCH_DATA (the_info
, codep
+ 1);
12229 /* REX prefixes family. */
12246 if (address_mode
== mode_64bit
)
12250 last_rex_prefix
= i
;
12253 prefixes
|= PREFIX_REPZ
;
12254 last_repz_prefix
= i
;
12257 prefixes
|= PREFIX_REPNZ
;
12258 last_repnz_prefix
= i
;
12261 prefixes
|= PREFIX_LOCK
;
12262 last_lock_prefix
= i
;
12265 prefixes
|= PREFIX_CS
;
12266 last_seg_prefix
= i
;
12267 active_seg_prefix
= PREFIX_CS
;
12270 prefixes
|= PREFIX_SS
;
12271 last_seg_prefix
= i
;
12272 active_seg_prefix
= PREFIX_SS
;
12275 prefixes
|= PREFIX_DS
;
12276 last_seg_prefix
= i
;
12277 active_seg_prefix
= PREFIX_DS
;
12280 prefixes
|= PREFIX_ES
;
12281 last_seg_prefix
= i
;
12282 active_seg_prefix
= PREFIX_ES
;
12285 prefixes
|= PREFIX_FS
;
12286 last_seg_prefix
= i
;
12287 active_seg_prefix
= PREFIX_FS
;
12290 prefixes
|= PREFIX_GS
;
12291 last_seg_prefix
= i
;
12292 active_seg_prefix
= PREFIX_GS
;
12295 prefixes
|= PREFIX_DATA
;
12296 last_data_prefix
= i
;
12299 prefixes
|= PREFIX_ADDR
;
12300 last_addr_prefix
= i
;
12303 /* fwait is really an instruction. If there are prefixes
12304 before the fwait, they belong to the fwait, *not* to the
12305 following instruction. */
12307 if (prefixes
|| rex
)
12309 prefixes
|= PREFIX_FWAIT
;
12311 /* This ensures that the previous REX prefixes are noticed
12312 as unused prefixes, as in the return case below. */
12316 prefixes
= PREFIX_FWAIT
;
12321 /* Rex is ignored when followed by another prefix. */
12327 if (*codep
!= FWAIT_OPCODE
)
12328 all_prefixes
[i
++] = *codep
;
12336 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
12339 static const char *
12340 prefix_name (int pref
, int sizeflag
)
12342 static const char *rexes
[16] =
12345 "rex.B", /* 0x41 */
12346 "rex.X", /* 0x42 */
12347 "rex.XB", /* 0x43 */
12348 "rex.R", /* 0x44 */
12349 "rex.RB", /* 0x45 */
12350 "rex.RX", /* 0x46 */
12351 "rex.RXB", /* 0x47 */
12352 "rex.W", /* 0x48 */
12353 "rex.WB", /* 0x49 */
12354 "rex.WX", /* 0x4a */
12355 "rex.WXB", /* 0x4b */
12356 "rex.WR", /* 0x4c */
12357 "rex.WRB", /* 0x4d */
12358 "rex.WRX", /* 0x4e */
12359 "rex.WRXB", /* 0x4f */
12364 /* REX prefixes family. */
12381 return rexes
[pref
- 0x40];
12401 return (sizeflag
& DFLAG
) ? "data16" : "data32";
12403 if (address_mode
== mode_64bit
)
12404 return (sizeflag
& AFLAG
) ? "addr32" : "addr64";
12406 return (sizeflag
& AFLAG
) ? "addr16" : "addr32";
12411 case XACQUIRE_PREFIX
:
12413 case XRELEASE_PREFIX
:
12422 static char op_out
[MAX_OPERANDS
][100];
12423 static int op_ad
, op_index
[MAX_OPERANDS
];
12424 static int two_source_ops
;
12425 static bfd_vma op_address
[MAX_OPERANDS
];
12426 static bfd_vma op_riprel
[MAX_OPERANDS
];
12427 static bfd_vma start_pc
;
12430 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
12431 * (see topic "Redundant prefixes" in the "Differences from 8086"
12432 * section of the "Virtual 8086 Mode" chapter.)
12433 * 'pc' should be the address of this instruction, it will
12434 * be used to print the target address if this is a relative jump or call
12435 * The function returns the length of this instruction in bytes.
12438 static char intel_syntax
;
12439 static char intel_mnemonic
= !SYSV386_COMPAT
;
12440 static char open_char
;
12441 static char close_char
;
12442 static char separator_char
;
12443 static char scale_char
;
12451 static enum x86_64_isa isa64
;
12453 /* Here for backwards compatibility. When gdb stops using
12454 print_insn_i386_att and print_insn_i386_intel these functions can
12455 disappear, and print_insn_i386 be merged into print_insn. */
12457 print_insn_i386_att (bfd_vma pc
, disassemble_info
*info
)
12461 return print_insn (pc
, info
);
12465 print_insn_i386_intel (bfd_vma pc
, disassemble_info
*info
)
12469 return print_insn (pc
, info
);
12473 print_insn_i386 (bfd_vma pc
, disassemble_info
*info
)
12477 return print_insn (pc
, info
);
12481 print_i386_disassembler_options (FILE *stream
)
12483 fprintf (stream
, _("\n\
12484 The following i386/x86-64 specific disassembler options are supported for use\n\
12485 with the -M switch (multiple options should be separated by commas):\n"));
12487 fprintf (stream
, _(" x86-64 Disassemble in 64bit mode\n"));
12488 fprintf (stream
, _(" i386 Disassemble in 32bit mode\n"));
12489 fprintf (stream
, _(" i8086 Disassemble in 16bit mode\n"));
12490 fprintf (stream
, _(" att Display instruction in AT&T syntax\n"));
12491 fprintf (stream
, _(" intel Display instruction in Intel syntax\n"));
12492 fprintf (stream
, _(" att-mnemonic\n"
12493 " Display instruction in AT&T mnemonic\n"));
12494 fprintf (stream
, _(" intel-mnemonic\n"
12495 " Display instruction in Intel mnemonic\n"));
12496 fprintf (stream
, _(" addr64 Assume 64bit address size\n"));
12497 fprintf (stream
, _(" addr32 Assume 32bit address size\n"));
12498 fprintf (stream
, _(" addr16 Assume 16bit address size\n"));
12499 fprintf (stream
, _(" data32 Assume 32bit data size\n"));
12500 fprintf (stream
, _(" data16 Assume 16bit data size\n"));
12501 fprintf (stream
, _(" suffix Always display instruction suffix in AT&T syntax\n"));
12502 fprintf (stream
, _(" amd64 Display instruction in AMD64 ISA\n"));
12503 fprintf (stream
, _(" intel64 Display instruction in Intel64 ISA\n"));
12507 static const struct dis386 bad_opcode
= { "(bad)", { XX
}, 0 };
12509 /* Get a pointer to struct dis386 with a valid name. */
12511 static const struct dis386
*
12512 get_valid_dis386 (const struct dis386
*dp
, disassemble_info
*info
)
12514 int vindex
, vex_table_index
;
12516 if (dp
->name
!= NULL
)
12519 switch (dp
->op
[0].bytemode
)
12521 case USE_REG_TABLE
:
12522 dp
= ®_table
[dp
->op
[1].bytemode
][modrm
.reg
];
12525 case USE_MOD_TABLE
:
12526 vindex
= modrm
.mod
== 0x3 ? 1 : 0;
12527 dp
= &mod_table
[dp
->op
[1].bytemode
][vindex
];
12531 dp
= &rm_table
[dp
->op
[1].bytemode
][modrm
.rm
];
12534 case USE_PREFIX_TABLE
:
12537 /* The prefix in VEX is implicit. */
12538 switch (vex
.prefix
)
12543 case REPE_PREFIX_OPCODE
:
12546 case DATA_PREFIX_OPCODE
:
12549 case REPNE_PREFIX_OPCODE
:
12559 int last_prefix
= -1;
12562 /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
12563 When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
12565 if ((prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0)
12567 if (last_repz_prefix
> last_repnz_prefix
)
12570 prefix
= PREFIX_REPZ
;
12571 last_prefix
= last_repz_prefix
;
12576 prefix
= PREFIX_REPNZ
;
12577 last_prefix
= last_repnz_prefix
;
12580 /* Check if prefix should be ignored. */
12581 if ((((prefix_table
[dp
->op
[1].bytemode
][vindex
].prefix_requirement
12582 & PREFIX_IGNORED
) >> PREFIX_IGNORED_SHIFT
)
12587 if (vindex
== 0 && (prefixes
& PREFIX_DATA
) != 0)
12590 prefix
= PREFIX_DATA
;
12591 last_prefix
= last_data_prefix
;
12596 used_prefixes
|= prefix
;
12597 all_prefixes
[last_prefix
] = 0;
12600 dp
= &prefix_table
[dp
->op
[1].bytemode
][vindex
];
12603 case USE_X86_64_TABLE
:
12604 vindex
= address_mode
== mode_64bit
? 1 : 0;
12605 dp
= &x86_64_table
[dp
->op
[1].bytemode
][vindex
];
12608 case USE_3BYTE_TABLE
:
12609 FETCH_DATA (info
, codep
+ 2);
12611 dp
= &three_byte_table
[dp
->op
[1].bytemode
][vindex
];
12613 modrm
.mod
= (*codep
>> 6) & 3;
12614 modrm
.reg
= (*codep
>> 3) & 7;
12615 modrm
.rm
= *codep
& 7;
12618 case USE_VEX_LEN_TABLE
:
12622 switch (vex
.length
)
12635 dp
= &vex_len_table
[dp
->op
[1].bytemode
][vindex
];
12638 case USE_XOP_8F_TABLE
:
12639 FETCH_DATA (info
, codep
+ 3);
12640 /* All bits in the REX prefix are ignored. */
12642 rex
= ~(*codep
>> 5) & 0x7;
12644 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
12645 switch ((*codep
& 0x1f))
12651 vex_table_index
= XOP_08
;
12654 vex_table_index
= XOP_09
;
12657 vex_table_index
= XOP_0A
;
12661 vex
.w
= *codep
& 0x80;
12662 if (vex
.w
&& address_mode
== mode_64bit
)
12665 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
12666 if (address_mode
!= mode_64bit
)
12668 /* In 16/32-bit mode REX_B is silently ignored. */
12670 if (vex
.register_specifier
> 0x7)
12677 vex
.length
= (*codep
& 0x4) ? 256 : 128;
12678 switch ((*codep
& 0x3))
12684 vex
.prefix
= DATA_PREFIX_OPCODE
;
12687 vex
.prefix
= REPE_PREFIX_OPCODE
;
12690 vex
.prefix
= REPNE_PREFIX_OPCODE
;
12697 dp
= &xop_table
[vex_table_index
][vindex
];
12700 FETCH_DATA (info
, codep
+ 1);
12701 modrm
.mod
= (*codep
>> 6) & 3;
12702 modrm
.reg
= (*codep
>> 3) & 7;
12703 modrm
.rm
= *codep
& 7;
12706 case USE_VEX_C4_TABLE
:
12708 FETCH_DATA (info
, codep
+ 3);
12709 /* All bits in the REX prefix are ignored. */
12711 rex
= ~(*codep
>> 5) & 0x7;
12712 switch ((*codep
& 0x1f))
12718 vex_table_index
= VEX_0F
;
12721 vex_table_index
= VEX_0F38
;
12724 vex_table_index
= VEX_0F3A
;
12728 vex
.w
= *codep
& 0x80;
12729 if (address_mode
== mode_64bit
)
12733 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
12737 /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
12738 is ignored, other REX bits are 0 and the highest bit in
12739 VEX.vvvv is also ignored. */
12741 vex
.register_specifier
= (~(*codep
>> 3)) & 0x7;
12743 vex
.length
= (*codep
& 0x4) ? 256 : 128;
12744 switch ((*codep
& 0x3))
12750 vex
.prefix
= DATA_PREFIX_OPCODE
;
12753 vex
.prefix
= REPE_PREFIX_OPCODE
;
12756 vex
.prefix
= REPNE_PREFIX_OPCODE
;
12763 dp
= &vex_table
[vex_table_index
][vindex
];
12765 /* There is no MODRM byte for VEX0F 77. */
12766 if (vex_table_index
!= VEX_0F
|| vindex
!= 0x77)
12768 FETCH_DATA (info
, codep
+ 1);
12769 modrm
.mod
= (*codep
>> 6) & 3;
12770 modrm
.reg
= (*codep
>> 3) & 7;
12771 modrm
.rm
= *codep
& 7;
12775 case USE_VEX_C5_TABLE
:
12777 FETCH_DATA (info
, codep
+ 2);
12778 /* All bits in the REX prefix are ignored. */
12780 rex
= (*codep
& 0x80) ? 0 : REX_R
;
12782 /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
12784 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
12786 vex
.length
= (*codep
& 0x4) ? 256 : 128;
12787 switch ((*codep
& 0x3))
12793 vex
.prefix
= DATA_PREFIX_OPCODE
;
12796 vex
.prefix
= REPE_PREFIX_OPCODE
;
12799 vex
.prefix
= REPNE_PREFIX_OPCODE
;
12806 dp
= &vex_table
[dp
->op
[1].bytemode
][vindex
];
12808 /* There is no MODRM byte for VEX 77. */
12809 if (vindex
!= 0x77)
12811 FETCH_DATA (info
, codep
+ 1);
12812 modrm
.mod
= (*codep
>> 6) & 3;
12813 modrm
.reg
= (*codep
>> 3) & 7;
12814 modrm
.rm
= *codep
& 7;
12818 case USE_VEX_W_TABLE
:
12822 dp
= &vex_w_table
[dp
->op
[1].bytemode
][vex
.w
? 1 : 0];
12825 case USE_EVEX_TABLE
:
12826 two_source_ops
= 0;
12829 FETCH_DATA (info
, codep
+ 4);
12830 /* All bits in the REX prefix are ignored. */
12832 /* The first byte after 0x62. */
12833 rex
= ~(*codep
>> 5) & 0x7;
12834 vex
.r
= *codep
& 0x10;
12835 switch ((*codep
& 0xf))
12838 return &bad_opcode
;
12840 vex_table_index
= EVEX_0F
;
12843 vex_table_index
= EVEX_0F38
;
12846 vex_table_index
= EVEX_0F3A
;
12850 /* The second byte after 0x62. */
12852 vex
.w
= *codep
& 0x80;
12853 if (vex
.w
&& address_mode
== mode_64bit
)
12856 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
12857 if (address_mode
!= mode_64bit
)
12859 /* In 16/32-bit mode silently ignore following bits. */
12863 vex
.register_specifier
&= 0x7;
12867 if (!(*codep
& 0x4))
12868 return &bad_opcode
;
12870 switch ((*codep
& 0x3))
12876 vex
.prefix
= DATA_PREFIX_OPCODE
;
12879 vex
.prefix
= REPE_PREFIX_OPCODE
;
12882 vex
.prefix
= REPNE_PREFIX_OPCODE
;
12886 /* The third byte after 0x62. */
12889 /* Remember the static rounding bits. */
12890 vex
.ll
= (*codep
>> 5) & 3;
12891 vex
.b
= (*codep
& 0x10) != 0;
12893 vex
.v
= *codep
& 0x8;
12894 vex
.mask_register_specifier
= *codep
& 0x7;
12895 vex
.zeroing
= *codep
& 0x80;
12901 dp
= &evex_table
[vex_table_index
][vindex
];
12903 FETCH_DATA (info
, codep
+ 1);
12904 modrm
.mod
= (*codep
>> 6) & 3;
12905 modrm
.reg
= (*codep
>> 3) & 7;
12906 modrm
.rm
= *codep
& 7;
12908 /* Set vector length. */
12909 if (modrm
.mod
== 3 && vex
.b
)
12925 return &bad_opcode
;
12938 if (dp
->name
!= NULL
)
12941 return get_valid_dis386 (dp
, info
);
12945 get_sib (disassemble_info
*info
, int sizeflag
)
12947 /* If modrm.mod == 3, operand must be register. */
12949 && ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
12953 FETCH_DATA (info
, codep
+ 2);
12954 sib
.index
= (codep
[1] >> 3) & 7;
12955 sib
.scale
= (codep
[1] >> 6) & 3;
12956 sib
.base
= codep
[1] & 7;
12961 print_insn (bfd_vma pc
, disassemble_info
*info
)
12963 const struct dis386
*dp
;
12965 char *op_txt
[MAX_OPERANDS
];
12967 int sizeflag
, orig_sizeflag
;
12969 struct dis_private priv
;
12972 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
12973 if ((info
->mach
& bfd_mach_i386_i386
) != 0)
12974 address_mode
= mode_32bit
;
12975 else if (info
->mach
== bfd_mach_i386_i8086
)
12977 address_mode
= mode_16bit
;
12978 priv
.orig_sizeflag
= 0;
12981 address_mode
= mode_64bit
;
12983 if (intel_syntax
== (char) -1)
12984 intel_syntax
= (info
->mach
& bfd_mach_i386_intel_syntax
) != 0;
12986 for (p
= info
->disassembler_options
; p
!= NULL
; )
12988 if (CONST_STRNEQ (p
, "amd64"))
12990 else if (CONST_STRNEQ (p
, "intel64"))
12992 else if (CONST_STRNEQ (p
, "x86-64"))
12994 address_mode
= mode_64bit
;
12995 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
12997 else if (CONST_STRNEQ (p
, "i386"))
12999 address_mode
= mode_32bit
;
13000 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
13002 else if (CONST_STRNEQ (p
, "i8086"))
13004 address_mode
= mode_16bit
;
13005 priv
.orig_sizeflag
= 0;
13007 else if (CONST_STRNEQ (p
, "intel"))
13010 if (CONST_STRNEQ (p
+ 5, "-mnemonic"))
13011 intel_mnemonic
= 1;
13013 else if (CONST_STRNEQ (p
, "att"))
13016 if (CONST_STRNEQ (p
+ 3, "-mnemonic"))
13017 intel_mnemonic
= 0;
13019 else if (CONST_STRNEQ (p
, "addr"))
13021 if (address_mode
== mode_64bit
)
13023 if (p
[4] == '3' && p
[5] == '2')
13024 priv
.orig_sizeflag
&= ~AFLAG
;
13025 else if (p
[4] == '6' && p
[5] == '4')
13026 priv
.orig_sizeflag
|= AFLAG
;
13030 if (p
[4] == '1' && p
[5] == '6')
13031 priv
.orig_sizeflag
&= ~AFLAG
;
13032 else if (p
[4] == '3' && p
[5] == '2')
13033 priv
.orig_sizeflag
|= AFLAG
;
13036 else if (CONST_STRNEQ (p
, "data"))
13038 if (p
[4] == '1' && p
[5] == '6')
13039 priv
.orig_sizeflag
&= ~DFLAG
;
13040 else if (p
[4] == '3' && p
[5] == '2')
13041 priv
.orig_sizeflag
|= DFLAG
;
13043 else if (CONST_STRNEQ (p
, "suffix"))
13044 priv
.orig_sizeflag
|= SUFFIX_ALWAYS
;
13046 p
= strchr (p
, ',');
13051 if (address_mode
== mode_64bit
&& sizeof (bfd_vma
) < 8)
13053 (*info
->fprintf_func
) (info
->stream
,
13054 _("64-bit address is disabled"));
13060 names64
= intel_names64
;
13061 names32
= intel_names32
;
13062 names16
= intel_names16
;
13063 names8
= intel_names8
;
13064 names8rex
= intel_names8rex
;
13065 names_seg
= intel_names_seg
;
13066 names_mm
= intel_names_mm
;
13067 names_bnd
= intel_names_bnd
;
13068 names_xmm
= intel_names_xmm
;
13069 names_ymm
= intel_names_ymm
;
13070 names_zmm
= intel_names_zmm
;
13071 index64
= intel_index64
;
13072 index32
= intel_index32
;
13073 names_mask
= intel_names_mask
;
13074 index16
= intel_index16
;
13077 separator_char
= '+';
13082 names64
= att_names64
;
13083 names32
= att_names32
;
13084 names16
= att_names16
;
13085 names8
= att_names8
;
13086 names8rex
= att_names8rex
;
13087 names_seg
= att_names_seg
;
13088 names_mm
= att_names_mm
;
13089 names_bnd
= att_names_bnd
;
13090 names_xmm
= att_names_xmm
;
13091 names_ymm
= att_names_ymm
;
13092 names_zmm
= att_names_zmm
;
13093 index64
= att_index64
;
13094 index32
= att_index32
;
13095 names_mask
= att_names_mask
;
13096 index16
= att_index16
;
13099 separator_char
= ',';
13103 /* The output looks better if we put 7 bytes on a line, since that
13104 puts most long word instructions on a single line. Use 8 bytes
13106 if ((info
->mach
& bfd_mach_l1om
) != 0)
13107 info
->bytes_per_line
= 8;
13109 info
->bytes_per_line
= 7;
13111 info
->private_data
= &priv
;
13112 priv
.max_fetched
= priv
.the_buffer
;
13113 priv
.insn_start
= pc
;
13116 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
13124 start_codep
= priv
.the_buffer
;
13125 codep
= priv
.the_buffer
;
13127 if (OPCODES_SIGSETJMP (priv
.bailout
) != 0)
13131 /* Getting here means we tried for data but didn't get it. That
13132 means we have an incomplete instruction of some sort. Just
13133 print the first byte as a prefix or a .byte pseudo-op. */
13134 if (codep
> priv
.the_buffer
)
13136 name
= prefix_name (priv
.the_buffer
[0], priv
.orig_sizeflag
);
13138 (*info
->fprintf_func
) (info
->stream
, "%s", name
);
13141 /* Just print the first byte as a .byte instruction. */
13142 (*info
->fprintf_func
) (info
->stream
, ".byte 0x%x",
13143 (unsigned int) priv
.the_buffer
[0]);
13153 sizeflag
= priv
.orig_sizeflag
;
13155 if (!ckprefix () || rex_used
)
13157 /* Too many prefixes or unused REX prefixes. */
13159 i
< (int) ARRAY_SIZE (all_prefixes
) && all_prefixes
[i
];
13161 (*info
->fprintf_func
) (info
->stream
, "%s%s",
13163 prefix_name (all_prefixes
[i
], sizeflag
));
13167 insn_codep
= codep
;
13169 FETCH_DATA (info
, codep
+ 1);
13170 two_source_ops
= (*codep
== 0x62) || (*codep
== 0xc8);
13172 if (((prefixes
& PREFIX_FWAIT
)
13173 && ((*codep
< 0xd8) || (*codep
> 0xdf))))
13175 /* Handle prefixes before fwait. */
13176 for (i
= 0; i
< fwait_prefix
&& all_prefixes
[i
];
13178 (*info
->fprintf_func
) (info
->stream
, "%s ",
13179 prefix_name (all_prefixes
[i
], sizeflag
));
13180 (*info
->fprintf_func
) (info
->stream
, "fwait");
13184 if (*codep
== 0x0f)
13186 unsigned char threebyte
;
13189 FETCH_DATA (info
, codep
+ 1);
13190 threebyte
= *codep
;
13191 dp
= &dis386_twobyte
[threebyte
];
13192 need_modrm
= twobyte_has_modrm
[*codep
];
13197 dp
= &dis386
[*codep
];
13198 need_modrm
= onebyte_has_modrm
[*codep
];
13202 /* Save sizeflag for printing the extra prefixes later before updating
13203 it for mnemonic and operand processing. The prefix names depend
13204 only on the address mode. */
13205 orig_sizeflag
= sizeflag
;
13206 if (prefixes
& PREFIX_ADDR
)
13208 if ((prefixes
& PREFIX_DATA
))
13214 FETCH_DATA (info
, codep
+ 1);
13215 modrm
.mod
= (*codep
>> 6) & 3;
13216 modrm
.reg
= (*codep
>> 3) & 7;
13217 modrm
.rm
= *codep
& 7;
13225 if (dp
->name
== NULL
&& dp
->op
[0].bytemode
== FLOATCODE
)
13227 get_sib (info
, sizeflag
);
13228 dofloat (sizeflag
);
13232 dp
= get_valid_dis386 (dp
, info
);
13233 if (dp
!= NULL
&& putop (dp
->name
, sizeflag
) == 0)
13235 get_sib (info
, sizeflag
);
13236 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
13239 op_ad
= MAX_OPERANDS
- 1 - i
;
13241 (*dp
->op
[i
].rtn
) (dp
->op
[i
].bytemode
, sizeflag
);
13242 /* For EVEX instruction after the last operand masking
13243 should be printed. */
13244 if (i
== 0 && vex
.evex
)
13246 /* Don't print {%k0}. */
13247 if (vex
.mask_register_specifier
)
13250 oappend (names_mask
[vex
.mask_register_specifier
]);
13260 /* Check if the REX prefix is used. */
13261 if (rex_ignored
== 0 && (rex
^ rex_used
) == 0 && last_rex_prefix
>= 0)
13262 all_prefixes
[last_rex_prefix
] = 0;
13264 /* Check if the SEG prefix is used. */
13265 if ((prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
| PREFIX_ES
13266 | PREFIX_FS
| PREFIX_GS
)) != 0
13267 && (used_prefixes
& active_seg_prefix
) != 0)
13268 all_prefixes
[last_seg_prefix
] = 0;
13270 /* Check if the ADDR prefix is used. */
13271 if ((prefixes
& PREFIX_ADDR
) != 0
13272 && (used_prefixes
& PREFIX_ADDR
) != 0)
13273 all_prefixes
[last_addr_prefix
] = 0;
13275 /* Check if the DATA prefix is used. */
13276 if ((prefixes
& PREFIX_DATA
) != 0
13277 && (used_prefixes
& PREFIX_DATA
) != 0)
13278 all_prefixes
[last_data_prefix
] = 0;
13280 /* Print the extra prefixes. */
13282 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
13283 if (all_prefixes
[i
])
13286 name
= prefix_name (all_prefixes
[i
], orig_sizeflag
);
13289 prefix_length
+= strlen (name
) + 1;
13290 (*info
->fprintf_func
) (info
->stream
, "%s ", name
);
13293 /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
13294 unused, opcode is invalid. Since the PREFIX_DATA prefix may be
13295 used by putop and MMX/SSE operand and may be overriden by the
13296 PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
13298 if (dp
->prefix_requirement
== PREFIX_OPCODE
13299 && dp
!= &bad_opcode
13301 & (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0
13303 & (PREFIX_REPZ
| PREFIX_REPNZ
)) == 0)
13305 & (PREFIX_REPZ
| PREFIX_REPNZ
| PREFIX_DATA
))
13307 && (used_prefixes
& PREFIX_DATA
) == 0))))
13309 (*info
->fprintf_func
) (info
->stream
, "(bad)");
13310 return end_codep
- priv
.the_buffer
;
13313 /* Check maximum code length. */
13314 if ((codep
- start_codep
) > MAX_CODE_LENGTH
)
13316 (*info
->fprintf_func
) (info
->stream
, "(bad)");
13317 return MAX_CODE_LENGTH
;
13320 obufp
= mnemonicendp
;
13321 for (i
= strlen (obuf
) + prefix_length
; i
< 6; i
++)
13324 (*info
->fprintf_func
) (info
->stream
, "%s", obuf
);
13326 /* The enter and bound instructions are printed with operands in the same
13327 order as the intel book; everything else is printed in reverse order. */
13328 if (intel_syntax
|| two_source_ops
)
13332 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
13333 op_txt
[i
] = op_out
[i
];
13335 if (intel_syntax
&& dp
&& dp
->op
[2].rtn
== OP_Rounding
13336 && dp
->op
[3].rtn
== OP_E
&& dp
->op
[4].rtn
== NULL
)
13338 op_txt
[2] = op_out
[3];
13339 op_txt
[3] = op_out
[2];
13342 for (i
= 0; i
< (MAX_OPERANDS
>> 1); ++i
)
13344 op_ad
= op_index
[i
];
13345 op_index
[i
] = op_index
[MAX_OPERANDS
- 1 - i
];
13346 op_index
[MAX_OPERANDS
- 1 - i
] = op_ad
;
13347 riprel
= op_riprel
[i
];
13348 op_riprel
[i
] = op_riprel
[MAX_OPERANDS
- 1 - i
];
13349 op_riprel
[MAX_OPERANDS
- 1 - i
] = riprel
;
13354 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
13355 op_txt
[MAX_OPERANDS
- 1 - i
] = op_out
[i
];
13359 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
13363 (*info
->fprintf_func
) (info
->stream
, ",");
13364 if (op_index
[i
] != -1 && !op_riprel
[i
])
13365 (*info
->print_address_func
) ((bfd_vma
) op_address
[op_index
[i
]], info
);
13367 (*info
->fprintf_func
) (info
->stream
, "%s", op_txt
[i
]);
13371 for (i
= 0; i
< MAX_OPERANDS
; i
++)
13372 if (op_index
[i
] != -1 && op_riprel
[i
])
13374 (*info
->fprintf_func
) (info
->stream
, " # ");
13375 (*info
->print_address_func
) ((bfd_vma
) (start_pc
+ (codep
- start_codep
)
13376 + op_address
[op_index
[i
]]), info
);
13379 return codep
- priv
.the_buffer
;
13382 static const char *float_mem
[] = {
13457 static const unsigned char float_mem_mode
[] = {
13532 #define ST { OP_ST, 0 }
13533 #define STi { OP_STi, 0 }
13535 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
13536 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
13537 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
13538 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
13539 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
13540 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
13541 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
13542 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
13543 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
13545 static const struct dis386 float_reg
[][8] = {
13548 { "fadd", { ST
, STi
}, 0 },
13549 { "fmul", { ST
, STi
}, 0 },
13550 { "fcom", { STi
}, 0 },
13551 { "fcomp", { STi
}, 0 },
13552 { "fsub", { ST
, STi
}, 0 },
13553 { "fsubr", { ST
, STi
}, 0 },
13554 { "fdiv", { ST
, STi
}, 0 },
13555 { "fdivr", { ST
, STi
}, 0 },
13559 { "fld", { STi
}, 0 },
13560 { "fxch", { STi
}, 0 },
13570 { "fcmovb", { ST
, STi
}, 0 },
13571 { "fcmove", { ST
, STi
}, 0 },
13572 { "fcmovbe",{ ST
, STi
}, 0 },
13573 { "fcmovu", { ST
, STi
}, 0 },
13581 { "fcmovnb",{ ST
, STi
}, 0 },
13582 { "fcmovne",{ ST
, STi
}, 0 },
13583 { "fcmovnbe",{ ST
, STi
}, 0 },
13584 { "fcmovnu",{ ST
, STi
}, 0 },
13586 { "fucomi", { ST
, STi
}, 0 },
13587 { "fcomi", { ST
, STi
}, 0 },
13592 { "fadd", { STi
, ST
}, 0 },
13593 { "fmul", { STi
, ST
}, 0 },
13596 { "fsub!M", { STi
, ST
}, 0 },
13597 { "fsubM", { STi
, ST
}, 0 },
13598 { "fdiv!M", { STi
, ST
}, 0 },
13599 { "fdivM", { STi
, ST
}, 0 },
13603 { "ffree", { STi
}, 0 },
13605 { "fst", { STi
}, 0 },
13606 { "fstp", { STi
}, 0 },
13607 { "fucom", { STi
}, 0 },
13608 { "fucomp", { STi
}, 0 },
13614 { "faddp", { STi
, ST
}, 0 },
13615 { "fmulp", { STi
, ST
}, 0 },
13618 { "fsub!Mp", { STi
, ST
}, 0 },
13619 { "fsubMp", { STi
, ST
}, 0 },
13620 { "fdiv!Mp", { STi
, ST
}, 0 },
13621 { "fdivMp", { STi
, ST
}, 0 },
13625 { "ffreep", { STi
}, 0 },
13630 { "fucomip", { ST
, STi
}, 0 },
13631 { "fcomip", { ST
, STi
}, 0 },
13636 static char *fgrps
[][8] = {
13639 "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13644 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13649 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
13654 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
13659 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
13664 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
13669 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13674 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
13675 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
13680 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13685 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13690 swap_operand (void)
13692 mnemonicendp
[0] = '.';
13693 mnemonicendp
[1] = 's';
13698 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED
,
13699 int sizeflag ATTRIBUTE_UNUSED
)
13701 /* Skip mod/rm byte. */
13707 dofloat (int sizeflag
)
13709 const struct dis386
*dp
;
13710 unsigned char floatop
;
13712 floatop
= codep
[-1];
13714 if (modrm
.mod
!= 3)
13716 int fp_indx
= (floatop
- 0xd8) * 8 + modrm
.reg
;
13718 putop (float_mem
[fp_indx
], sizeflag
);
13721 OP_E (float_mem_mode
[fp_indx
], sizeflag
);
13724 /* Skip mod/rm byte. */
13728 dp
= &float_reg
[floatop
- 0xd8][modrm
.reg
];
13729 if (dp
->name
== NULL
)
13731 putop (fgrps
[dp
->op
[0].bytemode
][modrm
.rm
], sizeflag
);
13733 /* Instruction fnstsw is only one with strange arg. */
13734 if (floatop
== 0xdf && codep
[-1] == 0xe0)
13735 strcpy (op_out
[0], names16
[0]);
13739 putop (dp
->name
, sizeflag
);
13744 (*dp
->op
[0].rtn
) (dp
->op
[0].bytemode
, sizeflag
);
13749 (*dp
->op
[1].rtn
) (dp
->op
[1].bytemode
, sizeflag
);
13753 /* Like oappend (below), but S is a string starting with '%'.
13754 In Intel syntax, the '%' is elided. */
13756 oappend_maybe_intel (const char *s
)
13758 oappend (s
+ intel_syntax
);
13762 OP_ST (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
13764 oappend_maybe_intel ("%st");
13768 OP_STi (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
13770 sprintf (scratchbuf
, "%%st(%d)", modrm
.rm
);
13771 oappend_maybe_intel (scratchbuf
);
13774 /* Capital letters in template are macros. */
13776 putop (const char *in_template
, int sizeflag
)
13781 unsigned int l
= 0, len
= 1;
13784 #define SAVE_LAST(c) \
13785 if (l < len && l < sizeof (last)) \
13790 for (p
= in_template
; *p
; p
++)
13806 while (*++p
!= '|')
13807 if (*p
== '}' || *p
== '\0')
13810 /* Fall through. */
13815 while (*++p
!= '}')
13826 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
13830 if (l
== 0 && len
== 1)
13835 if (sizeflag
& SUFFIX_ALWAYS
)
13848 if (address_mode
== mode_64bit
13849 && !(prefixes
& PREFIX_ADDR
))
13860 if (intel_syntax
&& !alt
)
13862 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
13864 if (sizeflag
& DFLAG
)
13865 *obufp
++ = intel_syntax
? 'd' : 'l';
13867 *obufp
++ = intel_syntax
? 'w' : 's';
13868 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13872 if (intel_syntax
|| !(sizeflag
& SUFFIX_ALWAYS
))
13875 if (modrm
.mod
== 3)
13881 if (sizeflag
& DFLAG
)
13882 *obufp
++ = intel_syntax
? 'd' : 'l';
13885 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13891 case 'E': /* For jcxz/jecxz */
13892 if (address_mode
== mode_64bit
)
13894 if (sizeflag
& AFLAG
)
13900 if (sizeflag
& AFLAG
)
13902 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
13907 if ((prefixes
& PREFIX_ADDR
) || (sizeflag
& SUFFIX_ALWAYS
))
13909 if (sizeflag
& AFLAG
)
13910 *obufp
++ = address_mode
== mode_64bit
? 'q' : 'l';
13912 *obufp
++ = address_mode
== mode_64bit
? 'l' : 'w';
13913 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
13917 if (intel_syntax
|| (obufp
[-1] != 's' && !(sizeflag
& SUFFIX_ALWAYS
)))
13919 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
13923 if (!(rex
& REX_W
))
13924 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13929 if ((prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_CS
13930 || (prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_DS
)
13932 used_prefixes
|= prefixes
& (PREFIX_CS
| PREFIX_DS
);
13935 if (prefixes
& PREFIX_DS
)
13954 if (l
!= 0 || len
!= 1)
13956 if (l
!= 1 || len
!= 2 || last
[0] != 'X')
13961 if (!need_vex
|| !vex
.evex
)
13964 || ((modrm
.mod
== 3 || vex
.b
) && !(sizeflag
& SUFFIX_ALWAYS
)))
13966 switch (vex
.length
)
13984 if (address_mode
== mode_64bit
&& (sizeflag
& SUFFIX_ALWAYS
))
13989 /* Fall through. */
13992 if (l
!= 0 || len
!= 1)
14000 if (sizeflag
& SUFFIX_ALWAYS
)
14004 if (intel_mnemonic
!= cond
)
14008 if ((prefixes
& PREFIX_FWAIT
) == 0)
14011 used_prefixes
|= PREFIX_FWAIT
;
14017 else if (intel_syntax
&& (sizeflag
& DFLAG
))
14021 if (!(rex
& REX_W
))
14022 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14026 && address_mode
== mode_64bit
14027 && isa64
== intel64
)
14032 /* Fall through. */
14035 && address_mode
== mode_64bit
14036 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14041 /* Fall through. */
14044 if (l
== 0 && len
== 1)
14049 if ((rex
& REX_W
) == 0
14050 && (prefixes
& PREFIX_DATA
))
14052 if ((sizeflag
& DFLAG
) == 0)
14054 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14058 if ((prefixes
& PREFIX_DATA
)
14060 || (sizeflag
& SUFFIX_ALWAYS
))
14067 if (sizeflag
& DFLAG
)
14071 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14077 if (l
!= 1 || len
!= 2 || last
[0] != 'L')
14083 if ((prefixes
& PREFIX_DATA
)
14085 || (sizeflag
& SUFFIX_ALWAYS
))
14092 if (sizeflag
& DFLAG
)
14093 *obufp
++ = intel_syntax
? 'd' : 'l';
14096 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14104 if (address_mode
== mode_64bit
14105 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14107 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
14111 /* Fall through. */
14114 if (l
== 0 && len
== 1)
14117 if (intel_syntax
&& !alt
)
14120 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
14126 if (sizeflag
& DFLAG
)
14127 *obufp
++ = intel_syntax
? 'd' : 'l';
14130 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14136 if (l
!= 1 || len
!= 2 || last
[0] != 'L')
14142 || (modrm
.mod
== 3 && !(sizeflag
& SUFFIX_ALWAYS
)))
14157 else if (sizeflag
& DFLAG
)
14166 if (intel_syntax
&& !p
[1]
14167 && ((rex
& REX_W
) || (sizeflag
& DFLAG
)))
14169 if (!(rex
& REX_W
))
14170 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14173 if (l
== 0 && len
== 1)
14177 if (address_mode
== mode_64bit
14178 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14180 if (sizeflag
& SUFFIX_ALWAYS
)
14202 /* Fall through. */
14205 if (l
== 0 && len
== 1)
14210 if (sizeflag
& SUFFIX_ALWAYS
)
14216 if (sizeflag
& DFLAG
)
14220 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14234 if (address_mode
== mode_64bit
14235 && !(prefixes
& PREFIX_ADDR
))
14246 if (l
!= 0 || len
!= 1)
14251 if (need_vex
&& vex
.prefix
)
14253 if (vex
.prefix
== DATA_PREFIX_OPCODE
)
14260 if (prefixes
& PREFIX_DATA
)
14264 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14268 if (l
== 0 && len
== 1)
14270 if (intel_syntax
|| !(sizeflag
& SUFFIX_ALWAYS
))
14281 if (l
!= 1 || len
!= 2 || last
[0] != 'X')
14289 || ((modrm
.mod
== 3 || vex
.b
) && !(sizeflag
& SUFFIX_ALWAYS
)))
14291 switch (vex
.length
)
14307 if (l
== 0 && len
== 1)
14309 /* operand size flag for cwtl, cbtw */
14318 else if (sizeflag
& DFLAG
)
14322 if (!(rex
& REX_W
))
14323 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14330 && last
[0] != 'L'))
14337 if (last
[0] == 'X')
14338 *obufp
++ = vex
.w
? 'd': 's';
14340 *obufp
++ = vex
.w
? 'q': 'd';
14346 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
14348 if (sizeflag
& DFLAG
)
14352 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14358 if (address_mode
== mode_64bit
14359 && (isa64
== intel64
14360 || ((sizeflag
& DFLAG
) || (rex
& REX_W
))))
14362 else if ((prefixes
& PREFIX_DATA
))
14364 if (!(sizeflag
& DFLAG
))
14366 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14373 mnemonicendp
= obufp
;
14378 oappend (const char *s
)
14380 obufp
= stpcpy (obufp
, s
);
14386 /* Only print the active segment register. */
14387 if (!active_seg_prefix
)
14390 used_prefixes
|= active_seg_prefix
;
14391 switch (active_seg_prefix
)
14394 oappend_maybe_intel ("%cs:");
14397 oappend_maybe_intel ("%ds:");
14400 oappend_maybe_intel ("%ss:");
14403 oappend_maybe_intel ("%es:");
14406 oappend_maybe_intel ("%fs:");
14409 oappend_maybe_intel ("%gs:");
14417 OP_indirE (int bytemode
, int sizeflag
)
14421 OP_E (bytemode
, sizeflag
);
14425 print_operand_value (char *buf
, int hex
, bfd_vma disp
)
14427 if (address_mode
== mode_64bit
)
14435 sprintf_vma (tmp
, disp
);
14436 for (i
= 0; tmp
[i
] == '0' && tmp
[i
+ 1]; i
++);
14437 strcpy (buf
+ 2, tmp
+ i
);
14441 bfd_signed_vma v
= disp
;
14448 /* Check for possible overflow on 0x8000000000000000. */
14451 strcpy (buf
, "9223372036854775808");
14465 tmp
[28 - i
] = (v
% 10) + '0';
14469 strcpy (buf
, tmp
+ 29 - i
);
14475 sprintf (buf
, "0x%x", (unsigned int) disp
);
14477 sprintf (buf
, "%d", (int) disp
);
14481 /* Put DISP in BUF as signed hex number. */
14484 print_displacement (char *buf
, bfd_vma disp
)
14486 bfd_signed_vma val
= disp
;
14495 /* Check for possible overflow. */
14498 switch (address_mode
)
14501 strcpy (buf
+ j
, "0x8000000000000000");
14504 strcpy (buf
+ j
, "0x80000000");
14507 strcpy (buf
+ j
, "0x8000");
14517 sprintf_vma (tmp
, (bfd_vma
) val
);
14518 for (i
= 0; tmp
[i
] == '0'; i
++)
14520 if (tmp
[i
] == '\0')
14522 strcpy (buf
+ j
, tmp
+ i
);
14526 intel_operand_size (int bytemode
, int sizeflag
)
14530 && (bytemode
== x_mode
14531 || bytemode
== evex_half_bcst_xmmq_mode
))
14534 oappend ("QWORD PTR ");
14536 oappend ("DWORD PTR ");
14545 oappend ("BYTE PTR ");
14550 oappend ("WORD PTR ");
14553 if (address_mode
== mode_64bit
&& isa64
== intel64
)
14555 oappend ("QWORD PTR ");
14558 /* Fall through. */
14560 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14562 oappend ("QWORD PTR ");
14565 /* Fall through. */
14571 oappend ("QWORD PTR ");
14574 if ((sizeflag
& DFLAG
) || bytemode
== dq_mode
)
14575 oappend ("DWORD PTR ");
14577 oappend ("WORD PTR ");
14578 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14582 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
14584 oappend ("WORD PTR ");
14585 if (!(rex
& REX_W
))
14586 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14589 if (sizeflag
& DFLAG
)
14590 oappend ("QWORD PTR ");
14592 oappend ("DWORD PTR ");
14593 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14596 case d_scalar_mode
:
14597 case d_scalar_swap_mode
:
14600 oappend ("DWORD PTR ");
14603 case q_scalar_mode
:
14604 case q_scalar_swap_mode
:
14606 oappend ("QWORD PTR ");
14609 if (address_mode
== mode_64bit
)
14610 oappend ("QWORD PTR ");
14612 oappend ("DWORD PTR ");
14615 if (sizeflag
& DFLAG
)
14616 oappend ("FWORD PTR ");
14618 oappend ("DWORD PTR ");
14619 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14622 oappend ("TBYTE PTR ");
14626 case evex_x_gscat_mode
:
14627 case evex_x_nobcst_mode
:
14630 switch (vex
.length
)
14633 oappend ("XMMWORD PTR ");
14636 oappend ("YMMWORD PTR ");
14639 oappend ("ZMMWORD PTR ");
14646 oappend ("XMMWORD PTR ");
14649 oappend ("XMMWORD PTR ");
14652 oappend ("YMMWORD PTR ");
14655 case evex_half_bcst_xmmq_mode
:
14659 switch (vex
.length
)
14662 oappend ("QWORD PTR ");
14665 oappend ("XMMWORD PTR ");
14668 oappend ("YMMWORD PTR ");
14678 switch (vex
.length
)
14683 oappend ("BYTE PTR ");
14693 switch (vex
.length
)
14698 oappend ("WORD PTR ");
14708 switch (vex
.length
)
14713 oappend ("DWORD PTR ");
14723 switch (vex
.length
)
14728 oappend ("QWORD PTR ");
14738 switch (vex
.length
)
14741 oappend ("WORD PTR ");
14744 oappend ("DWORD PTR ");
14747 oappend ("QWORD PTR ");
14757 switch (vex
.length
)
14760 oappend ("DWORD PTR ");
14763 oappend ("QWORD PTR ");
14766 oappend ("XMMWORD PTR ");
14776 switch (vex
.length
)
14779 oappend ("QWORD PTR ");
14782 oappend ("YMMWORD PTR ");
14785 oappend ("ZMMWORD PTR ");
14795 switch (vex
.length
)
14799 oappend ("XMMWORD PTR ");
14806 oappend ("OWORD PTR ");
14809 case vex_w_dq_mode
:
14810 case vex_scalar_w_dq_mode
:
14815 oappend ("QWORD PTR ");
14817 oappend ("DWORD PTR ");
14819 case vex_vsib_d_w_dq_mode
:
14820 case vex_vsib_q_w_dq_mode
:
14827 oappend ("QWORD PTR ");
14829 oappend ("DWORD PTR ");
14833 switch (vex
.length
)
14836 oappend ("XMMWORD PTR ");
14839 oappend ("YMMWORD PTR ");
14842 oappend ("ZMMWORD PTR ");
14849 case vex_vsib_q_w_d_mode
:
14850 case vex_vsib_d_w_d_mode
:
14851 if (!need_vex
|| !vex
.evex
)
14854 switch (vex
.length
)
14857 oappend ("QWORD PTR ");
14860 oappend ("XMMWORD PTR ");
14863 oappend ("YMMWORD PTR ");
14871 if (!need_vex
|| vex
.length
!= 128)
14874 oappend ("DWORD PTR ");
14876 oappend ("BYTE PTR ");
14882 oappend ("QWORD PTR ");
14884 oappend ("WORD PTR ");
14893 OP_E_register (int bytemode
, int sizeflag
)
14895 int reg
= modrm
.rm
;
14896 const char **names
;
14902 if ((sizeflag
& SUFFIX_ALWAYS
)
14903 && (bytemode
== b_swap_mode
14904 || bytemode
== v_swap_mode
))
14930 names
= address_mode
== mode_64bit
? names64
: names32
;
14936 if (address_mode
== mode_64bit
&& isa64
== intel64
)
14941 /* Fall through. */
14943 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14949 /* Fall through. */
14961 if ((sizeflag
& DFLAG
)
14962 || (bytemode
!= v_mode
14963 && bytemode
!= v_swap_mode
))
14967 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14977 names
= names_mask
;
14982 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14985 oappend (names
[reg
]);
14989 OP_E_memory (int bytemode
, int sizeflag
)
14992 int add
= (rex
& REX_B
) ? 8 : 0;
14998 /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */
15000 && bytemode
!= x_mode
15001 && bytemode
!= xmmq_mode
15002 && bytemode
!= evex_half_bcst_xmmq_mode
)
15017 case vex_vsib_d_w_dq_mode
:
15018 case vex_vsib_d_w_d_mode
:
15019 case vex_vsib_q_w_dq_mode
:
15020 case vex_vsib_q_w_d_mode
:
15021 case evex_x_gscat_mode
:
15023 shift
= vex
.w
? 3 : 2;
15026 case evex_half_bcst_xmmq_mode
:
15030 shift
= vex
.w
? 3 : 2;
15033 /* Fall through. */
15037 case evex_x_nobcst_mode
:
15039 switch (vex
.length
)
15062 case q_scalar_mode
:
15064 case q_scalar_swap_mode
:
15070 case d_scalar_mode
:
15072 case d_scalar_swap_mode
:
15084 /* Make necessary corrections to shift for modes that need it.
15085 For these modes we currently have shift 4, 5 or 6 depending on
15086 vex.length (it corresponds to xmmword, ymmword or zmmword
15087 operand). We might want to make it 3, 4 or 5 (e.g. for
15088 xmmq_mode). In case of broadcast enabled the corrections
15089 aren't needed, as element size is always 32 or 64 bits. */
15091 && (bytemode
== xmmq_mode
15092 || bytemode
== evex_half_bcst_xmmq_mode
))
15094 else if (bytemode
== xmmqd_mode
)
15096 else if (bytemode
== xmmdw_mode
)
15098 else if (bytemode
== ymmq_mode
&& vex
.length
== 128)
15106 intel_operand_size (bytemode
, sizeflag
);
15109 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
15111 /* 32/64 bit address mode */
15120 int addr32flag
= !((sizeflag
& AFLAG
)
15121 || bytemode
== v_bnd_mode
15122 || bytemode
== bnd_mode
);
15123 const char **indexes64
= names64
;
15124 const char **indexes32
= names32
;
15134 vindex
= sib
.index
;
15140 case vex_vsib_d_w_dq_mode
:
15141 case vex_vsib_d_w_d_mode
:
15142 case vex_vsib_q_w_dq_mode
:
15143 case vex_vsib_q_w_d_mode
:
15153 switch (vex
.length
)
15156 indexes64
= indexes32
= names_xmm
;
15160 || bytemode
== vex_vsib_q_w_dq_mode
15161 || bytemode
== vex_vsib_q_w_d_mode
)
15162 indexes64
= indexes32
= names_ymm
;
15164 indexes64
= indexes32
= names_xmm
;
15168 || bytemode
== vex_vsib_q_w_dq_mode
15169 || bytemode
== vex_vsib_q_w_d_mode
)
15170 indexes64
= indexes32
= names_zmm
;
15172 indexes64
= indexes32
= names_ymm
;
15179 haveindex
= vindex
!= 4;
15186 rbase
= base
+ add
;
15194 if (address_mode
== mode_64bit
&& !havesib
)
15200 FETCH_DATA (the_info
, codep
+ 1);
15202 if ((disp
& 0x80) != 0)
15204 if (vex
.evex
&& shift
> 0)
15212 /* In 32bit mode, we need index register to tell [offset] from
15213 [eiz*1 + offset]. */
15214 needindex
= (havesib
15217 && address_mode
== mode_32bit
);
15218 havedisp
= (havebase
15220 || (havesib
&& (haveindex
|| scale
!= 0)));
15223 if (modrm
.mod
!= 0 || base
== 5)
15225 if (havedisp
|| riprel
)
15226 print_displacement (scratchbuf
, disp
);
15228 print_operand_value (scratchbuf
, 1, disp
);
15229 oappend (scratchbuf
);
15233 oappend (!addr32flag
? "(%rip)" : "(%eip)");
15237 if ((havebase
|| haveindex
|| riprel
)
15238 && (bytemode
!= v_bnd_mode
)
15239 && (bytemode
!= bnd_mode
))
15240 used_prefixes
|= PREFIX_ADDR
;
15242 if (havedisp
|| (intel_syntax
&& riprel
))
15244 *obufp
++ = open_char
;
15245 if (intel_syntax
&& riprel
)
15248 oappend (!addr32flag
? "rip" : "eip");
15252 oappend (address_mode
== mode_64bit
&& !addr32flag
15253 ? names64
[rbase
] : names32
[rbase
]);
15256 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
15257 print index to tell base + index from base. */
15261 || (havebase
&& base
!= ESP_REG_NUM
))
15263 if (!intel_syntax
|| havebase
)
15265 *obufp
++ = separator_char
;
15269 oappend (address_mode
== mode_64bit
&& !addr32flag
15270 ? indexes64
[vindex
] : indexes32
[vindex
]);
15272 oappend (address_mode
== mode_64bit
&& !addr32flag
15273 ? index64
: index32
);
15275 *obufp
++ = scale_char
;
15277 sprintf (scratchbuf
, "%d", 1 << scale
);
15278 oappend (scratchbuf
);
15282 && (disp
|| modrm
.mod
!= 0 || base
== 5))
15284 if (!havedisp
|| (bfd_signed_vma
) disp
>= 0)
15289 else if (modrm
.mod
!= 1 && disp
!= -disp
)
15293 disp
= - (bfd_signed_vma
) disp
;
15297 print_displacement (scratchbuf
, disp
);
15299 print_operand_value (scratchbuf
, 1, disp
);
15300 oappend (scratchbuf
);
15303 *obufp
++ = close_char
;
15306 else if (intel_syntax
)
15308 if (modrm
.mod
!= 0 || base
== 5)
15310 if (!active_seg_prefix
)
15312 oappend (names_seg
[ds_reg
- es_reg
]);
15315 print_operand_value (scratchbuf
, 1, disp
);
15316 oappend (scratchbuf
);
15322 /* 16 bit address mode */
15323 used_prefixes
|= prefixes
& PREFIX_ADDR
;
15330 if ((disp
& 0x8000) != 0)
15335 FETCH_DATA (the_info
, codep
+ 1);
15337 if ((disp
& 0x80) != 0)
15342 if ((disp
& 0x8000) != 0)
15348 if (modrm
.mod
!= 0 || modrm
.rm
== 6)
15350 print_displacement (scratchbuf
, disp
);
15351 oappend (scratchbuf
);
15354 if (modrm
.mod
!= 0 || modrm
.rm
!= 6)
15356 *obufp
++ = open_char
;
15358 oappend (index16
[modrm
.rm
]);
15360 && (disp
|| modrm
.mod
!= 0 || modrm
.rm
== 6))
15362 if ((bfd_signed_vma
) disp
>= 0)
15367 else if (modrm
.mod
!= 1)
15371 disp
= - (bfd_signed_vma
) disp
;
15374 print_displacement (scratchbuf
, disp
);
15375 oappend (scratchbuf
);
15378 *obufp
++ = close_char
;
15381 else if (intel_syntax
)
15383 if (!active_seg_prefix
)
15385 oappend (names_seg
[ds_reg
- es_reg
]);
15388 print_operand_value (scratchbuf
, 1, disp
& 0xffff);
15389 oappend (scratchbuf
);
15392 if (vex
.evex
&& vex
.b
15393 && (bytemode
== x_mode
15394 || bytemode
== xmmq_mode
15395 || bytemode
== evex_half_bcst_xmmq_mode
))
15398 || bytemode
== xmmq_mode
15399 || bytemode
== evex_half_bcst_xmmq_mode
)
15401 switch (vex
.length
)
15404 oappend ("{1to2}");
15407 oappend ("{1to4}");
15410 oappend ("{1to8}");
15418 switch (vex
.length
)
15421 oappend ("{1to4}");
15424 oappend ("{1to8}");
15427 oappend ("{1to16}");
15437 OP_E (int bytemode
, int sizeflag
)
15439 /* Skip mod/rm byte. */
15443 if (modrm
.mod
== 3)
15444 OP_E_register (bytemode
, sizeflag
);
15446 OP_E_memory (bytemode
, sizeflag
);
15450 OP_G (int bytemode
, int sizeflag
)
15461 oappend (names8rex
[modrm
.reg
+ add
]);
15463 oappend (names8
[modrm
.reg
+ add
]);
15466 oappend (names16
[modrm
.reg
+ add
]);
15471 oappend (names32
[modrm
.reg
+ add
]);
15474 oappend (names64
[modrm
.reg
+ add
]);
15477 oappend (names_bnd
[modrm
.reg
]);
15486 oappend (names64
[modrm
.reg
+ add
]);
15489 if ((sizeflag
& DFLAG
) || bytemode
!= v_mode
)
15490 oappend (names32
[modrm
.reg
+ add
]);
15492 oappend (names16
[modrm
.reg
+ add
]);
15493 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15497 if (address_mode
== mode_64bit
)
15498 oappend (names64
[modrm
.reg
+ add
]);
15500 oappend (names32
[modrm
.reg
+ add
]);
15504 if ((modrm
.reg
+ add
) > 0x7)
15509 oappend (names_mask
[modrm
.reg
+ add
]);
15512 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15525 FETCH_DATA (the_info
, codep
+ 8);
15526 a
= *codep
++ & 0xff;
15527 a
|= (*codep
++ & 0xff) << 8;
15528 a
|= (*codep
++ & 0xff) << 16;
15529 a
|= (*codep
++ & 0xffu
) << 24;
15530 b
= *codep
++ & 0xff;
15531 b
|= (*codep
++ & 0xff) << 8;
15532 b
|= (*codep
++ & 0xff) << 16;
15533 b
|= (*codep
++ & 0xffu
) << 24;
15534 x
= a
+ ((bfd_vma
) b
<< 32);
15542 static bfd_signed_vma
15545 bfd_signed_vma x
= 0;
15547 FETCH_DATA (the_info
, codep
+ 4);
15548 x
= *codep
++ & (bfd_signed_vma
) 0xff;
15549 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
15550 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
15551 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
15555 static bfd_signed_vma
15558 bfd_signed_vma x
= 0;
15560 FETCH_DATA (the_info
, codep
+ 4);
15561 x
= *codep
++ & (bfd_signed_vma
) 0xff;
15562 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
15563 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
15564 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
15566 x
= (x
^ ((bfd_signed_vma
) 1 << 31)) - ((bfd_signed_vma
) 1 << 31);
15576 FETCH_DATA (the_info
, codep
+ 2);
15577 x
= *codep
++ & 0xff;
15578 x
|= (*codep
++ & 0xff) << 8;
15583 set_op (bfd_vma op
, int riprel
)
15585 op_index
[op_ad
] = op_ad
;
15586 if (address_mode
== mode_64bit
)
15588 op_address
[op_ad
] = op
;
15589 op_riprel
[op_ad
] = riprel
;
15593 /* Mask to get a 32-bit address. */
15594 op_address
[op_ad
] = op
& 0xffffffff;
15595 op_riprel
[op_ad
] = riprel
& 0xffffffff;
15600 OP_REG (int code
, int sizeflag
)
15607 case es_reg
: case ss_reg
: case cs_reg
:
15608 case ds_reg
: case fs_reg
: case gs_reg
:
15609 oappend (names_seg
[code
- es_reg
]);
15621 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
15622 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
15623 s
= names16
[code
- ax_reg
+ add
];
15625 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
15626 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
15629 s
= names8rex
[code
- al_reg
+ add
];
15631 s
= names8
[code
- al_reg
];
15633 case rAX_reg
: case rCX_reg
: case rDX_reg
: case rBX_reg
:
15634 case rSP_reg
: case rBP_reg
: case rSI_reg
: case rDI_reg
:
15635 if (address_mode
== mode_64bit
15636 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
15638 s
= names64
[code
- rAX_reg
+ add
];
15641 code
+= eAX_reg
- rAX_reg
;
15642 /* Fall through. */
15643 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
15644 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
15647 s
= names64
[code
- eAX_reg
+ add
];
15650 if (sizeflag
& DFLAG
)
15651 s
= names32
[code
- eAX_reg
+ add
];
15653 s
= names16
[code
- eAX_reg
+ add
];
15654 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15658 s
= INTERNAL_DISASSEMBLER_ERROR
;
15665 OP_IMREG (int code
, int sizeflag
)
15677 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
15678 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
15679 s
= names16
[code
- ax_reg
];
15681 case es_reg
: case ss_reg
: case cs_reg
:
15682 case ds_reg
: case fs_reg
: case gs_reg
:
15683 s
= names_seg
[code
- es_reg
];
15685 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
15686 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
15689 s
= names8rex
[code
- al_reg
];
15691 s
= names8
[code
- al_reg
];
15693 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
15694 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
15697 s
= names64
[code
- eAX_reg
];
15700 if (sizeflag
& DFLAG
)
15701 s
= names32
[code
- eAX_reg
];
15703 s
= names16
[code
- eAX_reg
];
15704 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15707 case z_mode_ax_reg
:
15708 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
15712 if (!(rex
& REX_W
))
15713 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15716 s
= INTERNAL_DISASSEMBLER_ERROR
;
15723 OP_I (int bytemode
, int sizeflag
)
15726 bfd_signed_vma mask
= -1;
15731 FETCH_DATA (the_info
, codep
+ 1);
15736 if (address_mode
== mode_64bit
)
15741 /* Fall through. */
15748 if (sizeflag
& DFLAG
)
15758 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15770 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15775 scratchbuf
[0] = '$';
15776 print_operand_value (scratchbuf
+ 1, 1, op
);
15777 oappend_maybe_intel (scratchbuf
);
15778 scratchbuf
[0] = '\0';
15782 OP_I64 (int bytemode
, int sizeflag
)
15785 bfd_signed_vma mask
= -1;
15787 if (address_mode
!= mode_64bit
)
15789 OP_I (bytemode
, sizeflag
);
15796 FETCH_DATA (the_info
, codep
+ 1);
15806 if (sizeflag
& DFLAG
)
15816 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15824 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15829 scratchbuf
[0] = '$';
15830 print_operand_value (scratchbuf
+ 1, 1, op
);
15831 oappend_maybe_intel (scratchbuf
);
15832 scratchbuf
[0] = '\0';
15836 OP_sI (int bytemode
, int sizeflag
)
15844 FETCH_DATA (the_info
, codep
+ 1);
15846 if ((op
& 0x80) != 0)
15848 if (bytemode
== b_T_mode
)
15850 if (address_mode
!= mode_64bit
15851 || !((sizeflag
& DFLAG
) || (rex
& REX_W
)))
15853 /* The operand-size prefix is overridden by a REX prefix. */
15854 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
15862 if (!(rex
& REX_W
))
15864 if (sizeflag
& DFLAG
)
15872 /* The operand-size prefix is overridden by a REX prefix. */
15873 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
15879 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15883 scratchbuf
[0] = '$';
15884 print_operand_value (scratchbuf
+ 1, 1, op
);
15885 oappend_maybe_intel (scratchbuf
);
15889 OP_J (int bytemode
, int sizeflag
)
15893 bfd_vma segment
= 0;
15898 FETCH_DATA (the_info
, codep
+ 1);
15900 if ((disp
& 0x80) != 0)
15904 if (isa64
== amd64
)
15906 if ((sizeflag
& DFLAG
)
15907 || (address_mode
== mode_64bit
15908 && (isa64
!= amd64
|| (rex
& REX_W
))))
15913 if ((disp
& 0x8000) != 0)
15915 /* In 16bit mode, address is wrapped around at 64k within
15916 the same segment. Otherwise, a data16 prefix on a jump
15917 instruction means that the pc is masked to 16 bits after
15918 the displacement is added! */
15920 if ((prefixes
& PREFIX_DATA
) == 0)
15921 segment
= ((start_pc
+ (codep
- start_codep
))
15922 & ~((bfd_vma
) 0xffff));
15924 if (address_mode
!= mode_64bit
15925 || (isa64
== amd64
&& !(rex
& REX_W
)))
15926 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15929 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15932 disp
= ((start_pc
+ (codep
- start_codep
) + disp
) & mask
) | segment
;
15934 print_operand_value (scratchbuf
, 1, disp
);
15935 oappend (scratchbuf
);
15939 OP_SEG (int bytemode
, int sizeflag
)
15941 if (bytemode
== w_mode
)
15942 oappend (names_seg
[modrm
.reg
]);
15944 OP_E (modrm
.mod
== 3 ? bytemode
: w_mode
, sizeflag
);
15948 OP_DIR (int dummy ATTRIBUTE_UNUSED
, int sizeflag
)
15952 if (sizeflag
& DFLAG
)
15962 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15964 sprintf (scratchbuf
, "0x%x:0x%x", seg
, offset
);
15966 sprintf (scratchbuf
, "$0x%x,$0x%x", seg
, offset
);
15967 oappend (scratchbuf
);
15971 OP_OFF (int bytemode
, int sizeflag
)
15975 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
15976 intel_operand_size (bytemode
, sizeflag
);
15979 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
15986 if (!active_seg_prefix
)
15988 oappend (names_seg
[ds_reg
- es_reg
]);
15992 print_operand_value (scratchbuf
, 1, off
);
15993 oappend (scratchbuf
);
15997 OP_OFF64 (int bytemode
, int sizeflag
)
16001 if (address_mode
!= mode_64bit
16002 || (prefixes
& PREFIX_ADDR
))
16004 OP_OFF (bytemode
, sizeflag
);
16008 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
16009 intel_operand_size (bytemode
, sizeflag
);
16016 if (!active_seg_prefix
)
16018 oappend (names_seg
[ds_reg
- es_reg
]);
16022 print_operand_value (scratchbuf
, 1, off
);
16023 oappend (scratchbuf
);
16027 ptr_reg (int code
, int sizeflag
)
16031 *obufp
++ = open_char
;
16032 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
16033 if (address_mode
== mode_64bit
)
16035 if (!(sizeflag
& AFLAG
))
16036 s
= names32
[code
- eAX_reg
];
16038 s
= names64
[code
- eAX_reg
];
16040 else if (sizeflag
& AFLAG
)
16041 s
= names32
[code
- eAX_reg
];
16043 s
= names16
[code
- eAX_reg
];
16045 *obufp
++ = close_char
;
16050 OP_ESreg (int code
, int sizeflag
)
16056 case 0x6d: /* insw/insl */
16057 intel_operand_size (z_mode
, sizeflag
);
16059 case 0xa5: /* movsw/movsl/movsq */
16060 case 0xa7: /* cmpsw/cmpsl/cmpsq */
16061 case 0xab: /* stosw/stosl */
16062 case 0xaf: /* scasw/scasl */
16063 intel_operand_size (v_mode
, sizeflag
);
16066 intel_operand_size (b_mode
, sizeflag
);
16069 oappend_maybe_intel ("%es:");
16070 ptr_reg (code
, sizeflag
);
16074 OP_DSreg (int code
, int sizeflag
)
16080 case 0x6f: /* outsw/outsl */
16081 intel_operand_size (z_mode
, sizeflag
);
16083 case 0xa5: /* movsw/movsl/movsq */
16084 case 0xa7: /* cmpsw/cmpsl/cmpsq */
16085 case 0xad: /* lodsw/lodsl/lodsq */
16086 intel_operand_size (v_mode
, sizeflag
);
16089 intel_operand_size (b_mode
, sizeflag
);
16092 /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
16093 default segment register DS is printed. */
16094 if (!active_seg_prefix
)
16095 active_seg_prefix
= PREFIX_DS
;
16097 ptr_reg (code
, sizeflag
);
16101 OP_C (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16109 else if (address_mode
!= mode_64bit
&& (prefixes
& PREFIX_LOCK
))
16111 all_prefixes
[last_lock_prefix
] = 0;
16112 used_prefixes
|= PREFIX_LOCK
;
16117 sprintf (scratchbuf
, "%%cr%d", modrm
.reg
+ add
);
16118 oappend_maybe_intel (scratchbuf
);
16122 OP_D (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16131 sprintf (scratchbuf
, "db%d", modrm
.reg
+ add
);
16133 sprintf (scratchbuf
, "%%db%d", modrm
.reg
+ add
);
16134 oappend (scratchbuf
);
16138 OP_T (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16140 sprintf (scratchbuf
, "%%tr%d", modrm
.reg
);
16141 oappend_maybe_intel (scratchbuf
);
16145 OP_R (int bytemode
, int sizeflag
)
16147 /* Skip mod/rm byte. */
16150 OP_E_register (bytemode
, sizeflag
);
16154 OP_MMX (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16156 int reg
= modrm
.reg
;
16157 const char **names
;
16159 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16160 if (prefixes
& PREFIX_DATA
)
16169 oappend (names
[reg
]);
16173 OP_XMM (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16175 int reg
= modrm
.reg
;
16176 const char **names
;
16188 && bytemode
!= xmm_mode
16189 && bytemode
!= xmmq_mode
16190 && bytemode
!= evex_half_bcst_xmmq_mode
16191 && bytemode
!= ymm_mode
16192 && bytemode
!= scalar_mode
)
16194 switch (vex
.length
)
16201 || (bytemode
!= vex_vsib_q_w_dq_mode
16202 && bytemode
!= vex_vsib_q_w_d_mode
))
16214 else if (bytemode
== xmmq_mode
16215 || bytemode
== evex_half_bcst_xmmq_mode
)
16217 switch (vex
.length
)
16230 else if (bytemode
== ymm_mode
)
16234 oappend (names
[reg
]);
16238 OP_EM (int bytemode
, int sizeflag
)
16241 const char **names
;
16243 if (modrm
.mod
!= 3)
16246 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
16248 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
16249 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16251 OP_E (bytemode
, sizeflag
);
16255 if ((sizeflag
& SUFFIX_ALWAYS
) && bytemode
== v_swap_mode
)
16258 /* Skip mod/rm byte. */
16261 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16263 if (prefixes
& PREFIX_DATA
)
16272 oappend (names
[reg
]);
16275 /* cvt* are the only instructions in sse2 which have
16276 both SSE and MMX operands and also have 0x66 prefix
16277 in their opcode. 0x66 was originally used to differentiate
16278 between SSE and MMX instruction(operands). So we have to handle the
16279 cvt* separately using OP_EMC and OP_MXC */
16281 OP_EMC (int bytemode
, int sizeflag
)
16283 if (modrm
.mod
!= 3)
16285 if (intel_syntax
&& bytemode
== v_mode
)
16287 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
16288 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16290 OP_E (bytemode
, sizeflag
);
16294 /* Skip mod/rm byte. */
16297 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16298 oappend (names_mm
[modrm
.rm
]);
16302 OP_MXC (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16304 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16305 oappend (names_mm
[modrm
.reg
]);
16309 OP_EX (int bytemode
, int sizeflag
)
16312 const char **names
;
16314 /* Skip mod/rm byte. */
16318 if (modrm
.mod
!= 3)
16320 OP_E_memory (bytemode
, sizeflag
);
16335 if ((sizeflag
& SUFFIX_ALWAYS
)
16336 && (bytemode
== x_swap_mode
16337 || bytemode
== d_swap_mode
16338 || bytemode
== d_scalar_swap_mode
16339 || bytemode
== q_swap_mode
16340 || bytemode
== q_scalar_swap_mode
))
16344 && bytemode
!= xmm_mode
16345 && bytemode
!= xmmdw_mode
16346 && bytemode
!= xmmqd_mode
16347 && bytemode
!= xmm_mb_mode
16348 && bytemode
!= xmm_mw_mode
16349 && bytemode
!= xmm_md_mode
16350 && bytemode
!= xmm_mq_mode
16351 && bytemode
!= xmm_mdq_mode
16352 && bytemode
!= xmmq_mode
16353 && bytemode
!= evex_half_bcst_xmmq_mode
16354 && bytemode
!= ymm_mode
16355 && bytemode
!= d_scalar_mode
16356 && bytemode
!= d_scalar_swap_mode
16357 && bytemode
!= q_scalar_mode
16358 && bytemode
!= q_scalar_swap_mode
16359 && bytemode
!= vex_scalar_w_dq_mode
)
16361 switch (vex
.length
)
16376 else if (bytemode
== xmmq_mode
16377 || bytemode
== evex_half_bcst_xmmq_mode
)
16379 switch (vex
.length
)
16392 else if (bytemode
== ymm_mode
)
16396 oappend (names
[reg
]);
16400 OP_MS (int bytemode
, int sizeflag
)
16402 if (modrm
.mod
== 3)
16403 OP_EM (bytemode
, sizeflag
);
16409 OP_XS (int bytemode
, int sizeflag
)
16411 if (modrm
.mod
== 3)
16412 OP_EX (bytemode
, sizeflag
);
16418 OP_M (int bytemode
, int sizeflag
)
16420 if (modrm
.mod
== 3)
16421 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
16424 OP_E (bytemode
, sizeflag
);
16428 OP_0f07 (int bytemode
, int sizeflag
)
16430 if (modrm
.mod
!= 3 || modrm
.rm
!= 0)
16433 OP_E (bytemode
, sizeflag
);
16436 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
16437 32bit mode and "xchg %rax,%rax" in 64bit mode. */
16440 NOP_Fixup1 (int bytemode
, int sizeflag
)
16442 if ((prefixes
& PREFIX_DATA
) != 0
16445 && address_mode
== mode_64bit
))
16446 OP_REG (bytemode
, sizeflag
);
16448 strcpy (obuf
, "nop");
16452 NOP_Fixup2 (int bytemode
, int sizeflag
)
16454 if ((prefixes
& PREFIX_DATA
) != 0
16457 && address_mode
== mode_64bit
))
16458 OP_IMREG (bytemode
, sizeflag
);
16461 static const char *const Suffix3DNow
[] = {
16462 /* 00 */ NULL
, NULL
, NULL
, NULL
,
16463 /* 04 */ NULL
, NULL
, NULL
, NULL
,
16464 /* 08 */ NULL
, NULL
, NULL
, NULL
,
16465 /* 0C */ "pi2fw", "pi2fd", NULL
, NULL
,
16466 /* 10 */ NULL
, NULL
, NULL
, NULL
,
16467 /* 14 */ NULL
, NULL
, NULL
, NULL
,
16468 /* 18 */ NULL
, NULL
, NULL
, NULL
,
16469 /* 1C */ "pf2iw", "pf2id", NULL
, NULL
,
16470 /* 20 */ NULL
, NULL
, NULL
, NULL
,
16471 /* 24 */ NULL
, NULL
, NULL
, NULL
,
16472 /* 28 */ NULL
, NULL
, NULL
, NULL
,
16473 /* 2C */ NULL
, NULL
, NULL
, NULL
,
16474 /* 30 */ NULL
, NULL
, NULL
, NULL
,
16475 /* 34 */ NULL
, NULL
, NULL
, NULL
,
16476 /* 38 */ NULL
, NULL
, NULL
, NULL
,
16477 /* 3C */ NULL
, NULL
, NULL
, NULL
,
16478 /* 40 */ NULL
, NULL
, NULL
, NULL
,
16479 /* 44 */ NULL
, NULL
, NULL
, NULL
,
16480 /* 48 */ NULL
, NULL
, NULL
, NULL
,
16481 /* 4C */ NULL
, NULL
, NULL
, NULL
,
16482 /* 50 */ NULL
, NULL
, NULL
, NULL
,
16483 /* 54 */ NULL
, NULL
, NULL
, NULL
,
16484 /* 58 */ NULL
, NULL
, NULL
, NULL
,
16485 /* 5C */ NULL
, NULL
, NULL
, NULL
,
16486 /* 60 */ NULL
, NULL
, NULL
, NULL
,
16487 /* 64 */ NULL
, NULL
, NULL
, NULL
,
16488 /* 68 */ NULL
, NULL
, NULL
, NULL
,
16489 /* 6C */ NULL
, NULL
, NULL
, NULL
,
16490 /* 70 */ NULL
, NULL
, NULL
, NULL
,
16491 /* 74 */ NULL
, NULL
, NULL
, NULL
,
16492 /* 78 */ NULL
, NULL
, NULL
, NULL
,
16493 /* 7C */ NULL
, NULL
, NULL
, NULL
,
16494 /* 80 */ NULL
, NULL
, NULL
, NULL
,
16495 /* 84 */ NULL
, NULL
, NULL
, NULL
,
16496 /* 88 */ NULL
, NULL
, "pfnacc", NULL
,
16497 /* 8C */ NULL
, NULL
, "pfpnacc", NULL
,
16498 /* 90 */ "pfcmpge", NULL
, NULL
, NULL
,
16499 /* 94 */ "pfmin", NULL
, "pfrcp", "pfrsqrt",
16500 /* 98 */ NULL
, NULL
, "pfsub", NULL
,
16501 /* 9C */ NULL
, NULL
, "pfadd", NULL
,
16502 /* A0 */ "pfcmpgt", NULL
, NULL
, NULL
,
16503 /* A4 */ "pfmax", NULL
, "pfrcpit1", "pfrsqit1",
16504 /* A8 */ NULL
, NULL
, "pfsubr", NULL
,
16505 /* AC */ NULL
, NULL
, "pfacc", NULL
,
16506 /* B0 */ "pfcmpeq", NULL
, NULL
, NULL
,
16507 /* B4 */ "pfmul", NULL
, "pfrcpit2", "pmulhrw",
16508 /* B8 */ NULL
, NULL
, NULL
, "pswapd",
16509 /* BC */ NULL
, NULL
, NULL
, "pavgusb",
16510 /* C0 */ NULL
, NULL
, NULL
, NULL
,
16511 /* C4 */ NULL
, NULL
, NULL
, NULL
,
16512 /* C8 */ NULL
, NULL
, NULL
, NULL
,
16513 /* CC */ NULL
, NULL
, NULL
, NULL
,
16514 /* D0 */ NULL
, NULL
, NULL
, NULL
,
16515 /* D4 */ NULL
, NULL
, NULL
, NULL
,
16516 /* D8 */ NULL
, NULL
, NULL
, NULL
,
16517 /* DC */ NULL
, NULL
, NULL
, NULL
,
16518 /* E0 */ NULL
, NULL
, NULL
, NULL
,
16519 /* E4 */ NULL
, NULL
, NULL
, NULL
,
16520 /* E8 */ NULL
, NULL
, NULL
, NULL
,
16521 /* EC */ NULL
, NULL
, NULL
, NULL
,
16522 /* F0 */ NULL
, NULL
, NULL
, NULL
,
16523 /* F4 */ NULL
, NULL
, NULL
, NULL
,
16524 /* F8 */ NULL
, NULL
, NULL
, NULL
,
16525 /* FC */ NULL
, NULL
, NULL
, NULL
,
16529 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16531 const char *mnemonic
;
16533 FETCH_DATA (the_info
, codep
+ 1);
16534 /* AMD 3DNow! instructions are specified by an opcode suffix in the
16535 place where an 8-bit immediate would normally go. ie. the last
16536 byte of the instruction. */
16537 obufp
= mnemonicendp
;
16538 mnemonic
= Suffix3DNow
[*codep
++ & 0xff];
16540 oappend (mnemonic
);
16543 /* Since a variable sized modrm/sib chunk is between the start
16544 of the opcode (0x0f0f) and the opcode suffix, we need to do
16545 all the modrm processing first, and don't know until now that
16546 we have a bad opcode. This necessitates some cleaning up. */
16547 op_out
[0][0] = '\0';
16548 op_out
[1][0] = '\0';
16551 mnemonicendp
= obufp
;
16554 static struct op simd_cmp_op
[] =
16556 { STRING_COMMA_LEN ("eq") },
16557 { STRING_COMMA_LEN ("lt") },
16558 { STRING_COMMA_LEN ("le") },
16559 { STRING_COMMA_LEN ("unord") },
16560 { STRING_COMMA_LEN ("neq") },
16561 { STRING_COMMA_LEN ("nlt") },
16562 { STRING_COMMA_LEN ("nle") },
16563 { STRING_COMMA_LEN ("ord") }
16567 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16569 unsigned int cmp_type
;
16571 FETCH_DATA (the_info
, codep
+ 1);
16572 cmp_type
= *codep
++ & 0xff;
16573 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
))
16576 char *p
= mnemonicendp
- 2;
16580 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
16581 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
16585 /* We have a reserved extension byte. Output it directly. */
16586 scratchbuf
[0] = '$';
16587 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16588 oappend_maybe_intel (scratchbuf
);
16589 scratchbuf
[0] = '\0';
16594 OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED
,
16595 int sizeflag ATTRIBUTE_UNUSED
)
16597 /* mwaitx %eax,%ecx,%ebx */
16600 const char **names
= (address_mode
== mode_64bit
16601 ? names64
: names32
);
16602 strcpy (op_out
[0], names
[0]);
16603 strcpy (op_out
[1], names
[1]);
16604 strcpy (op_out
[2], names
[3]);
16605 two_source_ops
= 1;
16607 /* Skip mod/rm byte. */
16613 OP_Mwait (int bytemode ATTRIBUTE_UNUSED
,
16614 int sizeflag ATTRIBUTE_UNUSED
)
16616 /* mwait %eax,%ecx */
16619 const char **names
= (address_mode
== mode_64bit
16620 ? names64
: names32
);
16621 strcpy (op_out
[0], names
[0]);
16622 strcpy (op_out
[1], names
[1]);
16623 two_source_ops
= 1;
16625 /* Skip mod/rm byte. */
16631 OP_Monitor (int bytemode ATTRIBUTE_UNUSED
,
16632 int sizeflag ATTRIBUTE_UNUSED
)
16634 /* monitor %eax,%ecx,%edx" */
16637 const char **op1_names
;
16638 const char **names
= (address_mode
== mode_64bit
16639 ? names64
: names32
);
16641 if (!(prefixes
& PREFIX_ADDR
))
16642 op1_names
= (address_mode
== mode_16bit
16643 ? names16
: names
);
16646 /* Remove "addr16/addr32". */
16647 all_prefixes
[last_addr_prefix
] = 0;
16648 op1_names
= (address_mode
!= mode_32bit
16649 ? names32
: names16
);
16650 used_prefixes
|= PREFIX_ADDR
;
16652 strcpy (op_out
[0], op1_names
[0]);
16653 strcpy (op_out
[1], names
[1]);
16654 strcpy (op_out
[2], names
[2]);
16655 two_source_ops
= 1;
16657 /* Skip mod/rm byte. */
16665 /* Throw away prefixes and 1st. opcode byte. */
16666 codep
= insn_codep
+ 1;
16671 REP_Fixup (int bytemode
, int sizeflag
)
16673 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
16675 if (prefixes
& PREFIX_REPZ
)
16676 all_prefixes
[last_repz_prefix
] = REP_PREFIX
;
16683 OP_IMREG (bytemode
, sizeflag
);
16686 OP_ESreg (bytemode
, sizeflag
);
16689 OP_DSreg (bytemode
, sizeflag
);
16697 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
16701 BND_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16703 if (prefixes
& PREFIX_REPNZ
)
16704 all_prefixes
[last_repnz_prefix
] = BND_PREFIX
;
16707 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
16708 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
16712 HLE_Fixup1 (int bytemode
, int sizeflag
)
16715 && (prefixes
& PREFIX_LOCK
) != 0)
16717 if (prefixes
& PREFIX_REPZ
)
16718 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
16719 if (prefixes
& PREFIX_REPNZ
)
16720 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
16723 OP_E (bytemode
, sizeflag
);
16726 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
16727 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
16731 HLE_Fixup2 (int bytemode
, int sizeflag
)
16733 if (modrm
.mod
!= 3)
16735 if (prefixes
& PREFIX_REPZ
)
16736 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
16737 if (prefixes
& PREFIX_REPNZ
)
16738 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
16741 OP_E (bytemode
, sizeflag
);
16744 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
16745 "xrelease" for memory operand. No check for LOCK prefix. */
16748 HLE_Fixup3 (int bytemode
, int sizeflag
)
16751 && last_repz_prefix
> last_repnz_prefix
16752 && (prefixes
& PREFIX_REPZ
) != 0)
16753 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
16755 OP_E (bytemode
, sizeflag
);
16759 CMPXCHG8B_Fixup (int bytemode
, int sizeflag
)
16764 /* Change cmpxchg8b to cmpxchg16b. */
16765 char *p
= mnemonicendp
- 2;
16766 mnemonicendp
= stpcpy (p
, "16b");
16769 else if ((prefixes
& PREFIX_LOCK
) != 0)
16771 if (prefixes
& PREFIX_REPZ
)
16772 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
16773 if (prefixes
& PREFIX_REPNZ
)
16774 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
16777 OP_M (bytemode
, sizeflag
);
16781 XMM_Fixup (int reg
, int sizeflag ATTRIBUTE_UNUSED
)
16783 const char **names
;
16787 switch (vex
.length
)
16801 oappend (names
[reg
]);
16805 CRC32_Fixup (int bytemode
, int sizeflag
)
16807 /* Add proper suffix to "crc32". */
16808 char *p
= mnemonicendp
;
16827 if (sizeflag
& DFLAG
)
16831 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16835 oappend (INTERNAL_DISASSEMBLER_ERROR
);
16842 if (modrm
.mod
== 3)
16846 /* Skip mod/rm byte. */
16851 add
= (rex
& REX_B
) ? 8 : 0;
16852 if (bytemode
== b_mode
)
16856 oappend (names8rex
[modrm
.rm
+ add
]);
16858 oappend (names8
[modrm
.rm
+ add
]);
16864 oappend (names64
[modrm
.rm
+ add
]);
16865 else if ((prefixes
& PREFIX_DATA
))
16866 oappend (names16
[modrm
.rm
+ add
]);
16868 oappend (names32
[modrm
.rm
+ add
]);
16872 OP_E (bytemode
, sizeflag
);
16876 FXSAVE_Fixup (int bytemode
, int sizeflag
)
16878 /* Add proper suffix to "fxsave" and "fxrstor". */
16882 char *p
= mnemonicendp
;
16888 OP_M (bytemode
, sizeflag
);
16892 PCMPESTR_Fixup (int bytemode
, int sizeflag
)
16894 /* Add proper suffix to "{,v}pcmpestr{i,m}". */
16897 char *p
= mnemonicendp
;
16902 else if (sizeflag
& SUFFIX_ALWAYS
)
16909 OP_EX (bytemode
, sizeflag
);
16912 /* Display the destination register operand for instructions with
16916 OP_VEX (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16919 const char **names
;
16927 reg
= vex
.register_specifier
;
16934 if (bytemode
== vex_scalar_mode
)
16936 oappend (names_xmm
[reg
]);
16940 switch (vex
.length
)
16947 case vex_vsib_q_w_dq_mode
:
16948 case vex_vsib_q_w_d_mode
:
16964 names
= names_mask
;
16978 case vex_vsib_q_w_dq_mode
:
16979 case vex_vsib_q_w_d_mode
:
16980 names
= vex
.w
? names_ymm
: names_xmm
;
16989 names
= names_mask
;
16992 /* See PR binutils/20893 for a reproducer. */
17004 oappend (names
[reg
]);
17007 /* Get the VEX immediate byte without moving codep. */
17009 static unsigned char
17010 get_vex_imm8 (int sizeflag
, int opnum
)
17012 int bytes_before_imm
= 0;
17014 if (modrm
.mod
!= 3)
17016 /* There are SIB/displacement bytes. */
17017 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
17019 /* 32/64 bit address mode */
17020 int base
= modrm
.rm
;
17022 /* Check SIB byte. */
17025 FETCH_DATA (the_info
, codep
+ 1);
17027 /* When decoding the third source, don't increase
17028 bytes_before_imm as this has already been incremented
17029 by one in OP_E_memory while decoding the second
17032 bytes_before_imm
++;
17035 /* Don't increase bytes_before_imm when decoding the third source,
17036 it has already been incremented by OP_E_memory while decoding
17037 the second source operand. */
17043 /* When modrm.rm == 5 or modrm.rm == 4 and base in
17044 SIB == 5, there is a 4 byte displacement. */
17046 /* No displacement. */
17048 /* Fall through. */
17050 /* 4 byte displacement. */
17051 bytes_before_imm
+= 4;
17054 /* 1 byte displacement. */
17055 bytes_before_imm
++;
17062 /* 16 bit address mode */
17063 /* Don't increase bytes_before_imm when decoding the third source,
17064 it has already been incremented by OP_E_memory while decoding
17065 the second source operand. */
17071 /* When modrm.rm == 6, there is a 2 byte displacement. */
17073 /* No displacement. */
17075 /* Fall through. */
17077 /* 2 byte displacement. */
17078 bytes_before_imm
+= 2;
17081 /* 1 byte displacement: when decoding the third source,
17082 don't increase bytes_before_imm as this has already
17083 been incremented by one in OP_E_memory while decoding
17084 the second source operand. */
17086 bytes_before_imm
++;
17094 FETCH_DATA (the_info
, codep
+ bytes_before_imm
+ 1);
17095 return codep
[bytes_before_imm
];
17099 OP_EX_VexReg (int bytemode
, int sizeflag
, int reg
)
17101 const char **names
;
17103 if (reg
== -1 && modrm
.mod
!= 3)
17105 OP_E_memory (bytemode
, sizeflag
);
17117 else if (reg
> 7 && address_mode
!= mode_64bit
)
17121 switch (vex
.length
)
17132 oappend (names
[reg
]);
17136 OP_EX_VexImmW (int bytemode
, int sizeflag
)
17139 static unsigned char vex_imm8
;
17141 if (vex_w_done
== 0)
17145 /* Skip mod/rm byte. */
17149 vex_imm8
= get_vex_imm8 (sizeflag
, 0);
17152 reg
= vex_imm8
>> 4;
17154 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
17156 else if (vex_w_done
== 1)
17161 reg
= vex_imm8
>> 4;
17163 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
17167 /* Output the imm8 directly. */
17168 scratchbuf
[0] = '$';
17169 print_operand_value (scratchbuf
+ 1, 1, vex_imm8
& 0xf);
17170 oappend_maybe_intel (scratchbuf
);
17171 scratchbuf
[0] = '\0';
17177 OP_Vex_2src (int bytemode
, int sizeflag
)
17179 if (modrm
.mod
== 3)
17181 int reg
= modrm
.rm
;
17185 oappend (names_xmm
[reg
]);
17190 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
17192 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
17193 used_prefixes
|= (prefixes
& PREFIX_DATA
);
17195 OP_E (bytemode
, sizeflag
);
17200 OP_Vex_2src_1 (int bytemode
, int sizeflag
)
17202 if (modrm
.mod
== 3)
17204 /* Skip mod/rm byte. */
17210 oappend (names_xmm
[vex
.register_specifier
]);
17212 OP_Vex_2src (bytemode
, sizeflag
);
17216 OP_Vex_2src_2 (int bytemode
, int sizeflag
)
17219 OP_Vex_2src (bytemode
, sizeflag
);
17221 oappend (names_xmm
[vex
.register_specifier
]);
17225 OP_EX_VexW (int bytemode
, int sizeflag
)
17233 /* Skip mod/rm byte. */
17238 reg
= get_vex_imm8 (sizeflag
, 0) >> 4;
17243 reg
= get_vex_imm8 (sizeflag
, 1) >> 4;
17246 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
17250 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED
,
17251 int sizeflag ATTRIBUTE_UNUSED
)
17253 /* Skip the immediate byte and check for invalid bits. */
17254 FETCH_DATA (the_info
, codep
+ 1);
17255 if (*codep
++ & 0xf)
17260 OP_REG_VexI4 (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
17263 const char **names
;
17265 FETCH_DATA (the_info
, codep
+ 1);
17268 if (bytemode
!= x_mode
)
17275 if (reg
> 7 && address_mode
!= mode_64bit
)
17278 switch (vex
.length
)
17289 oappend (names
[reg
]);
17293 OP_XMM_VexW (int bytemode
, int sizeflag
)
17295 /* Turn off the REX.W bit since it is used for swapping operands
17298 OP_XMM (bytemode
, sizeflag
);
17302 OP_EX_Vex (int bytemode
, int sizeflag
)
17304 if (modrm
.mod
!= 3)
17306 if (vex
.register_specifier
!= 0)
17310 OP_EX (bytemode
, sizeflag
);
17314 OP_XMM_Vex (int bytemode
, int sizeflag
)
17316 if (modrm
.mod
!= 3)
17318 if (vex
.register_specifier
!= 0)
17322 OP_XMM (bytemode
, sizeflag
);
17326 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
17328 switch (vex
.length
)
17331 mnemonicendp
= stpcpy (obuf
, "vzeroupper");
17334 mnemonicendp
= stpcpy (obuf
, "vzeroall");
17341 static struct op vex_cmp_op
[] =
17343 { STRING_COMMA_LEN ("eq") },
17344 { STRING_COMMA_LEN ("lt") },
17345 { STRING_COMMA_LEN ("le") },
17346 { STRING_COMMA_LEN ("unord") },
17347 { STRING_COMMA_LEN ("neq") },
17348 { STRING_COMMA_LEN ("nlt") },
17349 { STRING_COMMA_LEN ("nle") },
17350 { STRING_COMMA_LEN ("ord") },
17351 { STRING_COMMA_LEN ("eq_uq") },
17352 { STRING_COMMA_LEN ("nge") },
17353 { STRING_COMMA_LEN ("ngt") },
17354 { STRING_COMMA_LEN ("false") },
17355 { STRING_COMMA_LEN ("neq_oq") },
17356 { STRING_COMMA_LEN ("ge") },
17357 { STRING_COMMA_LEN ("gt") },
17358 { STRING_COMMA_LEN ("true") },
17359 { STRING_COMMA_LEN ("eq_os") },
17360 { STRING_COMMA_LEN ("lt_oq") },
17361 { STRING_COMMA_LEN ("le_oq") },
17362 { STRING_COMMA_LEN ("unord_s") },
17363 { STRING_COMMA_LEN ("neq_us") },
17364 { STRING_COMMA_LEN ("nlt_uq") },
17365 { STRING_COMMA_LEN ("nle_uq") },
17366 { STRING_COMMA_LEN ("ord_s") },
17367 { STRING_COMMA_LEN ("eq_us") },
17368 { STRING_COMMA_LEN ("nge_uq") },
17369 { STRING_COMMA_LEN ("ngt_uq") },
17370 { STRING_COMMA_LEN ("false_os") },
17371 { STRING_COMMA_LEN ("neq_os") },
17372 { STRING_COMMA_LEN ("ge_oq") },
17373 { STRING_COMMA_LEN ("gt_oq") },
17374 { STRING_COMMA_LEN ("true_us") },
17378 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
17380 unsigned int cmp_type
;
17382 FETCH_DATA (the_info
, codep
+ 1);
17383 cmp_type
= *codep
++ & 0xff;
17384 if (cmp_type
< ARRAY_SIZE (vex_cmp_op
))
17387 char *p
= mnemonicendp
- 2;
17391 sprintf (p
, "%s%s", vex_cmp_op
[cmp_type
].name
, suffix
);
17392 mnemonicendp
+= vex_cmp_op
[cmp_type
].len
;
17396 /* We have a reserved extension byte. Output it directly. */
17397 scratchbuf
[0] = '$';
17398 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
17399 oappend_maybe_intel (scratchbuf
);
17400 scratchbuf
[0] = '\0';
17405 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
,
17406 int sizeflag ATTRIBUTE_UNUSED
)
17408 unsigned int cmp_type
;
17413 FETCH_DATA (the_info
, codep
+ 1);
17414 cmp_type
= *codep
++ & 0xff;
17415 /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
17416 If it's the case, print suffix, otherwise - print the immediate. */
17417 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
)
17422 char *p
= mnemonicendp
- 2;
17424 /* vpcmp* can have both one- and two-lettered suffix. */
17438 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
17439 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
17443 /* We have a reserved extension byte. Output it directly. */
17444 scratchbuf
[0] = '$';
17445 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
17446 oappend_maybe_intel (scratchbuf
);
17447 scratchbuf
[0] = '\0';
17451 static const struct op pclmul_op
[] =
17453 { STRING_COMMA_LEN ("lql") },
17454 { STRING_COMMA_LEN ("hql") },
17455 { STRING_COMMA_LEN ("lqh") },
17456 { STRING_COMMA_LEN ("hqh") }
17460 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED
,
17461 int sizeflag ATTRIBUTE_UNUSED
)
17463 unsigned int pclmul_type
;
17465 FETCH_DATA (the_info
, codep
+ 1);
17466 pclmul_type
= *codep
++ & 0xff;
17467 switch (pclmul_type
)
17478 if (pclmul_type
< ARRAY_SIZE (pclmul_op
))
17481 char *p
= mnemonicendp
- 3;
17486 sprintf (p
, "%s%s", pclmul_op
[pclmul_type
].name
, suffix
);
17487 mnemonicendp
+= pclmul_op
[pclmul_type
].len
;
17491 /* We have a reserved extension byte. Output it directly. */
17492 scratchbuf
[0] = '$';
17493 print_operand_value (scratchbuf
+ 1, 1, pclmul_type
);
17494 oappend_maybe_intel (scratchbuf
);
17495 scratchbuf
[0] = '\0';
17500 MOVBE_Fixup (int bytemode
, int sizeflag
)
17502 /* Add proper suffix to "movbe". */
17503 char *p
= mnemonicendp
;
17512 if (sizeflag
& SUFFIX_ALWAYS
)
17518 if (sizeflag
& DFLAG
)
17522 used_prefixes
|= (prefixes
& PREFIX_DATA
);
17527 oappend (INTERNAL_DISASSEMBLER_ERROR
);
17534 OP_M (bytemode
, sizeflag
);
17538 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
17541 const char **names
;
17543 /* Skip mod/rm byte. */
17557 oappend (names
[reg
]);
17561 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
17563 const char **names
;
17570 oappend (names
[vex
.register_specifier
]);
17574 OP_Mask (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
17577 || (bytemode
!= mask_mode
&& bytemode
!= mask_bd_mode
))
17581 if ((rex
& REX_R
) != 0 || !vex
.r
)
17587 oappend (names_mask
[modrm
.reg
]);
17591 OP_Rounding (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
17594 || (bytemode
!= evex_rounding_mode
17595 && bytemode
!= evex_sae_mode
))
17597 if (modrm
.mod
== 3 && vex
.b
)
17600 case evex_rounding_mode
:
17601 oappend (names_rounding
[vex
.ll
]);
17603 case evex_sae_mode
: