opcodes/ppc-dis.c

   1 /* ppc-dis.c -- Disassemble PowerPC instructions
   2    Copyright (C) 1994-2025 Free Software Foundation, Inc.
   3    Written by Ian Lance Taylor, Cygnus Support
   4
   5    This file is part of the GNU opcodes library.
   6
   7    This library is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3, or (at your option)
  10    any later version.
  11
  12    It is distributed in the hope that it will be useful, but WITHOUT
  13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15    License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this file; see the file COPYING.  If not, write to the
  19    Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
  20    MA 02110-1301, USA.  */
  21
  22 #include "sysdep.h"
  23 #include <stdio.h>
  24 #include "disassemble.h"
  25 #include "elf-bfd.h"
  26 #include "elf/ppc.h"
  27 #include "opintl.h"
  28 #include "opcode/ppc.h"
  29 #include "libiberty.h"
  30
  31 /* This file provides several disassembler functions, all of which use
  32    the disassembler interface defined in dis-asm.h.  Several functions
  33    are provided because this file handles disassembly for the PowerPC
  34    in both big and little endian mode and also for the POWER (RS/6000)
  35    chip.  */
  36 static int print_insn_powerpc (bfd_vma, struct disassemble_info *, int,
  37                                ppc_cpu_t);
  38
  39 struct dis_private
  40 {
  41   /* Stash the result of parsing disassembler_options here.  */
  42   ppc_cpu_t dialect;
  43
  44   /* .got and .plt sections.  NAME is set to NULL if not present.  */
  45   struct sec_buf {
  46     asection *sec;
  47     bfd_byte *buf;
  48     const char *name;
  49   } special[2];
  50 };
  51
  52 static inline struct dis_private *
  53 private_data (struct disassemble_info *info)
  54 {
  55   return (struct dis_private *) info->private_data;
  56 }
  57
  58 struct ppc_mopt {
  59   /* Option string, without -m or -M prefix.  */
  60   const char *opt;
  61   /* CPU option flags.  */
  62   ppc_cpu_t cpu;
  63   /* Flags that should stay on, even when combined with another cpu
  64      option.  This should only be used for generic options like
  65      "-many" or "-maltivec" where it is reasonable to add some
  66      capability to another cpu selection.  The added flags are sticky
  67      so that, for example, "-many -me500" and "-me500 -many" result in
  68      the same assembler or disassembler behaviour.  Do not use
  69      "sticky" for specific cpus, as this will prevent that cpu's flags
  70      from overriding the defaults set in powerpc_init_dialect or a
  71      prior -m option.  */
  72   ppc_cpu_t sticky;
  73 };
  74
  75 struct ppc_mopt ppc_opts[] = {
  76   { "403",     PPC_OPCODE_PPC | PPC_OPCODE_403,
  77     0 },
  78   { "405",     PPC_OPCODE_PPC | PPC_OPCODE_403 | PPC_OPCODE_405,
  79     0 },
  80   { "440",     (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_440
  81                 | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI),
  82     0 },
  83   { "464",     (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_440
  84                 | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI),
  85     0 },
  86   { "476",     (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_476
  87                 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5),
  88     0 },
  89   { "601",     PPC_OPCODE_PPC | PPC_OPCODE_601,
  90     0 },
  91   { "603",     PPC_OPCODE_PPC,
  92     0 },
  93   { "604",     PPC_OPCODE_PPC,
  94     0 },
  95   { "620",     PPC_OPCODE_PPC | PPC_OPCODE_64,
  96     0 },
  97   { "7400",    PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC,
  98     0 },
  99   { "7410",    PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC,
 100     0 },
 101   { "7450",    PPC_OPCODE_PPC | PPC_OPCODE_7450 | PPC_OPCODE_ALTIVEC,
 102     0 },
 103   { "7455",    PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC,
 104     0 },
 105   { "750cl",   PPC_OPCODE_PPC | PPC_OPCODE_750 | PPC_OPCODE_PPCPS
 106     , 0 },
 107   { "gekko",   PPC_OPCODE_PPC | PPC_OPCODE_750 | PPC_OPCODE_PPCPS
 108     , 0 },
 109   { "broadway", PPC_OPCODE_PPC | PPC_OPCODE_750 | PPC_OPCODE_PPCPS
 110     , 0 },
 111   { "821",     PPC_OPCODE_PPC | PPC_OPCODE_860,
 112     0 },
 113   { "850",     PPC_OPCODE_PPC | PPC_OPCODE_860,
 114     0 },
 115   { "860",     PPC_OPCODE_PPC | PPC_OPCODE_860,
 116     0 },
 117   { "a2",      (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_POWER4
 118                 | PPC_OPCODE_POWER5 | PPC_OPCODE_CACHELCK | PPC_OPCODE_64
 119                 | PPC_OPCODE_A2),
 120     0 },
 121   { "altivec", PPC_OPCODE_PPC,
 122     PPC_OPCODE_ALTIVEC },
 123   { "any",     PPC_OPCODE_PPC,
 124     PPC_OPCODE_ANY },
 125   { "booke",   PPC_OPCODE_PPC | PPC_OPCODE_BOOKE,
 126     0 },
 127   { "booke32", PPC_OPCODE_PPC | PPC_OPCODE_BOOKE,
 128     0 },
 129   { "cell",    (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
 130                 | PPC_OPCODE_CELL | PPC_OPCODE_ALTIVEC),
 131     0 },
 132   { "com",     PPC_OPCODE_COMMON,
 133     0 },
 134   { "e200z2",  (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_LSP
 135                 | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
 136                 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 137                 | PPC_OPCODE_E500 | PPC_OPCODE_VLE | PPC_OPCODE_E200Z4
 138                 | PPC_OPCODE_EFS2),
 139     0 },
 140   { "e200z4",  (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE
 141                 | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
 142                 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 143                 | PPC_OPCODE_E500 | PPC_OPCODE_VLE | PPC_OPCODE_E200Z4
 144                 | PPC_OPCODE_EFS2),
 145     0 },
 146   { "e300",    PPC_OPCODE_PPC | PPC_OPCODE_E300,
 147     0 },
 148   { "e500",    (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE
 149                 | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
 150                 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 151                 | PPC_OPCODE_E500),
 152     0 },
 153   { "e500mc",  (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
 154                 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 155                 | PPC_OPCODE_E500MC),
 156     0 },
 157   { "e500mc64",  (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
 158                 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 159                 | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_POWER5
 160                 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7),
 161     0 },
 162   { "e5500",    (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
 163                 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 164                 | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
 165                 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7),
 166     0 },
 167   { "e6500",   (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
 168                 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 169                 | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_ALTIVEC
 170                 | PPC_OPCODE_E6500 | PPC_OPCODE_TMR | PPC_OPCODE_POWER4
 171                 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7),
 172     0 },
 173   { "e500x2",  (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE
 174                 | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
 175                 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 176                 | PPC_OPCODE_E500),
 177     0 },
 178   { "efs",     PPC_OPCODE_PPC | PPC_OPCODE_EFS,
 179     0 },
 180   { "efs2",    PPC_OPCODE_PPC | PPC_OPCODE_EFS | PPC_OPCODE_EFS2,
 181     0 },
 182   { "lsp",     PPC_OPCODE_PPC,
 183     PPC_OPCODE_LSP },
 184   { "power4",  PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4,
 185     0 },
 186   { "power5",  (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
 187                 | PPC_OPCODE_POWER5),
 188     0 },
 189   { "power6",  (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
 190                 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC),
 191     0 },
 192   { "power7",  (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
 193                 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
 194                 | PPC_OPCODE_POWER7 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
 195     0 },
 196   { "power8",  (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
 197                 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
 198                 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8
 199                 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
 200     0 },
 201   { "power9",  (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
 202                 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
 203                 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9
 204                 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
 205     0 },
 206   { "power10", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
 207                 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
 208                 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9
 209                 | PPC_OPCODE_POWER10 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
 210     0 },
 211   { "power11", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
 212                 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
 213                 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9
 214                 | PPC_OPCODE_POWER10 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
 215     0 },
 216   { "libresoc",(PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
 217                 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
 218                 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9
 219                 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX | PPC_OPCODE_SVP64),
 220     0 },
 221   { "future",  (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
 222                 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
 223                 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9
 224                 | PPC_OPCODE_POWER10 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX
 225                 | PPC_OPCODE_FUTURE),
 226     0 },
 227   { "ppc",     PPC_OPCODE_PPC,
 228     0 },
 229   { "ppc32",   PPC_OPCODE_PPC,
 230     0 },
 231   { "32",      PPC_OPCODE_PPC,
 232     0 },
 233   { "ppc64",   PPC_OPCODE_PPC | PPC_OPCODE_64,
 234     0 },
 235   { "64",      PPC_OPCODE_PPC | PPC_OPCODE_64,
 236     0 },
 237   { "ppc64bridge", PPC_OPCODE_PPC | PPC_OPCODE_64_BRIDGE,
 238     0 },
 239   { "ppcps",   PPC_OPCODE_PPC | PPC_OPCODE_PPCPS,
 240     0 },
 241   { "pwr",     PPC_OPCODE_POWER,
 242     0 },
 243   { "pwr2",    PPC_OPCODE_POWER | PPC_OPCODE_POWER2,
 244     0 },
 245   { "pwr4",    PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4,
 246     0 },
 247   { "pwr5",    (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
 248                 | PPC_OPCODE_POWER5),
 249     0 },
 250   { "pwr5x",   (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
 251                 | PPC_OPCODE_POWER5),
 252     0 },
 253   { "pwr6",    (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
 254                 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC),
 255     0 },
 256   { "pwr7",    (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
 257                 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
 258                 | PPC_OPCODE_POWER7 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
 259     0 },
 260   { "pwr8",    (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
 261                 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
 262                 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8
 263                 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
 264     0 },
 265   { "pwr9",    (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
 266                 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
 267                 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9
 268                 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
 269     0 },
 270   { "pwr10",   (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
 271                 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
 272                 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9
 273                 | PPC_OPCODE_POWER10 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
 274     0 },
 275   { "pwr11",   (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
 276                 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
 277                 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9
 278                 | PPC_OPCODE_POWER10 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
 279     0 },
 280   { "pwrx",    PPC_OPCODE_POWER | PPC_OPCODE_POWER2,
 281     0 },
 282   { "raw",     PPC_OPCODE_PPC,
 283     PPC_OPCODE_RAW },
 284   { "spe",     PPC_OPCODE_PPC | PPC_OPCODE_EFS,
 285     PPC_OPCODE_SPE },
 286   { "spe2",     PPC_OPCODE_PPC | PPC_OPCODE_EFS | PPC_OPCODE_EFS2 | PPC_OPCODE_SPE,
 287     PPC_OPCODE_SPE2 },
 288   { "titan",   (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_PMR
 289                 | PPC_OPCODE_RFMCI | PPC_OPCODE_TITAN),
 290     0 },
 291   { "vle",     (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE
 292                 | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
 293                 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 294                 | PPC_OPCODE_EFS2 | PPC_OPCODE_SPE2),
 295     PPC_OPCODE_VLE },
 296   { "vsx",     PPC_OPCODE_PPC,
 297     PPC_OPCODE_VSX },
 298 };
 299
 300 /* Switch between Booke and VLE dialects for interlinked dumps.  */
 301 static ppc_cpu_t
 302 get_powerpc_dialect (struct disassemble_info *info)
 303 {
 304   ppc_cpu_t dialect = 0;
 305
 306   if (info->private_data)
 307     dialect = private_data (info)->dialect;
 308
 309   /* Disassemble according to the section headers flags for VLE-mode.  */
 310   if (dialect & PPC_OPCODE_VLE
 311       && info->section != NULL && info->section->owner != NULL
 312       && bfd_get_flavour (info->section->owner) == bfd_target_elf_flavour
 313       && elf_object_id (info->section->owner) == PPC32_ELF_DATA
 314       && (elf_section_flags (info->section) & SHF_PPC_VLE) != 0)
 315     return dialect;
 316   else
 317     return dialect & ~ PPC_OPCODE_VLE;
 318 }
 319
 320 /* Handle -m and -M options that set cpu type, and .machine arg.  */
 321
 322 ppc_cpu_t
 323 ppc_parse_cpu (ppc_cpu_t ppc_cpu, ppc_cpu_t *sticky, const char *arg)
 324 {
 325   unsigned int i;
 326
 327   for (i = 0; i < ARRAY_SIZE (ppc_opts); i++)
 328     if (disassembler_options_cmp (ppc_opts[i].opt, arg) == 0)
 329       {
 330         if (ppc_opts[i].sticky)
 331           {
 332             *sticky |= ppc_opts[i].sticky;
 333             if ((ppc_cpu & ~*sticky) != 0)
 334               break;
 335           }
 336         ppc_cpu = ppc_opts[i].cpu;
 337         break;
 338       }
 339   if (i >= ARRAY_SIZE (ppc_opts))
 340     return 0;
 341
 342   /* SPE and LSP are mutually exclusive, don't allow them both in
 343      sticky options.  However do allow them both in ppc_cpu, so that
 344      for example, -mvle -mlsp enables both SPE and LSP for assembly.  */
 345   if ((ppc_opts[i].sticky & PPC_OPCODE_LSP) != 0)
 346     *sticky &= ~(PPC_OPCODE_SPE | PPC_OPCODE_SPE2);
 347   else if ((ppc_opts[i].sticky & (PPC_OPCODE_SPE | PPC_OPCODE_SPE2)) != 0)
 348     *sticky &= ~PPC_OPCODE_LSP;
 349   ppc_cpu |= *sticky;
 350
 351   return ppc_cpu;
 352 }
 353
 354 /* Determine which set of machines to disassemble for.  */
 355
 356 static void
 357 powerpc_init_dialect (struct disassemble_info *info)
 358 {
 359   ppc_cpu_t dialect = 0;
 360   ppc_cpu_t sticky = 0;
 361   struct dis_private *priv = calloc (1, sizeof (*priv));
 362
 363   if (priv == NULL)
 364     return;
 365
 366   switch (info->mach)
 367     {
 368     case bfd_mach_ppc_403:
 369     case bfd_mach_ppc_403gc:
 370       dialect = ppc_parse_cpu (dialect, &sticky, "403");
 371       break;
 372     case bfd_mach_ppc_405:
 373       dialect = ppc_parse_cpu (dialect, &sticky, "405");
 374       break;
 375     case bfd_mach_ppc_601:
 376       dialect = ppc_parse_cpu (dialect, &sticky, "601");
 377       break;
 378     case bfd_mach_ppc_750:
 379       dialect = ppc_parse_cpu (dialect, &sticky, "750cl");
 380       break;
 381     case bfd_mach_ppc_a35:
 382     case bfd_mach_ppc_rs64ii:
 383     case bfd_mach_ppc_rs64iii:
 384       dialect = ppc_parse_cpu (dialect, &sticky, "pwr2") | PPC_OPCODE_64;
 385       break;
 386     case bfd_mach_ppc_e500:
 387       dialect = ppc_parse_cpu (dialect, &sticky, "e500");
 388       break;
 389     case bfd_mach_ppc_e500mc:
 390       dialect = ppc_parse_cpu (dialect, &sticky, "e500mc");
 391       break;
 392     case bfd_mach_ppc_e500mc64:
 393       dialect = ppc_parse_cpu (dialect, &sticky, "e500mc64");
 394       break;
 395     case bfd_mach_ppc_e5500:
 396       dialect = ppc_parse_cpu (dialect, &sticky, "e5500");
 397       break;
 398     case bfd_mach_ppc_e6500:
 399       dialect = ppc_parse_cpu (dialect, &sticky, "e6500");
 400       break;
 401     case bfd_mach_ppc_titan:
 402       dialect = ppc_parse_cpu (dialect, &sticky, "titan");
 403       break;
 404     case bfd_mach_ppc_vle:
 405       dialect = ppc_parse_cpu (dialect, &sticky, "vle");
 406       break;
 407     default:
 408       if (info->arch == bfd_arch_powerpc)
 409         dialect = ppc_parse_cpu (dialect, &sticky, "power11") | PPC_OPCODE_ANY;
 410       else
 411         dialect = ppc_parse_cpu (dialect, &sticky, "pwr");
 412       break;
 413     }
 414
 415   const char *opt;
 416   FOR_EACH_DISASSEMBLER_OPTION (opt, info->disassembler_options)
 417     {
 418       ppc_cpu_t new_cpu = 0;
 419
 420       if (disassembler_options_cmp (opt, "32") == 0)
 421         dialect &= ~(ppc_cpu_t) PPC_OPCODE_64;
 422       else if (disassembler_options_cmp (opt, "64") == 0)
 423         dialect |= PPC_OPCODE_64;
 424       else if ((new_cpu = ppc_parse_cpu (dialect, &sticky, opt)) != 0)
 425         dialect = new_cpu;
 426       else
 427         /* xgettext: c-format */
 428         opcodes_error_handler (_("warning: ignoring unknown -M%s option"), opt);
 429     }
 430
 431   info->private_data = priv;
 432   private_data (info)->dialect = dialect;
 433 }
 434
 435 #define PPC_OPCD_SEGS (1 + PPC_OP (-1))
 436 static unsigned short powerpc_opcd_indices[PPC_OPCD_SEGS + 1];
 437 #define PREFIX_OPCD_SEGS (1 + PPC_PREFIX_SEG (-1))
 438 static unsigned short prefix_opcd_indices[PREFIX_OPCD_SEGS + 1];
 439 #define VLE_OPCD_SEGS (1 + VLE_OP_TO_SEG (VLE_OP (-1, 0xffff)))
 440 static unsigned short vle_opcd_indices[VLE_OPCD_SEGS + 1];
 441 #define LSP_OPCD_SEGS (1 + LSP_OP_TO_SEG (-1))
 442 static unsigned short lsp_opcd_indices[LSP_OPCD_SEGS + 1];
 443 #define SPE2_OPCD_SEGS (1 + SPE2_XOP_TO_SEG (SPE2_XOP (-1)))
 444 static unsigned short spe2_opcd_indices[SPE2_OPCD_SEGS + 1];
 445
 446 static bool
 447 ppc_symbol_is_valid (asymbol *sym,
 448                      struct disassemble_info *info ATTRIBUTE_UNUSED)
 449 {
 450   elf_symbol_type * est;
 451
 452   if (sym == NULL)
 453     return false;
 454
 455   est = elf_symbol_from (sym);
 456
 457   /* Ignore ELF hidden, local, no-type symbols.
 458      These are generated by annobin.  */
 459   if (est != NULL
 460       && ELF_ST_VISIBILITY (est->internal_elf_sym.st_other) == STV_HIDDEN
 461       && ELF_ST_BIND (est->internal_elf_sym.st_info) == STB_LOCAL
 462       && ELF_ST_TYPE (est->internal_elf_sym.st_info) == STT_NOTYPE)
 463     return false;
 464
 465   return true;
 466 }
 467
 468 /* Calculate opcode table indices to speed up disassembly,
 469    and init dialect.  */
 470
 471 void
 472 disassemble_init_powerpc (struct disassemble_info *info)
 473 {
 474   info->symbol_is_valid = ppc_symbol_is_valid;
 475
 476   if (powerpc_opcd_indices[PPC_OPCD_SEGS] == 0)
 477     {
 478       unsigned seg, idx, op;
 479
 480       /* PPC opcodes */
 481       for (seg = 0, idx = 0; seg <= PPC_OPCD_SEGS; seg++)
 482         {
 483           powerpc_opcd_indices[seg] = idx;
 484           for (; idx < powerpc_num_opcodes; idx++)
 485             if (seg < PPC_OP (powerpc_opcodes[idx].opcode))
 486               break;
 487         }
 488
 489       /* 64-bit prefix opcodes */
 490       for (seg = 0, idx = 0; seg <= PREFIX_OPCD_SEGS; seg++)
 491         {
 492           prefix_opcd_indices[seg] = idx;
 493           for (; idx < prefix_num_opcodes; idx++)
 494             if (seg < PPC_PREFIX_SEG (prefix_opcodes[idx].opcode))
 495               break;
 496         }
 497
 498       /* VLE opcodes */
 499       for (seg = 0, idx = 0; seg <= VLE_OPCD_SEGS; seg++)
 500         {
 501           vle_opcd_indices[seg] = idx;
 502           for (; idx < vle_num_opcodes; idx++)
 503             {
 504               op = VLE_OP (vle_opcodes[idx].opcode, vle_opcodes[idx].mask);
 505               if (seg < VLE_OP_TO_SEG (op))
 506                 break;
 507             }
 508         }
 509
 510       /* LSP opcodes */
 511       for (seg = 0, idx = 0; seg <= LSP_OPCD_SEGS; seg++)
 512         {
 513           lsp_opcd_indices[seg] = idx;
 514           for (; idx < lsp_num_opcodes; idx++)
 515             if (seg < LSP_OP_TO_SEG (lsp_opcodes[idx].opcode))
 516               break;
 517         }
 518
 519       /* SPE2 opcodes */
 520       for (seg = 0, idx = 0; seg <= SPE2_OPCD_SEGS; seg++)
 521         {
 522           spe2_opcd_indices[seg] = idx;
 523           for (; idx < spe2_num_opcodes; idx++)
 524             {
 525               op = SPE2_XOP (spe2_opcodes[idx].opcode);
 526               if (seg < SPE2_XOP_TO_SEG (op))
 527                 break;
 528             }
 529         }
 530     }
 531
 532   powerpc_init_dialect (info);
 533   if (info->private_data != NULL)
 534     {
 535       private_data (info)->special[0].name = ".got";
 536       private_data (info)->special[1].name = ".plt";
 537     }
 538 }
 539
 540 void
 541 disassemble_free_powerpc (struct disassemble_info *info)
 542 {
 543   if (info->private_data != NULL)
 544     {
 545       free (private_data (info)->special[0].buf);
 546       free (private_data (info)->special[1].buf);
 547     }
 548 }
 549
 550 /* Print a big endian PowerPC instruction.  */
 551
 552 int
 553 print_insn_big_powerpc (bfd_vma memaddr, struct disassemble_info *info)
 554 {
 555   return print_insn_powerpc (memaddr, info, 1, get_powerpc_dialect (info));
 556 }
 557
 558 /* Print a little endian PowerPC instruction.  */
 559
 560 int
 561 print_insn_little_powerpc (bfd_vma memaddr, struct disassemble_info *info)
 562 {
 563   return print_insn_powerpc (memaddr, info, 0, get_powerpc_dialect (info));
 564 }
 565
 566 /* Extract the operand value from the PowerPC or POWER instruction.  */
 567
 568 static int64_t
 569 operand_value_powerpc (const struct powerpc_operand *operand,
 570                        uint64_t insn, ppc_cpu_t dialect)
 571 {
 572   int64_t value;
 573   int invalid = 0;
 574   /* Extract the value from the instruction.  */
 575   if (operand->extract)
 576     value = (*operand->extract) (insn, dialect, &invalid);
 577   else
 578     {
 579       if (operand->shift >= 0)
 580         value = (insn >> operand->shift) & operand->bitm;
 581       else
 582         value = (insn << -operand->shift) & operand->bitm;
 583       if ((operand->flags & PPC_OPERAND_SIGNED) != 0)
 584         {
 585           /* BITM is always some number of zeros followed by some
 586              number of ones, followed by some number of zeros.  */
 587           uint64_t top = operand->bitm;
 588           /* top & -top gives the rightmost 1 bit, so this
 589              fills in any trailing zeros.  */
 590           top |= (top & -top) - 1;
 591           top &= ~(top >> 1);
 592           value = (value ^ top) - top;
 593         }
 594     }
 595
 596   if ((operand->flags & PPC_OPERAND_NONZERO) != 0)
 597     ++value;
 598
 599   return value;
 600 }
 601
 602 /* Determine whether the optional operand(s) should be printed.  */
 603
 604 static bool
 605 skip_optional_operands (const ppc_opindex_t *opindex,
 606                         uint64_t insn, ppc_cpu_t dialect, bool *is_pcrel)
 607 {
 608   const struct powerpc_operand *operand;
 609   int num_optional;
 610
 611   for (num_optional = 0; *opindex != 0; opindex++)
 612     {
 613       operand = &powerpc_operands[*opindex];
 614       if ((operand->flags & PPC_OPERAND_NEXT) != 0)
 615         return false;
 616       if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0)
 617         {
 618           int64_t value = operand_value_powerpc (operand, insn, dialect);
 619
 620           if (operand->shift == 52)
 621             *is_pcrel = value != 0;
 622
 623           /* Negative count is used as a flag to extract function.  */
 624           --num_optional;
 625           if (value != ppc_optional_operand_value (operand, insn, dialect,
 626                                                    num_optional))
 627             return false;
 628         }
 629     }
 630
 631   return true;
 632 }
 633
 634 /* Find a match for INSN in the opcode table, given machine DIALECT.  */
 635
 636 static const struct powerpc_opcode *
 637 lookup_powerpc (uint64_t insn, ppc_cpu_t dialect)
 638 {
 639   const struct powerpc_opcode *opcode, *opcode_end;
 640   unsigned long op;
 641
 642   /* Get the major opcode of the instruction.  */
 643   op = PPC_OP (insn);
 644
 645   /* Find the first match in the opcode table for this major opcode.  */
 646   opcode_end = powerpc_opcodes + powerpc_opcd_indices[op + 1];
 647   for (opcode = powerpc_opcodes + powerpc_opcd_indices[op];
 648        opcode < opcode_end;
 649        ++opcode)
 650     {
 651       const ppc_opindex_t *opindex;
 652       const struct powerpc_operand *operand;
 653       int invalid;
 654
 655       if ((insn & opcode->mask) != opcode->opcode
 656           || ((dialect & PPC_OPCODE_ANY) == 0
 657               && ((opcode->flags & dialect) == 0
 658                   || (opcode->deprecated & dialect) != 0))
 659           || (opcode->deprecated & dialect & PPC_OPCODE_RAW) != 0)
 660         continue;
 661
 662       /* Check validity of operands.  */
 663       invalid = 0;
 664       for (opindex = opcode->operands; *opindex != 0; opindex++)
 665         {
 666           operand = powerpc_operands + *opindex;
 667           if (operand->extract)
 668             (*operand->extract) (insn, dialect, &invalid);
 669         }
 670       if (invalid)
 671         continue;
 672
 673       return opcode;
 674     }
 675
 676   return NULL;
 677 }
 678
 679 /* Find a match for INSN in the PREFIX opcode table.  */
 680
 681 static const struct powerpc_opcode *
 682 lookup_prefix (uint64_t insn, ppc_cpu_t dialect)
 683 {
 684   const struct powerpc_opcode *opcode, *opcode_end;
 685   unsigned long seg;
 686
 687   /* Get the opcode segment of the instruction.  */
 688   seg = PPC_PREFIX_SEG (insn);
 689
 690   /* Find the first match in the opcode table for this major opcode.  */
 691   opcode_end = prefix_opcodes + prefix_opcd_indices[seg + 1];
 692   for (opcode = prefix_opcodes + prefix_opcd_indices[seg];
 693        opcode < opcode_end;
 694        ++opcode)
 695     {
 696       const ppc_opindex_t *opindex;
 697       const struct powerpc_operand *operand;
 698       int invalid;
 699
 700       if ((insn & opcode->mask) != opcode->opcode
 701           || ((dialect & PPC_OPCODE_ANY) == 0
 702               && (opcode->flags & dialect) == 0)
 703           || (opcode->deprecated & dialect) != 0)
 704         continue;
 705
 706       /* Check validity of operands.  */
 707       invalid = 0;
 708       for (opindex = opcode->operands; *opindex != 0; opindex++)
 709         {
 710           operand = powerpc_operands + *opindex;
 711           if (operand->extract)
 712             (*operand->extract) (insn, dialect, &invalid);
 713         }
 714       if (invalid)
 715         continue;
 716
 717       return opcode;
 718     }
 719
 720   return NULL;
 721 }
 722
 723 /* Find a match for INSN in the VLE opcode table.  */
 724
 725 static const struct powerpc_opcode *
 726 lookup_vle (uint64_t insn, ppc_cpu_t dialect)
 727 {
 728   const struct powerpc_opcode *opcode;
 729   const struct powerpc_opcode *opcode_end;
 730   unsigned op, seg;
 731
 732   op = PPC_OP (insn);
 733   if (op >= 0x20 && op <= 0x37)
 734     {
 735       /* This insn has a 4-bit opcode.  */
 736       op &= 0x3c;
 737     }
 738   seg = VLE_OP_TO_SEG (op);
 739
 740   /* Find the first match in the opcode table for this major opcode.  */
 741   opcode_end = vle_opcodes + vle_opcd_indices[seg + 1];
 742   for (opcode = vle_opcodes + vle_opcd_indices[seg];
 743        opcode < opcode_end;
 744        ++opcode)
 745     {
 746       uint64_t table_opcd = opcode->opcode;
 747       uint64_t table_mask = opcode->mask;
 748       bool table_op_is_short = PPC_OP_SE_VLE(table_mask);
 749       uint64_t insn2;
 750       const ppc_opindex_t *opindex;
 751       const struct powerpc_operand *operand;
 752       int invalid;
 753
 754       insn2 = insn;
 755       if (table_op_is_short)
 756         insn2 >>= 16;
 757       if ((insn2 & table_mask) != table_opcd
 758           || (opcode->deprecated & dialect) != 0)
 759         continue;
 760
 761       /* Check validity of operands.  */
 762       invalid = 0;
 763       for (opindex = opcode->operands; *opindex != 0; ++opindex)
 764         {
 765           operand = powerpc_operands + *opindex;
 766           if (operand->extract)
 767             (*operand->extract) (insn, (ppc_cpu_t)0, &invalid);
 768         }
 769       if (invalid)
 770         continue;
 771
 772       return opcode;
 773     }
 774
 775   return NULL;
 776 }
 777
 778 /* Find a match for INSN in the LSP opcode table.  */
 779
 780 static const struct powerpc_opcode *
 781 lookup_lsp (uint64_t insn, ppc_cpu_t dialect)
 782 {
 783   const struct powerpc_opcode *opcode, *opcode_end;
 784   unsigned op, seg;
 785
 786   op = PPC_OP (insn);
 787   if (op != 0x4)
 788     return NULL;
 789
 790   seg = LSP_OP_TO_SEG (insn);
 791
 792   /* Find the first match in the opcode table for this opcode.  */
 793   opcode_end = lsp_opcodes + lsp_opcd_indices[seg + 1];
 794   for (opcode = lsp_opcodes + lsp_opcd_indices[seg];
 795        opcode < opcode_end;
 796        ++opcode)
 797     {
 798       const ppc_opindex_t *opindex;
 799       const struct powerpc_operand *operand;
 800       int invalid;
 801
 802       if ((insn & opcode->mask) != opcode->opcode
 803           || (opcode->deprecated & dialect) != 0)
 804         continue;
 805
 806       /* Check validity of operands.  */
 807       invalid = 0;
 808       for (opindex = opcode->operands; *opindex != 0; ++opindex)
 809         {
 810           operand = powerpc_operands + *opindex;
 811           if (operand->extract)
 812             (*operand->extract) (insn, (ppc_cpu_t) 0, &invalid);
 813         }
 814       if (invalid)
 815         continue;
 816
 817       return opcode;
 818     }
 819
 820   return NULL;
 821 }
 822
 823 /* Find a match for INSN in the SPE2 opcode table.  */
 824
 825 static const struct powerpc_opcode *
 826 lookup_spe2 (uint64_t insn, ppc_cpu_t dialect)
 827 {
 828   const struct powerpc_opcode *opcode, *opcode_end;
 829   unsigned op, xop, seg;
 830
 831   op = PPC_OP (insn);
 832   if (op != 0x4)
 833     {
 834       /* This is not SPE2 insn.
 835        * All SPE2 instructions have OP=4 and differs by XOP  */
 836       return NULL;
 837     }
 838   xop = SPE2_XOP (insn);
 839   seg = SPE2_XOP_TO_SEG (xop);
 840
 841   /* Find the first match in the opcode table for this opcode.  */
 842   opcode_end = spe2_opcodes + spe2_opcd_indices[seg + 1];
 843   for (opcode = spe2_opcodes + spe2_opcd_indices[seg];
 844        opcode < opcode_end;
 845        ++opcode)
 846     {
 847       uint64_t table_opcd = opcode->opcode;
 848       uint64_t table_mask = opcode->mask;
 849       uint64_t insn2;
 850       const ppc_opindex_t *opindex;
 851       const struct powerpc_operand *operand;
 852       int invalid;
 853
 854       insn2 = insn;
 855       if ((insn2 & table_mask) != table_opcd
 856           || (opcode->deprecated & dialect) != 0)
 857         continue;
 858
 859       /* Check validity of operands.  */
 860       invalid = 0;
 861       for (opindex = opcode->operands; *opindex != 0; ++opindex)
 862         {
 863           operand = powerpc_operands + *opindex;
 864           if (operand->extract)
 865             (*operand->extract) (insn, (ppc_cpu_t)0, &invalid);
 866         }
 867       if (invalid)
 868         continue;
 869
 870       return opcode;
 871     }
 872
 873   return NULL;
 874 }
 875
 876 static arelent *
 877 bsearch_reloc (arelent **lo, arelent **hi, bfd_vma vma)
 878 {
 879   while (lo < hi)
 880     {
 881       arelent **mid = lo + (hi - lo) / 2;
 882       arelent *rel = *mid;
 883
 884       if (vma < rel->address)
 885         hi = mid;
 886       else if (vma > rel->address)
 887         lo = mid + 1;
 888       else
 889         return rel;
 890     }
 891   return NULL;
 892 }
 893
 894 static bool
 895 print_got_plt (struct sec_buf *sb, uint64_t vma, struct disassemble_info *info)
 896 {
 897   if (sb->name != NULL)
 898     {
 899       asection *s = sb->sec;
 900       if (s == NULL)
 901         {
 902           s = bfd_get_section_by_name (info->section->owner, sb->name);
 903           sb->sec = s;
 904           if (s == NULL)
 905             sb->name = NULL;
 906         }
 907       if (s != NULL
 908           && vma >= s->vma
 909           && vma < s->vma + s->size)
 910         {
 911           asymbol *sym = NULL;
 912           uint64_t ent = 0;
 913           if (info->dynrelcount > 0)
 914             {
 915               arelent **lo = info->dynrelbuf;
 916               arelent **hi = lo + info->dynrelcount;
 917               arelent *rel = bsearch_reloc (lo, hi, vma);
 918               if (rel != NULL && rel->sym_ptr_ptr != NULL)
 919                 sym = *rel->sym_ptr_ptr;
 920             }
 921           if (sym == NULL && (s->flags & SEC_HAS_CONTENTS) != 0)
 922             {
 923               if (sb->buf == NULL
 924                   && !bfd_malloc_and_get_section (s->owner, s, &sb->buf))
 925                 sb->name = NULL;
 926               if (sb->buf != NULL)
 927                 {
 928                   ent = bfd_get_64 (s->owner, sb->buf + (vma - s->vma));
 929                   if (ent != 0)
 930                     sym = (*info->symbol_at_address_func) (ent, info);
 931                 }
 932             }
 933           (*info->fprintf_styled_func) (info->stream, dis_style_text, " [");
 934           if (sym != NULL)
 935             {
 936               (*info->fprintf_styled_func) (info->stream, dis_style_symbol,
 937                                             "%s", bfd_asymbol_name (sym));
 938               (*info->fprintf_styled_func) (info->stream, dis_style_text, "@");
 939               (*info->fprintf_styled_func) (info->stream, dis_style_symbol,
 940                                             "%s", sb->name + 1);
 941             }
 942           else
 943             {
 944               (*info->fprintf_styled_func) (info->stream, dis_style_address,
 945                                             "%" PRIx64, ent);
 946               (*info->fprintf_styled_func) (info->stream, dis_style_text, "@");
 947               (*info->fprintf_styled_func) (info->stream, dis_style_symbol,
 948                                             "%s", sb->name + 1);
 949             }
 950           (*info->fprintf_styled_func) (info->stream, dis_style_text, "]");
 951           return true;
 952         }
 953     }
 954   return false;
 955 }
 956
 957 /* Print a PowerPC or POWER instruction.  */
 958
 959 static int
 960 print_insn_powerpc (bfd_vma memaddr,
 961                     struct disassemble_info *info,
 962                     int bigendian,
 963                     ppc_cpu_t dialect)
 964 {
 965   bfd_byte buffer[4];
 966   int status;
 967   uint64_t insn;
 968   const struct powerpc_opcode *opcode;
 969   int insn_length = 4;  /* Assume we have a normal 4-byte instruction.  */
 970
 971   status = (*info->read_memory_func) (memaddr, buffer, 4, info);
 972
 973   /* The final instruction may be a 2-byte VLE insn.  */
 974   if (status != 0 && (dialect & PPC_OPCODE_VLE) != 0)
 975     {
 976       /* Clear buffer so unused bytes will not have garbage in them.  */
 977       buffer[2] = buffer[3] = 0;
 978       status = (*info->read_memory_func) (memaddr, buffer, 2, info);
 979       insn_length = 2;
 980     }
 981
 982   if (status != 0)
 983     {
 984       (*info->memory_error_func) (status, memaddr, info);
 985       return -1;
 986     }
 987
 988   if (bigendian)
 989     insn = bfd_getb32 (buffer);
 990   else
 991     insn = bfd_getl32 (buffer);
 992
 993   /* Get the major opcode of the insn.  */
 994   opcode = NULL;
 995   if ((dialect & PPC_OPCODE_POWER10) != 0
 996       && PPC_OP (insn) == 0x1)
 997     {
 998       uint64_t temp_insn, suffix;
 999       status = (*info->read_memory_func) (memaddr + 4, buffer, 4, info);
1000       if (status == 0)
1001         {
1002           if (bigendian)
1003             suffix = bfd_getb32 (buffer);
1004           else
1005             suffix = bfd_getl32 (buffer);
1006           temp_insn = (insn << 32) | suffix;
1007           opcode = lookup_prefix (temp_insn, dialect & ~PPC_OPCODE_ANY);
1008           if (opcode == NULL && (dialect & PPC_OPCODE_ANY) != 0)
1009             opcode = lookup_prefix (temp_insn, dialect);
1010           if (opcode != NULL)
1011             {
1012               insn = temp_insn;
1013               insn_length = 8;
1014               if ((info->flags & WIDE_OUTPUT) != 0)
1015                 info->bytes_per_line = 8;
1016             }
1017         }
1018     }
1019   if (opcode == NULL && (dialect & PPC_OPCODE_VLE) != 0)
1020     {
1021       opcode = lookup_vle (insn, dialect);
1022       if (opcode != NULL && PPC_OP_SE_VLE (opcode->mask))
1023         {
1024           /* The operands will be fetched out of the 16-bit instruction.  */
1025           insn >>= 16;
1026           insn_length = 2;
1027         }
1028     }
1029   if (opcode == NULL && insn_length == 4)
1030     {
1031       if ((dialect & PPC_OPCODE_LSP) != 0)
1032         opcode = lookup_lsp (insn, dialect);
1033       if ((dialect & PPC_OPCODE_SPE2) != 0)
1034         opcode = lookup_spe2 (insn, dialect);
1035       if (opcode == NULL)
1036         opcode = lookup_powerpc (insn, dialect & ~PPC_OPCODE_ANY);
1037       if (opcode == NULL && (dialect & PPC_OPCODE_ANY) != 0)
1038         opcode = lookup_powerpc (insn, dialect);
1039       if (opcode == NULL && (dialect & PPC_OPCODE_ANY) != 0)
1040         opcode = lookup_spe2 (insn, dialect);
1041       if (opcode == NULL && (dialect & PPC_OPCODE_ANY) != 0)
1042         opcode = lookup_lsp (insn, dialect);
1043     }
1044
1045   if (opcode != NULL)
1046     {
1047       const ppc_opindex_t *opindex;
1048       const struct powerpc_operand *operand;
1049       enum {
1050         need_comma = 0,
1051         need_1space = 1,
1052         need_2spaces = 2,
1053         need_3spaces = 3,
1054         need_4spaces = 4,
1055         need_5spaces = 5,
1056         need_6spaces = 6,
1057         need_7spaces = 7,
1058         need_paren
1059       } op_separator;
1060       bool skip_optional;
1061       bool is_pcrel;
1062       uint64_t d34;
1063       int blanks;
1064
1065       (*info->fprintf_styled_func) (info->stream, dis_style_mnemonic,
1066                                     "%s", opcode->name);
1067       /* gdb fprintf_styled_func doesn't return count printed.  */
1068       blanks = 8 - strlen (opcode->name);
1069       if (blanks <= 0)
1070         blanks = 1;
1071
1072       /* Now extract and print the operands.  */
1073       op_separator = blanks;
1074       skip_optional = false;
1075       is_pcrel = false;
1076       d34 = 0;
1077       for (opindex = opcode->operands; *opindex != 0; opindex++)
1078         {
1079           int64_t value;
1080
1081           operand = powerpc_operands + *opindex;
1082
1083           /* If all of the optional operands past this one have their
1084              default value, then don't print any of them.  Except in
1085              raw mode, print them all.  */
1086           if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0
1087               && (dialect & PPC_OPCODE_RAW) == 0)
1088             {
1089               if (!skip_optional)
1090                 skip_optional = skip_optional_operands (opindex, insn,
1091                                                         dialect, &is_pcrel);
1092               if (skip_optional)
1093                 continue;
1094             }
1095
1096           value = operand_value_powerpc (operand, insn, dialect);
1097
1098           if (op_separator == need_comma)
1099             (*info->fprintf_styled_func) (info->stream, dis_style_text, ",");
1100           else if (op_separator == need_paren)
1101             (*info->fprintf_styled_func) (info->stream, dis_style_text, "(");
1102           else
1103             (*info->fprintf_styled_func) (info->stream, dis_style_text, "%*s",
1104                                           op_separator, " ");
1105
1106           /* Print the operand as directed by the flags.  */
1107           if ((operand->flags & PPC_OPERAND_GPR) != 0
1108               || ((operand->flags & PPC_OPERAND_GPR_0) != 0 && value != 0))
1109             (*info->fprintf_styled_func) (info->stream, dis_style_register,
1110                                           "r%" PRId64, value);
1111           else if ((operand->flags & PPC_OPERAND_FPR) != 0)
1112             (*info->fprintf_styled_func) (info->stream, dis_style_register,
1113                                           "f%" PRId64, value);
1114           else if ((operand->flags & PPC_OPERAND_VR) != 0)
1115             (*info->fprintf_styled_func) (info->stream, dis_style_register,
1116                                           "v%" PRId64, value);
1117           else if ((operand->flags & PPC_OPERAND_VSR) != 0)
1118             (*info->fprintf_styled_func) (info->stream, dis_style_register,
1119                                           "vs%" PRId64, value);
1120           else if ((operand->flags & PPC_OPERAND_DMR) != 0)
1121             (*info->fprintf_styled_func) (info->stream, dis_style_register,
1122                                           "dm%" PRId64, value);
1123           else if ((operand->flags & PPC_OPERAND_ACC) != 0)
1124             (*info->fprintf_styled_func) (info->stream, dis_style_register,
1125                                           "a%" PRId64, value);
1126           else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0)
1127             (*info->print_address_func) (memaddr + value, info);
1128           else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0)
1129             (*info->print_address_func) ((bfd_vma) value & 0xffffffff, info);
1130           else if ((operand->flags & PPC_OPERAND_FSL) != 0)
1131             (*info->fprintf_styled_func) (info->stream, dis_style_register,
1132                                           "fsl%" PRId64, value);
1133           else if ((operand->flags & PPC_OPERAND_FCR) != 0)
1134             (*info->fprintf_styled_func) (info->stream, dis_style_register,
1135                                           "fcr%" PRId64, value);
1136           else if ((operand->flags & PPC_OPERAND_UDI) != 0)
1137             (*info->fprintf_styled_func) (info->stream, dis_style_register,
1138                                           "%" PRId64, value);
1139           else if ((operand->flags & PPC_OPERAND_CR_REG) != 0
1140                    && (operand->flags & PPC_OPERAND_CR_BIT) == 0
1141                    && (((dialect & PPC_OPCODE_PPC) != 0)
1142                        || ((dialect & PPC_OPCODE_VLE) != 0)))
1143             (*info->fprintf_styled_func) (info->stream, dis_style_register,
1144                                           "cr%" PRId64, value);
1145           else if ((operand->flags & PPC_OPERAND_CR_BIT) != 0
1146                    && (operand->flags & PPC_OPERAND_CR_REG) == 0
1147                    && (((dialect & PPC_OPCODE_PPC) != 0)
1148                        || ((dialect & PPC_OPCODE_VLE) != 0)))
1149             {
1150               static const char *cbnames[4] = { "lt", "gt", "eq", "so" };
1151               int cr;
1152               int cc;
1153
1154               cr = value >> 2;
1155               cc = value & 3;
1156               if (cr != 0)
1157                 {
1158                   (*info->fprintf_styled_func) (info->stream, dis_style_text,
1159                                                 "4*");
1160                   (*info->fprintf_styled_func) (info->stream,
1161                                                 dis_style_register,
1162                                                 "cr%d", cr);
1163                   (*info->fprintf_styled_func) (info->stream, dis_style_text,
1164                                                 "+");
1165                 }
1166
1167               (*info->fprintf_styled_func) (info->stream,
1168                                             dis_style_sub_mnemonic,
1169                                             "%s", cbnames[cc]);
1170             }
1171           else
1172             {
1173               /* An immediate, but what style?  */
1174               enum disassembler_style style;
1175
1176               if ((operand->flags & PPC_OPERAND_PARENS) != 0)
1177                 style = dis_style_address_offset;
1178               else
1179                 style = dis_style_immediate;
1180
1181               (*info->fprintf_styled_func) (info->stream, style,
1182                                             "%" PRId64, value);
1183             }
1184
1185           if (operand->shift == 52)
1186             is_pcrel = value != 0;
1187           else if (operand->bitm == UINT64_C (0x3ffffffff))
1188             d34 = value;
1189
1190           if (op_separator == need_paren)
1191             (*info->fprintf_styled_func) (info->stream, dis_style_text, ")");
1192
1193           op_separator = need_comma;
1194           if ((operand->flags & PPC_OPERAND_PARENS) != 0)
1195             op_separator = need_paren;
1196         }
1197
1198       if (is_pcrel)
1199         {
1200           d34 += memaddr;
1201           (*info->fprintf_styled_func) (info->stream,
1202                                         dis_style_comment_start,
1203                                         "\t# %" PRIx64, d34);
1204           asymbol *sym = (*info->symbol_at_address_func) (d34, info);
1205           if (sym)
1206             (*info->fprintf_styled_func) (info->stream, dis_style_text,
1207                                           " <%s>", bfd_asymbol_name (sym));
1208
1209           if (info->private_data != NULL
1210               && info->section != NULL
1211               && info->section->owner != NULL
1212               && (bfd_get_file_flags (info->section->owner)
1213                   & (EXEC_P | DYNAMIC)) != 0
1214               && ((insn & ((-1ULL << 50) | (0x3fULL << 26)))
1215                   == ((1ULL << 58) | (1ULL << 52) | (57ULL << 26)) /* pld */))
1216             {
1217               for (int i = 0; i < 2; i++)
1218                 if (print_got_plt (private_data (info)->special + i, d34, info))
1219                   break;
1220             }
1221         }
1222
1223       /* We have found and printed an instruction.  */
1224       return insn_length;
1225     }
1226
1227   /* We could not find a match.  */
1228   if (insn_length == 4)
1229     (*info->fprintf_styled_func) (info->stream,
1230                                   dis_style_assembler_directive, ".long");
1231   else
1232     {
1233       (*info->fprintf_styled_func) (info->stream,
1234                                     dis_style_assembler_directive, ".word");
1235       insn >>= 16;
1236     }
1237   (*info->fprintf_styled_func) (info->stream, dis_style_text, " ");
1238   (*info->fprintf_styled_func) (info->stream, dis_style_immediate, "0x%x",
1239                                 (unsigned int) insn);
1240
1241
1242   return insn_length;
1243 }
1244
1245 const disasm_options_and_args_t *
1246 disassembler_options_powerpc (void)
1247 {
1248   static disasm_options_and_args_t *opts_and_args;
1249
1250   if (opts_and_args == NULL)
1251     {
1252       size_t i, num_options = ARRAY_SIZE (ppc_opts);
1253       disasm_options_t *opts;
1254
1255       opts_and_args = XNEW (disasm_options_and_args_t);
1256       opts_and_args->args = NULL;
1257
1258       opts = &opts_and_args->options;
1259       opts->name = XNEWVEC (const char *, num_options + 1);
1260       opts->description = NULL;
1261       opts->arg = NULL;
1262       for (i = 0; i < num_options; i++)
1263         opts->name[i] = ppc_opts[i].opt;
1264       /* The array we return must be NULL terminated.  */
1265       opts->name[i] = NULL;
1266     }
1267
1268   return opts_and_args;
1269 }
1270
1271 void
1272 print_ppc_disassembler_options (FILE *stream)
1273 {
1274   unsigned int i, col;
1275
1276   fprintf (stream, _("\n\
1277 The following PPC specific disassembler options are supported for use with\n\
1278 the -M switch:\n"));
1279
1280   for (col = 0, i = 0; i < ARRAY_SIZE (ppc_opts); i++)
1281     {
1282       col += fprintf (stream, " %s,", ppc_opts[i].opt);
1283       if (col > 66)
1284         {
1285           fprintf (stream, "\n");
1286           col = 0;
1287         }
1288     }
1289   fprintf (stream, "\n");
1290 }