3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * Author: Igor Lisitsin <igor@emcraft.com>
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 * The Ethernet Media Access Controllers (EMAC) are tested in the
32 * internal loopback mode.
33 * The controllers are configured accordingly and several packets
34 * are transmitted. The configurable test parameters are:
35 * MIN_PACKET_LENGTH - minimum size of packet to transmit
36 * MAX_PACKET_LENGTH - maximum size of packet to transmit
37 * TEST_NUM - number of tests
42 #if CONFIG_POST & CONFIG_SYS_POST_ETHER
44 #include <asm/cache.h>
46 #include <asm/processor.h>
47 #include <asm/ppc4xx-mal.h>
48 #include <asm/ppc4xx-emac.h>
51 DECLARE_GLOBAL_DATA_PTR
;
54 * Get count of EMAC devices (doesn't have to be the max. possible number
55 * supported by the cpu)
57 * CONFIG_BOARD_EMAC_COUNT added so now a "dynamic" way to configure the
58 * EMAC count is possible. As it is needed for the Kilauea/Haleakala
59 * 405EX/405EXr eval board, using the same binary.
61 #if defined(CONFIG_BOARD_EMAC_COUNT)
62 #define LAST_EMAC_NUM board_emac_count()
63 #else /* CONFIG_BOARD_EMAC_COUNT */
64 #if defined(CONFIG_HAS_ETH3)
65 #define LAST_EMAC_NUM 4
66 #elif defined(CONFIG_HAS_ETH2)
67 #define LAST_EMAC_NUM 3
68 #elif defined(CONFIG_HAS_ETH1)
69 #define LAST_EMAC_NUM 2
71 #define LAST_EMAC_NUM 1
73 #endif /* CONFIG_BOARD_EMAC_COUNT */
75 #if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
76 #define SDR0_MFR_ETH_CLK_SEL_V(n) ((0x01<<27) / (n+1))
79 #define MIN_PACKET_LENGTH 64
80 #define MAX_PACKET_LENGTH 256
83 static volatile mal_desc_t tx __cacheline_aligned
;
84 static volatile mal_desc_t rx __cacheline_aligned
;
88 int board_emac_count(void);
90 static void ether_post_init (int devnum
, int hw_addr
)
93 #if defined(CONFIG_440GX) || \
94 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
95 defined(CONFIG_440SP) || defined(CONFIG_440SPE)
99 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || defined(CONFIG_440SPE)
103 #if defined(CONFIG_440GX) || \
104 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
105 defined(CONFIG_440SP) || defined(CONFIG_440SPE)
106 /* Need to get the OPB frequency so we can access the PHY */
107 get_sys_info (&sysinfo
);
110 #if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
111 /* provide clocks for EMAC internal loopback */
112 mfsdr (SDR0_MFR
, mfr
);
113 mfr
|= SDR0_MFR_ETH_CLK_SEL_V(devnum
);
114 mtsdr (SDR0_MFR
, mfr
);
118 out_be32 ((void*)(EMAC0_MR0
+ hw_addr
), EMAC_MR0_SRST
);
122 if (!(in_be32 ((void*)(EMAC0_MR0
+ hw_addr
)) & EMAC_MR0_SRST
))
125 printf ("Timeout resetting EMAC\n");
130 #if defined(CONFIG_440GX) || \
131 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
132 defined(CONFIG_440SP) || defined(CONFIG_440SPE)
133 /* Whack the M1 register */
135 if (sysinfo
.freqOPB
<= 50000000);
136 else if (sysinfo
.freqOPB
<= 66666667)
137 mode_reg
|= EMAC_MR1_OBCI_66
;
138 else if (sysinfo
.freqOPB
<= 83333333)
139 mode_reg
|= EMAC_MR1_OBCI_83
;
140 else if (sysinfo
.freqOPB
<= 100000000)
141 mode_reg
|= EMAC_MR1_OBCI_100
;
143 mode_reg
|= EMAC_MR1_OBCI_GT100
;
145 out_be32 ((void*)(EMAC0_MR1
+ hw_addr
), mode_reg
);
147 #endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */
149 /* set the Mal configuration reg */
150 #if defined(CONFIG_440GX) || \
151 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
152 defined(CONFIG_440SP) || defined(CONFIG_440SPE)
153 mtdcr (MAL0_CFG
, MAL_CR_PLBB
| MAL_CR_OPBBL
| MAL_CR_LEA
|
154 MAL_CR_PLBLT_DEFAULT
| 0x00330000);
156 mtdcr (MAL0_CFG
, MAL_CR_PLBB
| MAL_CR_OPBBL
| MAL_CR_LEA
| MAL_CR_PLBLT_DEFAULT
);
157 /* Errata 1.12: MAL_1 -- Disable MAL bursting */
158 if (get_pvr() == PVR_440GP_RB
) {
159 mtdcr (MAL0_CFG
, mfdcr(MAL0_CFG
) & ~MAL_CR_PLBB
);
162 /* setup buffer descriptors */
163 tx
.ctrl
= MAL_TX_CTRL_WRAP
;
165 tx
.data_ptr
= (char*)L1_CACHE_ALIGN((u32
)tx_buf
);
167 rx
.ctrl
= MAL_TX_CTRL_WRAP
| MAL_RX_CTRL_EMPTY
;
169 rx
.data_ptr
= (char*)L1_CACHE_ALIGN((u32
)rx_buf
);
170 flush_dcache_range((u32
)&rx
, (u32
)&rx
+ sizeof(mal_desc_t
));
171 flush_dcache_range((u32
)&tx
, (u32
)&tx
+ sizeof(mal_desc_t
));
175 /* setup MAL tx & rx channel pointers */
176 #if defined (CONFIG_405EP) || defined (CONFIG_440EP) || defined (CONFIG_440GR)
177 mtdcr (MAL0_TXCTP2R
, &tx
);
179 mtdcr (MAL0_TXCTP1R
, &tx
);
181 #if defined(CONFIG_440)
182 mtdcr (MAL0_TXBADDR
, 0x0);
183 mtdcr (MAL0_RXBADDR
, 0x0);
185 mtdcr (MAL0_RXCTP1R
, &rx
);
186 /* set RX buffer size */
187 mtdcr (MAL0_RCBS1
, PKTSIZE_ALIGN
/ 16);
191 /* setup MAL tx & rx channel pointers */
192 #if defined(CONFIG_440)
193 mtdcr (MAL0_TXBADDR
, 0x0);
194 mtdcr (MAL0_RXBADDR
, 0x0);
196 mtdcr (MAL0_TXCTP0R
, &tx
);
197 mtdcr (MAL0_RXCTP0R
, &rx
);
198 /* set RX buffer size */
199 mtdcr (MAL0_RCBS0
, PKTSIZE_ALIGN
/ 16);
203 /* Enable MAL transmit and receive channels */
204 #if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
205 mtdcr (MAL0_TXCASR
, (MAL_TXRX_CASR
>> (devnum
*2)));
207 mtdcr (MAL0_TXCASR
, (MAL_TXRX_CASR
>> devnum
));
209 mtdcr (MAL0_RXCASR
, (MAL_TXRX_CASR
>> devnum
));
211 /* set internal loopback mode */
212 #ifdef CONFIG_SYS_POST_ETHER_EXT_LOOPBACK
213 out_be32 ((void*)(EMAC0_MR1
+ hw_addr
), EMAC_MR1_FDE
| 0 |
214 EMAC_MR1_RFS_4K
| EMAC_MR1_TX_FIFO_2K
|
215 EMAC_MR1_MF_100MBPS
| EMAC_MR1_IST
|
216 in_be32 ((void*)(EMAC0_MR1
+ hw_addr
)));
218 out_be32 ((void*)(EMAC0_MR1
+ hw_addr
), EMAC_MR1_FDE
| EMAC_MR1_ILE
|
219 EMAC_MR1_RFS_4K
| EMAC_MR1_TX_FIFO_2K
|
220 EMAC_MR1_MF_100MBPS
| EMAC_MR1_IST
|
221 in_be32 ((void*)(EMAC0_MR1
+ hw_addr
)));
224 /* set transmit enable & receive enable */
225 out_be32 ((void*)(EMAC0_MR0
+ hw_addr
), EMAC_MR0_TXE
| EMAC_MR0_RXE
);
227 /* enable broadcast address */
228 out_be32 ((void*)(EMAC0_RXM
+ hw_addr
), EMAC_RMR_BAE
);
230 /* set transmit request threshold register */
231 out_be32 ((void*)(EMAC0_TRTR
+ hw_addr
), 0x18000000); /* 256 byte threshold */
233 /* set receive low/high water mark register */
234 #if defined(CONFIG_440)
235 /* 440s has a 64 byte burst length */
236 out_be32 ((void*)(EMAC0_RX_HI_LO_WMARK
+ hw_addr
), 0x80009000);
238 /* 405s have a 16 byte burst length */
239 out_be32 ((void*)(EMAC0_RX_HI_LO_WMARK
+ hw_addr
), 0x0f002000);
240 #endif /* defined(CONFIG_440) */
241 out_be32 ((void*)(EMAC0_TMR1
+ hw_addr
), 0xf8640000);
243 /* Set fifo limit entry in tx mode 0 */
244 out_be32 ((void*)(EMAC0_TMR0
+ hw_addr
), 0x00000003);
246 out_be32 ((void*)(EMAC0_I_FRAME_GAP_REG
+ hw_addr
), 0x00000008);
250 static void ether_post_halt (int devnum
, int hw_addr
)
253 #if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
257 /* 1st reset MAL channel */
258 /* Note: writing a 0 to a channel has no effect */
259 #if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
260 mtdcr (MAL0_TXCARR
, MAL_TXRX_CASR
>> (devnum
* 2));
262 mtdcr (MAL0_TXCARR
, MAL_TXRX_CASR
>> devnum
);
264 mtdcr (MAL0_RXCARR
, MAL_TXRX_CASR
>> devnum
);
267 while (mfdcr (MAL0_RXCASR
) & (MAL_TXRX_CASR
>> devnum
)) {
273 out_be32 ((void*)(EMAC0_MR0
+ hw_addr
), EMAC_MR0_SRST
);
275 #if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
276 /* remove clocks for EMAC internal loopback */
277 mfsdr (SDR0_MFR
, mfr
);
278 mfr
&= ~SDR0_MFR_ETH_CLK_SEL_V(devnum
);
279 mtsdr (SDR0_MFR
, mfr
);
283 static void ether_post_send (int devnum
, int hw_addr
, void *packet
, int length
)
287 while (tx
.ctrl
& MAL_TX_CTRL_READY
) {
289 printf ("TX timeout\n");
293 invalidate_dcache_range((u32
)&tx
, (u32
)&tx
+ sizeof(mal_desc_t
));
295 tx
.ctrl
= MAL_TX_CTRL_READY
| MAL_TX_CTRL_WRAP
| MAL_TX_CTRL_LAST
|
296 EMAC_TX_CTRL_GFCS
| EMAC_TX_CTRL_GP
;
297 tx
.data_len
= length
;
298 memcpy (tx
.data_ptr
, packet
, length
);
299 flush_dcache_range((u32
)&tx
, (u32
)&tx
+ sizeof(mal_desc_t
));
300 flush_dcache_range((u32
)tx
.data_ptr
, (u32
)tx
.data_ptr
+ length
);
303 out_be32 ((void*)(EMAC0_TMR0
+ hw_addr
), in_be32 ((void*)(EMAC0_TMR0
+ hw_addr
)) | EMAC_TMR0_GNP0
);
307 static int ether_post_recv (int devnum
, int hw_addr
, void *packet
, int max_length
)
312 while (rx
.ctrl
& MAL_RX_CTRL_EMPTY
) {
314 printf ("RX timeout\n");
318 invalidate_dcache_range((u32
)&rx
, (u32
)&rx
+ sizeof(mal_desc_t
));
320 length
= rx
.data_len
- 4;
321 if (length
<= max_length
) {
322 invalidate_dcache_range((u32
)rx
.data_ptr
, (u32
)rx
.data_ptr
+ length
);
323 memcpy(packet
, rx
.data_ptr
, length
);
327 rx
.ctrl
|= MAL_RX_CTRL_EMPTY
;
328 flush_dcache_range((u32
)&rx
, (u32
)&rx
+ sizeof(mal_desc_t
));
338 static void packet_fill (char *packet
, int length
)
340 char c
= (char) length
;
343 /* set up ethernet header */
344 memset (packet
, 0xff, 14);
346 for (i
= 14; i
< length
; i
++) {
351 static int packet_check (char *packet
, int length
)
353 char c
= (char) length
;
356 for (i
= 14; i
< length
; i
++) {
357 if (packet
[i
] != c
++)
364 static int test_ctlr (int devnum
, int hw_addr
)
367 char packet_send
[MAX_PACKET_LENGTH
];
368 char packet_recv
[MAX_PACKET_LENGTH
];
373 ether_post_init (devnum
, hw_addr
);
375 for (i
= 0; i
< TEST_NUM
; i
++) {
376 for (l
= MIN_PACKET_LENGTH
; l
<= MAX_PACKET_LENGTH
; l
++) {
377 packet_fill (packet_send
, l
);
379 ether_post_send (devnum
, hw_addr
, packet_send
, l
);
381 length
= ether_post_recv (devnum
, hw_addr
, packet_recv
,
382 sizeof (packet_recv
));
384 if (length
!= l
|| packet_check (packet_recv
, length
) < 0) {
394 ether_post_halt (devnum
, hw_addr
);
397 post_log ("EMAC%d test failed\n", devnum
);
403 int ether_post_test (int flags
)
408 /* Allocate tx & rx packet buffers */
409 tx_buf
= malloc (PKTSIZE_ALIGN
+ CONFIG_SYS_CACHELINE_SIZE
);
410 rx_buf
= malloc (PKTSIZE_ALIGN
+ CONFIG_SYS_CACHELINE_SIZE
);
412 if (!tx_buf
|| !rx_buf
) {
413 printf ("Failed to allocate packet buffers\n");
418 for (i
= 0; i
< LAST_EMAC_NUM
; i
++) {
419 if (test_ctlr (i
, i
*0x100))
430 #endif /* CONFIG_POST & CONFIG_SYS_POST_ETHER */