3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * Author: Igor Lisitsin <igor@emcraft.com>
7 * SPDX-License-Identifier: GPL-2.0+
15 * The Ethernet Media Access Controllers (EMAC) are tested in the
16 * internal loopback mode.
17 * The controllers are configured accordingly and several packets
18 * are transmitted. The configurable test parameters are:
19 * MIN_PACKET_LENGTH - minimum size of packet to transmit
20 * MAX_PACKET_LENGTH - maximum size of packet to transmit
21 * CONFIG_SYS_POST_ETH_LOOPS - Number of test loops. Each loop
22 * is tested with a different frame length. Starting with
23 * MAX_PACKET_LENGTH and going down to MIN_PACKET_LENGTH.
24 * Defaults to 10 and can be overriden in the board config header.
29 #if CONFIG_POST & CONFIG_SYS_POST_ETHER
31 #include <asm/cache.h>
33 #include <asm/processor.h>
34 #include <asm/ppc4xx-mal.h>
35 #include <asm/ppc4xx-emac.h>
38 DECLARE_GLOBAL_DATA_PTR
;
41 * Get count of EMAC devices (doesn't have to be the max. possible number
42 * supported by the cpu)
44 * CONFIG_BOARD_EMAC_COUNT added so now a "dynamic" way to configure the
45 * EMAC count is possible. As it is needed for the Kilauea/Haleakala
46 * 405EX/405EXr eval board, using the same binary.
48 #if defined(CONFIG_BOARD_EMAC_COUNT)
49 #define LAST_EMAC_NUM board_emac_count()
50 #else /* CONFIG_BOARD_EMAC_COUNT */
51 #if defined(CONFIG_HAS_ETH3)
52 #define LAST_EMAC_NUM 4
53 #elif defined(CONFIG_HAS_ETH2)
54 #define LAST_EMAC_NUM 3
55 #elif defined(CONFIG_HAS_ETH1)
56 #define LAST_EMAC_NUM 2
58 #define LAST_EMAC_NUM 1
60 #endif /* CONFIG_BOARD_EMAC_COUNT */
62 #if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
63 #define SDR0_MFR_ETH_CLK_SEL_V(n) ((0x01<<27) / (n+1))
66 #define MIN_PACKET_LENGTH 64
67 #define MAX_PACKET_LENGTH 1514
68 #ifndef CONFIG_SYS_POST_ETH_LOOPS
69 #define CONFIG_SYS_POST_ETH_LOOPS 10
71 #define PACKET_INCR ((MAX_PACKET_LENGTH - MIN_PACKET_LENGTH) / \
72 CONFIG_SYS_POST_ETH_LOOPS)
74 static volatile mal_desc_t tx __cacheline_aligned
;
75 static volatile mal_desc_t rx __cacheline_aligned
;
79 int board_emac_count(void);
81 static void ether_post_init (int devnum
, int hw_addr
)
84 #if defined(CONFIG_440GX) || \
85 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
86 defined(CONFIG_440SP) || defined(CONFIG_440SPE)
90 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || defined(CONFIG_440SPE)
94 #if defined(CONFIG_440GX) || \
95 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
96 defined(CONFIG_440SP) || defined(CONFIG_440SPE)
97 /* Need to get the OPB frequency so we can access the PHY */
98 get_sys_info (&sysinfo
);
101 #if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
102 /* provide clocks for EMAC internal loopback */
103 mfsdr (SDR0_MFR
, mfr
);
104 mfr
|= SDR0_MFR_ETH_CLK_SEL_V(devnum
);
105 mtsdr (SDR0_MFR
, mfr
);
109 out_be32 ((void*)(EMAC0_MR0
+ hw_addr
), EMAC_MR0_SRST
);
113 if (!(in_be32 ((void*)(EMAC0_MR0
+ hw_addr
)) & EMAC_MR0_SRST
))
116 printf ("Timeout resetting EMAC\n");
121 #if defined(CONFIG_440GX) || \
122 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
123 defined(CONFIG_440SP) || defined(CONFIG_440SPE)
124 /* Whack the M1 register */
126 if (sysinfo
.freqOPB
<= 50000000);
127 else if (sysinfo
.freqOPB
<= 66666667)
128 mode_reg
|= EMAC_MR1_OBCI_66
;
129 else if (sysinfo
.freqOPB
<= 83333333)
130 mode_reg
|= EMAC_MR1_OBCI_83
;
131 else if (sysinfo
.freqOPB
<= 100000000)
132 mode_reg
|= EMAC_MR1_OBCI_100
;
134 mode_reg
|= EMAC_MR1_OBCI_GT100
;
136 out_be32 ((void*)(EMAC0_MR1
+ hw_addr
), mode_reg
);
138 #endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */
140 /* set the Mal configuration reg */
141 #if defined(CONFIG_440GX) || \
142 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
143 defined(CONFIG_440SP) || defined(CONFIG_440SPE)
144 mtdcr (MAL0_CFG
, MAL_CR_PLBB
| MAL_CR_OPBBL
| MAL_CR_LEA
|
145 MAL_CR_PLBLT_DEFAULT
| 0x00330000);
147 mtdcr (MAL0_CFG
, MAL_CR_PLBB
| MAL_CR_OPBBL
| MAL_CR_LEA
| MAL_CR_PLBLT_DEFAULT
);
148 /* Errata 1.12: MAL_1 -- Disable MAL bursting */
149 if (get_pvr() == PVR_440GP_RB
) {
150 mtdcr (MAL0_CFG
, mfdcr(MAL0_CFG
) & ~MAL_CR_PLBB
);
153 /* setup buffer descriptors */
154 tx
.ctrl
= MAL_TX_CTRL_WRAP
;
156 tx
.data_ptr
= (char*)L1_CACHE_ALIGN((u32
)tx_buf
);
158 rx
.ctrl
= MAL_TX_CTRL_WRAP
| MAL_RX_CTRL_EMPTY
;
160 rx
.data_ptr
= (char*)L1_CACHE_ALIGN((u32
)rx_buf
);
161 flush_dcache_range((u32
)&rx
, (u32
)&rx
+ sizeof(mal_desc_t
));
162 flush_dcache_range((u32
)&tx
, (u32
)&tx
+ sizeof(mal_desc_t
));
166 /* setup MAL tx & rx channel pointers */
167 #if defined (CONFIG_405EP) || defined (CONFIG_440EP) || defined (CONFIG_440GR)
168 mtdcr (MAL0_TXCTP2R
, &tx
);
170 mtdcr (MAL0_TXCTP1R
, &tx
);
172 #if defined(CONFIG_440)
173 mtdcr (MAL0_TXBADDR
, 0x0);
174 mtdcr (MAL0_RXBADDR
, 0x0);
176 mtdcr (MAL0_RXCTP1R
, &rx
);
177 /* set RX buffer size */
178 mtdcr (MAL0_RCBS1
, PKTSIZE_ALIGN
/ 16);
182 /* setup MAL tx & rx channel pointers */
183 #if defined(CONFIG_440)
184 mtdcr (MAL0_TXBADDR
, 0x0);
185 mtdcr (MAL0_RXBADDR
, 0x0);
187 mtdcr (MAL0_TXCTP0R
, &tx
);
188 mtdcr (MAL0_RXCTP0R
, &rx
);
189 /* set RX buffer size */
190 mtdcr (MAL0_RCBS0
, PKTSIZE_ALIGN
/ 16);
194 /* Enable MAL transmit and receive channels */
195 #if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
196 mtdcr (MAL0_TXCASR
, (MAL_TXRX_CASR
>> (devnum
*2)));
198 mtdcr (MAL0_TXCASR
, (MAL_TXRX_CASR
>> devnum
));
200 mtdcr (MAL0_RXCASR
, (MAL_TXRX_CASR
>> devnum
));
202 /* set internal loopback mode */
203 #ifdef CONFIG_SYS_POST_ETHER_EXT_LOOPBACK
204 out_be32 ((void*)(EMAC0_MR1
+ hw_addr
), EMAC_MR1_FDE
| 0 |
205 EMAC_MR1_RFS_4K
| EMAC_MR1_TX_FIFO_2K
|
206 EMAC_MR1_MF_100MBPS
| EMAC_MR1_IST
|
207 in_be32 ((void*)(EMAC0_MR1
+ hw_addr
)));
209 out_be32 ((void*)(EMAC0_MR1
+ hw_addr
), EMAC_MR1_FDE
| EMAC_MR1_ILE
|
210 EMAC_MR1_RFS_4K
| EMAC_MR1_TX_FIFO_2K
|
211 EMAC_MR1_MF_100MBPS
| EMAC_MR1_IST
|
212 in_be32 ((void*)(EMAC0_MR1
+ hw_addr
)));
215 /* set transmit enable & receive enable */
216 out_be32 ((void*)(EMAC0_MR0
+ hw_addr
), EMAC_MR0_TXE
| EMAC_MR0_RXE
);
218 /* enable broadcast address */
219 out_be32 ((void*)(EMAC0_RXM
+ hw_addr
), EMAC_RMR_BAE
);
221 /* set transmit request threshold register */
222 out_be32 ((void*)(EMAC0_TRTR
+ hw_addr
), 0x18000000); /* 256 byte threshold */
224 /* set receive low/high water mark register */
225 #if defined(CONFIG_440)
226 /* 440s has a 64 byte burst length */
227 out_be32 ((void*)(EMAC0_RX_HI_LO_WMARK
+ hw_addr
), 0x80009000);
229 /* 405s have a 16 byte burst length */
230 out_be32 ((void*)(EMAC0_RX_HI_LO_WMARK
+ hw_addr
), 0x0f002000);
231 #endif /* defined(CONFIG_440) */
232 out_be32 ((void*)(EMAC0_TMR1
+ hw_addr
), 0xf8640000);
234 /* Set fifo limit entry in tx mode 0 */
235 out_be32 ((void*)(EMAC0_TMR0
+ hw_addr
), 0x00000003);
237 out_be32 ((void*)(EMAC0_I_FRAME_GAP_REG
+ hw_addr
), 0x00000008);
241 static void ether_post_halt (int devnum
, int hw_addr
)
244 #if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
248 /* 1st reset MAL channel */
249 /* Note: writing a 0 to a channel has no effect */
250 #if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
251 mtdcr (MAL0_TXCARR
, MAL_TXRX_CASR
>> (devnum
* 2));
253 mtdcr (MAL0_TXCARR
, MAL_TXRX_CASR
>> devnum
);
255 mtdcr (MAL0_RXCARR
, MAL_TXRX_CASR
>> devnum
);
258 while (mfdcr (MAL0_RXCASR
) & (MAL_TXRX_CASR
>> devnum
)) {
264 out_be32 ((void*)(EMAC0_MR0
+ hw_addr
), EMAC_MR0_SRST
);
266 #if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
267 /* remove clocks for EMAC internal loopback */
268 mfsdr (SDR0_MFR
, mfr
);
269 mfr
&= ~SDR0_MFR_ETH_CLK_SEL_V(devnum
);
270 mtsdr (SDR0_MFR
, mfr
);
274 static void ether_post_send (int devnum
, int hw_addr
, void *packet
, int length
)
278 while (tx
.ctrl
& MAL_TX_CTRL_READY
) {
280 printf ("TX timeout\n");
284 invalidate_dcache_range((u32
)&tx
, (u32
)&tx
+ sizeof(mal_desc_t
));
286 tx
.ctrl
= MAL_TX_CTRL_READY
| MAL_TX_CTRL_WRAP
| MAL_TX_CTRL_LAST
|
287 EMAC_TX_CTRL_GFCS
| EMAC_TX_CTRL_GP
;
288 tx
.data_len
= length
;
289 memcpy (tx
.data_ptr
, packet
, length
);
290 flush_dcache_range((u32
)&tx
, (u32
)&tx
+ sizeof(mal_desc_t
));
291 flush_dcache_range((u32
)tx
.data_ptr
, (u32
)tx
.data_ptr
+ length
);
294 out_be32 ((void*)(EMAC0_TMR0
+ hw_addr
), in_be32 ((void*)(EMAC0_TMR0
+ hw_addr
)) | EMAC_TMR0_GNP0
);
298 static int ether_post_recv (int devnum
, int hw_addr
, void *packet
, int max_length
)
303 while (rx
.ctrl
& MAL_RX_CTRL_EMPTY
) {
305 printf ("RX timeout\n");
309 invalidate_dcache_range((u32
)&rx
, (u32
)&rx
+ sizeof(mal_desc_t
));
311 length
= rx
.data_len
- 4;
312 if (length
<= max_length
) {
313 invalidate_dcache_range((u32
)rx
.data_ptr
, (u32
)rx
.data_ptr
+ length
);
314 memcpy(packet
, rx
.data_ptr
, length
);
318 rx
.ctrl
|= MAL_RX_CTRL_EMPTY
;
319 flush_dcache_range((u32
)&rx
, (u32
)&rx
+ sizeof(mal_desc_t
));
329 static void packet_fill (char *packet
, int length
)
331 char c
= (char) length
;
334 /* set up ethernet header */
335 memset (packet
, 0xff, 14);
337 for (i
= 14; i
< length
; i
++) {
342 static int packet_check (char *packet
, int length
)
344 char c
= (char) length
;
347 for (i
= 14; i
< length
; i
++) {
348 if (packet
[i
] != c
++)
355 char packet_send
[MAX_PACKET_LENGTH
];
356 char packet_recv
[MAX_PACKET_LENGTH
];
357 static int test_ctlr (int devnum
, int hw_addr
)
363 ether_post_init (devnum
, hw_addr
);
365 for (l
= MAX_PACKET_LENGTH
; l
>= MIN_PACKET_LENGTH
;
367 packet_fill (packet_send
, l
);
369 ether_post_send (devnum
, hw_addr
, packet_send
, l
);
371 length
= ether_post_recv (devnum
, hw_addr
, packet_recv
,
372 sizeof (packet_recv
));
374 if (length
!= l
|| packet_check (packet_recv
, length
) < 0) {
383 ether_post_halt (devnum
, hw_addr
);
386 post_log ("EMAC%d test failed\n", devnum
);
392 int ether_post_test (int flags
)
397 /* Allocate tx & rx packet buffers */
398 tx_buf
= malloc (PKTSIZE_ALIGN
+ CONFIG_SYS_CACHELINE_SIZE
);
399 rx_buf
= malloc (PKTSIZE_ALIGN
+ CONFIG_SYS_CACHELINE_SIZE
);
401 if (!tx_buf
|| !rx_buf
) {
402 printf ("Failed to allocate packet buffers\n");
407 for (i
= 0; i
< LAST_EMAC_NUM
; i
++) {
408 if (test_ctlr (i
, i
*0x100))
419 #endif /* CONFIG_POST & CONFIG_SYS_POST_ETHER */