]>
git.ipfire.org Git - people/ms/u-boot.git/blob - post/cpu/ppc4xx/uart.c
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * Author: Igor Lisitsin <igor@emcraft.com>
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 * The controllers are configured to loopback mode and several
32 * characters are transmitted.
37 #if CONFIG_POST & CFG_POST_UART
40 * This table defines the UART's that should be tested and can
41 * be overridden in the board config file
43 #ifndef CFG_POST_UART_TABLE
44 #define CFG_POST_UART_TABLE {UART0_BASE, UART1_BASE, UART2_BASE, UART3_BASE}
47 #include <asm/processor.h>
50 #if defined(CONFIG_440)
51 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
52 defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
53 #define UART0_BASE CFG_PERIPHERAL_BASE + 0x00000300
54 #define UART1_BASE CFG_PERIPHERAL_BASE + 0x00000400
55 #define UART2_BASE CFG_PERIPHERAL_BASE + 0x00000500
56 #define UART3_BASE CFG_PERIPHERAL_BASE + 0x00000600
58 #define UART0_BASE CFG_PERIPHERAL_BASE + 0x00000200
59 #define UART1_BASE CFG_PERIPHERAL_BASE + 0x00000300
62 #if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
63 #define UART2_BASE CFG_PERIPHERAL_BASE + 0x00000600
66 #if defined(CONFIG_440GP)
67 #define CR0_MASK 0x3fff0000
68 #define CR0_EXTCLK_ENA 0x00600000
69 #define CR0_UDIV_POS 16
70 #define UDIV_SUBTRACT 1
71 #define UART0_SDR cntrl0
72 #define MFREG(a, d) d = mfdcr(a)
73 #define MTREG(a, d) mtdcr(a, d)
74 #else /* #if defined(CONFIG_440GP) */
75 /* all other 440 PPC's access clock divider via sdr register */
76 #define CR0_MASK 0xdfffffff
77 #define CR0_EXTCLK_ENA 0x00800000
78 #define CR0_UDIV_POS 0
79 #define UDIV_SUBTRACT 0
80 #define UART0_SDR sdr_uart0
81 #define UART1_SDR sdr_uart1
82 #if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
83 defined(CONFIG_440GR) || defined(CONFIG_440GRX) || \
84 defined(CONFIG_440SP) || defined(CONFIG_440SPE)
85 #define UART2_SDR sdr_uart2
87 #if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
88 defined(CONFIG_440GR) || defined(CONFIG_440GRX)
89 #define UART3_SDR sdr_uart3
91 #define MFREG(a, d) mfsdr(a, d)
92 #define MTREG(a, d) mtsdr(a, d)
93 #endif /* #if defined(CONFIG_440GP) */
94 #elif defined(CONFIG_405EP) || defined(CONFIG_405EZ)
95 #define UART0_BASE 0xef600300
96 #define UART1_BASE 0xef600400
97 #define UCR0_MASK 0x0000007f
98 #define UCR1_MASK 0x00007f00
99 #define UCR0_UDIV_POS 0
100 #define UCR1_UDIV_POS 8
102 #elif defined(CONFIG_405EX)
103 #define UART0_BASE 0xef600200
104 #define UART1_BASE 0xef600300
105 #define CR0_MASK 0x000000ff
106 #define CR0_EXTCLK_ENA 0x00800000
107 #define CR0_UDIV_POS 0
108 #define UDIV_SUBTRACT 0
109 #define UART0_SDR sdr_uart0
110 #define UART1_SDR sdr_uart1
111 #define MFREG(a, d) mfsdr(a, d)
112 #define MTREG(a, d) mtsdr(a, d)
113 #else /* CONFIG_405GP || CONFIG_405CR */
114 #define UART0_BASE 0xef600300
115 #define UART1_BASE 0xef600400
116 #define CR0_MASK 0x00001fff
117 #define CR0_EXTCLK_ENA 0x000000c0
118 #define CR0_UDIV_POS 1
122 #define UART_RBR 0x00
123 #define UART_THR 0x00
124 #define UART_IER 0x01
125 #define UART_IIR 0x02
126 #define UART_FCR 0x02
127 #define UART_LCR 0x03
128 #define UART_MCR 0x04
129 #define UART_LSR 0x05
130 #define UART_MSR 0x06
131 #define UART_SCR 0x07
132 #define UART_DLL 0x00
133 #define UART_DLM 0x01
136 * Line Status Register.
138 #define asyncLSRDataReady1 0x01
139 #define asyncLSROverrunError1 0x02
140 #define asyncLSRParityError1 0x04
141 #define asyncLSRFramingError1 0x08
142 #define asyncLSRBreakInterrupt1 0x10
143 #define asyncLSRTxHoldEmpty1 0x20
144 #define asyncLSRTxShiftEmpty1 0x40
145 #define asyncLSRRxFifoError1 0x80
147 DECLARE_GLOBAL_DATA_PTR
;
149 #if defined(CONFIG_440) || defined(CONFIG_405EX)
150 #if !defined(CFG_EXT_SERIAL_CLOCK)
151 static void serial_divs (int baudrate
, unsigned long *pudiv
,
152 unsigned short *pbdiv
)
155 unsigned long div
; /* total divisor udiv * bdiv */
156 unsigned long umin
; /* minimum udiv */
157 unsigned short diff
; /* smallest diff */
158 unsigned long udiv
; /* best udiv */
159 unsigned short idiff
; /* current diff */
160 unsigned short ibdiv
; /* current bdiv */
162 unsigned long est
; /* current estimate */
164 get_sys_info(&sysinfo
);
166 udiv
= 32; /* Assume lowest possible serial clk */
167 div
= sysinfo
.freqPLB
/ (16 * baudrate
); /* total divisor */
168 umin
= sysinfo
.pllOpbDiv
<< 1; /* 2 x OPB divisor */
169 diff
= 32; /* highest possible */
171 /* i is the test udiv value -- start with the largest
172 * possible (32) to minimize serial clock and constrain
175 for (i
= 32; i
> umin
; i
--) {
178 idiff
= (est
> div
) ? (est
-div
) : (div
-est
);
181 break; /* can't do better */
182 } else if (idiff
< diff
) {
183 udiv
= i
; /* best so far */
184 diff
= idiff
; /* update lowest diff*/
193 static int uart_post_init (unsigned long dev_base
)
195 unsigned long reg
= 0;
199 #ifdef CFG_EXT_SERIAL_CLOCK
204 for (i
= 0; i
< 3500; i
++) {
205 if (in8 (dev_base
+ UART_LSR
) & asyncLSRTxHoldEmpty1
)
209 MFREG(UART0_SDR
, reg
);
212 #ifdef CFG_EXT_SERIAL_CLOCK
213 reg
|= CR0_EXTCLK_ENA
;
215 tmp
= gd
->baudrate
* 16;
216 bdiv
= (CFG_EXT_SERIAL_CLOCK
+ tmp
/ 2) / tmp
;
218 /* For 440, the cpu clock is on divider chain A, UART on divider
219 * chain B ... so cpu clock is irrelevant. Get the "optimized"
220 * values that are subject to the 1/2 opb clock constraint
222 serial_divs (gd
->baudrate
, &udiv
, &bdiv
);
225 reg
|= (udiv
- UDIV_SUBTRACT
) << CR0_UDIV_POS
; /* set the UART divisor */
228 * Configure input clock to baudrate generator for all
229 * available serial ports here
231 MTREG(UART0_SDR
, reg
);
232 #if defined(UART1_SDR)
233 MTREG(UART1_SDR
, reg
);
235 #if defined(UART2_SDR)
236 MTREG(UART2_SDR
, reg
);
238 #if defined(UART3_SDR)
239 MTREG(UART3_SDR
, reg
);
242 out8(dev_base
+ UART_LCR
, 0x80); /* set DLAB bit */
243 out8(dev_base
+ UART_DLL
, bdiv
); /* set baudrate divisor */
244 out8(dev_base
+ UART_DLM
, bdiv
>> 8); /* set baudrate divisor */
245 out8(dev_base
+ UART_LCR
, 0x03); /* clear DLAB; set 8 bits, no parity */
246 out8(dev_base
+ UART_FCR
, 0x00); /* disable FIFO */
247 out8(dev_base
+ UART_MCR
, 0x10); /* enable loopback mode */
248 val
= in8(dev_base
+ UART_LSR
); /* clear line status */
249 val
= in8(dev_base
+ UART_RBR
); /* read receive buffer */
250 out8(dev_base
+ UART_SCR
, 0x00); /* set scratchpad */
251 out8(dev_base
+ UART_IER
, 0x00); /* set interrupt enable reg */
256 #else /* CONFIG_440 */
258 static int uart_post_init (unsigned long dev_base
)
268 for (i
= 0; i
< 3500; i
++) {
269 if (in8 (dev_base
+ UART_LSR
) & asyncLSRTxHoldEmpty1
)
274 #if defined(CONFIG_405EZ)
275 serial_divs(gd
->baudrate
, &udiv
, &bdiv
);
279 reg
= mfdcr(cpc0_ucr
) & ~(UCR0_MASK
| UCR1_MASK
);
281 tmp
= CFG_BASE_BAUD
* 16;
282 udiv
= (clk
+ tmp
/ 2) / tmp
;
283 if (udiv
> UDIV_MAX
) /* max. n bits for udiv */
285 reg
|= (udiv
) << UCR0_UDIV_POS
; /* set the UART divisor */
286 reg
|= (udiv
) << UCR1_UDIV_POS
; /* set the UART divisor */
287 mtdcr (cpc0_ucr
, reg
);
288 #else /* CONFIG_405EP */
289 reg
= mfdcr(cntrl0
) & ~CR0_MASK
;
290 #ifdef CFG_EXT_SERIAL_CLOCK
291 clk
= CFG_EXT_SERIAL_CLOCK
;
293 reg
|= CR0_EXTCLK_ENA
;
296 #ifdef CFG_405_UART_ERRATA_59
297 udiv
= 31; /* Errata 59: stuck at 31 */
299 tmp
= CFG_BASE_BAUD
* 16;
300 udiv
= (clk
+ tmp
/ 2) / tmp
;
301 if (udiv
> UDIV_MAX
) /* max. n bits for udiv */
305 reg
|= (udiv
- 1) << CR0_UDIV_POS
; /* set the UART divisor */
307 #endif /* CONFIG_405EP */
308 tmp
= gd
->baudrate
* udiv
* 16;
309 bdiv
= (clk
+ tmp
/ 2) / tmp
;
310 #endif /* CONFIG_405EZ */
312 out8(dev_base
+ UART_LCR
, 0x80); /* set DLAB bit */
313 out8(dev_base
+ UART_DLL
, bdiv
); /* set baudrate divisor */
314 out8(dev_base
+ UART_DLM
, bdiv
>> 8); /* set baudrate divisor */
315 out8(dev_base
+ UART_LCR
, 0x03); /* clear DLAB; set 8 bits, no parity */
316 out8(dev_base
+ UART_FCR
, 0x00); /* disable FIFO */
317 out8(dev_base
+ UART_MCR
, 0x10); /* enable loopback mode */
318 val
= in8(dev_base
+ UART_LSR
); /* clear line status */
319 val
= in8(dev_base
+ UART_RBR
); /* read receive buffer */
320 out8(dev_base
+ UART_SCR
, 0x00); /* set scratchpad */
321 out8(dev_base
+ UART_IER
, 0x00); /* set interrupt enable reg */
325 #endif /* CONFIG_440 */
327 static void uart_post_putc (unsigned long dev_base
, char c
)
331 out8 (dev_base
+ UART_THR
, c
); /* put character out */
333 /* Wait for transfer completion */
334 for (i
= 0; i
< 3500; i
++) {
335 if (in8 (dev_base
+ UART_LSR
) & asyncLSRTxHoldEmpty1
)
341 static int uart_post_getc (unsigned long dev_base
)
345 /* Wait for character available */
346 for (i
= 0; i
< 3500; i
++) {
347 if (in8 (dev_base
+ UART_LSR
) & asyncLSRDataReady1
)
351 return 0xff & in8 (dev_base
+ UART_RBR
);
354 static int test_ctlr (unsigned long dev_base
, int index
)
357 char test_str
[] = "*** UART Test String ***\r\n";
360 uart_post_init (dev_base
);
362 for (i
= 0; i
< sizeof (test_str
) - 1; i
++) {
363 uart_post_putc (dev_base
, test_str
[i
]);
364 if (uart_post_getc (dev_base
) != test_str
[i
])
370 post_log ("uart%d test failed\n", index
);
375 int uart_post_test (int flags
)
378 static unsigned long base
[] = CFG_POST_UART_TABLE
;
380 for (i
= 0; i
< sizeof (base
) / sizeof (base
[0]); i
++) {
381 if (test_ctlr (base
[i
], i
))
384 serial_reinit_all ();
389 #endif /* CONFIG_POST & CFG_POST_UART */