post/cpu/ppc4xx/uart.c

   1 /*
   2  * (C) Copyright 2007
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * Author: Igor Lisitsin <igor@emcraft.com>
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 #include <common.h>
  27
  28 /*
  29  * UART test
  30  *
  31  * The controllers are configured to loopback mode and several
  32  * characters are transmitted.
  33  */
  34
  35 #ifdef CONFIG_POST
  36
  37 #include <post.h>
  38
  39 #if CONFIG_POST & CFG_POST_UART
  40
  41 /*
  42  * This table defines the UART's that should be tested and can
  43  * be overridden in the board config file
  44  */
  45 #ifndef CFG_POST_UART_TABLE
  46 #define CFG_POST_UART_TABLE     {UART0_BASE, UART1_BASE, UART2_BASE, UART3_BASE}
  47 #endif
  48
  49 #include <asm/processor.h>
  50 #include <serial.h>
  51
  52 #if defined(CONFIG_440)
  53 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
  54     defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
  55 #define UART0_BASE  CFG_PERIPHERAL_BASE + 0x00000300
  56 #define UART1_BASE  CFG_PERIPHERAL_BASE + 0x00000400
  57 #define UART2_BASE  CFG_PERIPHERAL_BASE + 0x00000500
  58 #define UART3_BASE  CFG_PERIPHERAL_BASE + 0x00000600
  59 #else
  60 #define UART0_BASE  CFG_PERIPHERAL_BASE + 0x00000200
  61 #define UART1_BASE  CFG_PERIPHERAL_BASE + 0x00000300
  62 #endif
  63
  64 #if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
  65 #define UART2_BASE  CFG_PERIPHERAL_BASE + 0x00000600
  66 #endif
  67
  68 #if defined(CONFIG_440GP)
  69 #define CR0_MASK        0x3fff0000
  70 #define CR0_EXTCLK_ENA  0x00600000
  71 #define CR0_UDIV_POS    16
  72 #define UDIV_SUBTRACT   1
  73 #define UART0_SDR       cntrl0
  74 #define MFREG(a, d)     d = mfdcr(a)
  75 #define MTREG(a, d)     mtdcr(a, d)
  76 #else /* #if defined(CONFIG_440GP) */
  77 /* all other 440 PPC's access clock divider via sdr register */
  78 #define CR0_MASK        0xdfffffff
  79 #define CR0_EXTCLK_ENA  0x00800000
  80 #define CR0_UDIV_POS    0
  81 #define UDIV_SUBTRACT   0
  82 #define UART0_SDR       sdr_uart0
  83 #define UART1_SDR       sdr_uart1
  84 #if defined(CONFIG_440EP) || defined(CONFIG_440EPx) || \
  85     defined(CONFIG_440GR) || defined(CONFIG_440GRx) || \
  86     defined(CONFIG_440SP) || defined(CONFIG_440SPe)
  87 #define UART2_SDR       sdr_uart2
  88 #endif
  89 #if defined(CONFIG_440EP) || defined(CONFIG_440EPx) || \
  90     defined(CONFIG_440GR) || defined(CONFIG_440GRx)
  91 #define UART3_SDR       sdr_uart3
  92 #endif
  93 #define MFREG(a, d)     mfsdr(a, d)
  94 #define MTREG(a, d)     mtsdr(a, d)
  95 #endif /* #if defined(CONFIG_440GP) */
  96 #elif defined(CONFIG_405EP) || defined(CONFIG_405EZ)
  97 #define UART0_BASE      0xef600300
  98 #define UART1_BASE      0xef600400
  99 #define UCR0_MASK       0x0000007f
 100 #define UCR1_MASK       0x00007f00
 101 #define UCR0_UDIV_POS   0
 102 #define UCR1_UDIV_POS   8
 103 #define UDIV_MAX        127
 104 #elif defined(CONFIG_405EX)
 105 #define UART0_BASE      0xef600200
 106 #define UART1_BASE      0xef600300
 107 #define CR0_MASK        0x000000ff
 108 #define CR0_EXTCLK_ENA  0x00800000
 109 #define CR0_UDIV_POS    0
 110 #define UDIV_SUBTRACT   0
 111 #define UART0_SDR       sdr_uart0
 112 #define UART1_SDR       sdr_uart1
 113 #define MFREG(a, d)     mfsdr(a, d)
 114 #define MTREG(a, d)     mtsdr(a, d)
 115 #else /* CONFIG_405GP || CONFIG_405CR */
 116 #define UART0_BASE      0xef600300
 117 #define UART1_BASE      0xef600400
 118 #define CR0_MASK        0x00001fff
 119 #define CR0_EXTCLK_ENA  0x000000c0
 120 #define CR0_UDIV_POS    1
 121 #define UDIV_MAX        32
 122 #endif
 123
 124 #define UART_RBR    0x00
 125 #define UART_THR    0x00
 126 #define UART_IER    0x01
 127 #define UART_IIR    0x02
 128 #define UART_FCR    0x02
 129 #define UART_LCR    0x03
 130 #define UART_MCR    0x04
 131 #define UART_LSR    0x05
 132 #define UART_MSR    0x06
 133 #define UART_SCR    0x07
 134 #define UART_DLL    0x00
 135 #define UART_DLM    0x01
 136
 137 /*
 138  * Line Status Register.
 139  */
 140 #define asyncLSRDataReady1            0x01
 141 #define asyncLSROverrunError1         0x02
 142 #define asyncLSRParityError1          0x04
 143 #define asyncLSRFramingError1         0x08
 144 #define asyncLSRBreakInterrupt1       0x10
 145 #define asyncLSRTxHoldEmpty1          0x20
 146 #define asyncLSRTxShiftEmpty1         0x40
 147 #define asyncLSRRxFifoError1          0x80
 148
 149 DECLARE_GLOBAL_DATA_PTR;
 150
 151 #if defined(CONFIG_440) || defined(CONFIG_405EX)
 152 #if !defined(CFG_EXT_SERIAL_CLOCK)
 153 static void serial_divs (int baudrate, unsigned long *pudiv,
 154                          unsigned short *pbdiv)
 155 {
 156         sys_info_t sysinfo;
 157         unsigned long div;              /* total divisor udiv * bdiv */
 158         unsigned long umin;             /* minimum udiv */
 159         unsigned short diff;            /* smallest diff */
 160         unsigned long udiv;             /* best udiv */
 161         unsigned short idiff;           /* current diff */
 162         unsigned short ibdiv;           /* current bdiv */
 163         unsigned long i;
 164         unsigned long est;              /* current estimate */
 165
 166         get_sys_info(&sysinfo);
 167
 168         udiv = 32;                      /* Assume lowest possible serial clk */
 169         div = sysinfo.freqPLB / (16 * baudrate); /* total divisor */
 170         umin = sysinfo.pllOpbDiv << 1;  /* 2 x OPB divisor */
 171         diff = 32;                      /* highest possible */
 172
 173         /* i is the test udiv value -- start with the largest
 174          * possible (32) to minimize serial clock and constrain
 175          * search to umin.
 176          */
 177         for (i = 32; i > umin; i--) {
 178                 ibdiv = div / i;
 179                 est = i * ibdiv;
 180                 idiff = (est > div) ? (est-div) : (div-est);
 181                 if (idiff == 0) {
 182                         udiv = i;
 183                         break;  /* can't do better */
 184                 } else if (idiff < diff) {
 185                         udiv = i;       /* best so far */
 186                         diff = idiff;   /* update lowest diff*/
 187                 }
 188         }
 189
 190         *pudiv = udiv;
 191         *pbdiv = div / udiv;
 192 }
 193 #endif
 194
 195 static int uart_post_init (unsigned long dev_base)
 196 {
 197         unsigned long reg = 0;
 198         unsigned long udiv;
 199         unsigned short bdiv;
 200         volatile char val;
 201 #ifdef CFG_EXT_SERIAL_CLOCK
 202         unsigned long tmp;
 203 #endif
 204         int i;
 205
 206         for (i = 0; i < 3500; i++) {
 207                 if (in8 (dev_base + UART_LSR) & asyncLSRTxHoldEmpty1)
 208                         break;
 209                 udelay (100);
 210         }
 211         MFREG(UART0_SDR, reg);
 212         reg &= ~CR0_MASK;
 213
 214 #ifdef CFG_EXT_SERIAL_CLOCK
 215         reg |= CR0_EXTCLK_ENA;
 216         udiv = 1;
 217         tmp  = gd->baudrate * 16;
 218         bdiv = (CFG_EXT_SERIAL_CLOCK + tmp / 2) / tmp;
 219 #else
 220         /* For 440, the cpu clock is on divider chain A, UART on divider
 221          * chain B ... so cpu clock is irrelevant. Get the "optimized"
 222          * values that are subject to the 1/2 opb clock constraint
 223          */
 224         serial_divs (gd->baudrate, &udiv, &bdiv);
 225 #endif
 226
 227         reg |= (udiv - UDIV_SUBTRACT) << CR0_UDIV_POS;  /* set the UART divisor */
 228
 229         /*
 230          * Configure input clock to baudrate generator for all
 231          * available serial ports here
 232          */
 233         MTREG(UART0_SDR, reg);
 234 #if defined(UART1_SDR)
 235         MTREG(UART1_SDR, reg);
 236 #endif
 237 #if defined(UART2_SDR)
 238         MTREG(UART2_SDR, reg);
 239 #endif
 240 #if defined(UART3_SDR)
 241         MTREG(UART3_SDR, reg);
 242 #endif
 243
 244         out8(dev_base + UART_LCR, 0x80);        /* set DLAB bit */
 245         out8(dev_base + UART_DLL, bdiv);        /* set baudrate divisor */
 246         out8(dev_base + UART_DLM, bdiv >> 8);   /* set baudrate divisor */
 247         out8(dev_base + UART_LCR, 0x03);        /* clear DLAB; set 8 bits, no parity */
 248         out8(dev_base + UART_FCR, 0x00);        /* disable FIFO */
 249         out8(dev_base + UART_MCR, 0x10);        /* enable loopback mode */
 250         val = in8(dev_base + UART_LSR);         /* clear line status */
 251         val = in8(dev_base + UART_RBR);         /* read receive buffer */
 252         out8(dev_base + UART_SCR, 0x00);        /* set scratchpad */
 253         out8(dev_base + UART_IER, 0x00);        /* set interrupt enable reg */
 254
 255         return 0;
 256 }
 257
 258 #else /* CONFIG_440 */
 259
 260 static int uart_post_init (unsigned long dev_base)
 261 {
 262         unsigned long reg;
 263         unsigned long tmp;
 264         unsigned long clk;
 265         unsigned long udiv;
 266         unsigned short bdiv;
 267         volatile char val;
 268         int i;
 269
 270         for (i = 0; i < 3500; i++) {
 271                 if (in8 (dev_base + UART_LSR) & asyncLSRTxHoldEmpty1)
 272                         break;
 273                 udelay (100);
 274         }
 275
 276 #if defined(CONFIG_405EZ)
 277         serial_divs(gd->baudrate, &udiv, &bdiv);
 278         clk = tmp = reg = 0;
 279 #else
 280 #ifdef CONFIG_405EP
 281         reg = mfdcr(cpc0_ucr) & ~(UCR0_MASK | UCR1_MASK);
 282         clk = gd->cpu_clk;
 283         tmp = CFG_BASE_BAUD * 16;
 284         udiv = (clk + tmp / 2) / tmp;
 285         if (udiv > UDIV_MAX)                    /* max. n bits for udiv */
 286                 udiv = UDIV_MAX;
 287         reg |= (udiv) << UCR0_UDIV_POS;         /* set the UART divisor */
 288         reg |= (udiv) << UCR1_UDIV_POS;         /* set the UART divisor */
 289         mtdcr (cpc0_ucr, reg);
 290 #else /* CONFIG_405EP */
 291         reg = mfdcr(cntrl0) & ~CR0_MASK;
 292 #ifdef CFG_EXT_SERIAL_CLOCK
 293         clk = CFG_EXT_SERIAL_CLOCK;
 294         udiv = 1;
 295         reg |= CR0_EXTCLK_ENA;
 296 #else
 297         clk = gd->cpu_clk;
 298 #ifdef CFG_405_UART_ERRATA_59
 299         udiv = 31;                      /* Errata 59: stuck at 31 */
 300 #else
 301         tmp = CFG_BASE_BAUD * 16;
 302         udiv = (clk + tmp / 2) / tmp;
 303         if (udiv > UDIV_MAX)                    /* max. n bits for udiv */
 304                 udiv = UDIV_MAX;
 305 #endif
 306 #endif
 307         reg |= (udiv - 1) << CR0_UDIV_POS;      /* set the UART divisor */
 308         mtdcr (cntrl0, reg);
 309 #endif /* CONFIG_405EP */
 310         tmp = gd->baudrate * udiv * 16;
 311         bdiv = (clk + tmp / 2) / tmp;
 312 #endif /* CONFIG_405EZ */
 313
 314         out8(dev_base + UART_LCR, 0x80);        /* set DLAB bit */
 315         out8(dev_base + UART_DLL, bdiv);        /* set baudrate divisor */
 316         out8(dev_base + UART_DLM, bdiv >> 8);   /* set baudrate divisor */
 317         out8(dev_base + UART_LCR, 0x03);        /* clear DLAB; set 8 bits, no parity */
 318         out8(dev_base + UART_FCR, 0x00);        /* disable FIFO */
 319         out8(dev_base + UART_MCR, 0x10);        /* enable loopback mode */
 320         val = in8(dev_base + UART_LSR); /* clear line status */
 321         val = in8(dev_base + UART_RBR); /* read receive buffer */
 322         out8(dev_base + UART_SCR, 0x00);        /* set scratchpad */
 323         out8(dev_base + UART_IER, 0x00);        /* set interrupt enable reg */
 324
 325         return (0);
 326 }
 327 #endif /* CONFIG_440 */
 328
 329 static void uart_post_putc (unsigned long dev_base, char c)
 330 {
 331         int i;
 332
 333         out8 (dev_base + UART_THR, c);  /* put character out */
 334
 335         /* Wait for transfer completion */
 336         for (i = 0; i < 3500; i++) {
 337                 if (in8 (dev_base + UART_LSR) & asyncLSRTxHoldEmpty1)
 338                         break;
 339                 udelay (100);
 340         }
 341 }
 342
 343 static int uart_post_getc (unsigned long dev_base)
 344 {
 345         int i;
 346
 347         /* Wait for character available */
 348         for (i = 0; i < 3500; i++) {
 349                 if (in8 (dev_base + UART_LSR) & asyncLSRDataReady1)
 350                         break;
 351                 udelay (100);
 352         }
 353         return 0xff & in8 (dev_base + UART_RBR);
 354 }
 355
 356 static int test_ctlr (unsigned long dev_base, int index)
 357 {
 358         int res = -1;
 359         char test_str[] = "*** UART Test String ***\r\n";
 360         int i;
 361
 362         uart_post_init (dev_base);
 363
 364         for (i = 0; i < sizeof (test_str) - 1; i++) {
 365                 uart_post_putc (dev_base, test_str[i]);
 366                 if (uart_post_getc (dev_base) != test_str[i])
 367                         goto done;
 368         }
 369         res = 0;
 370 done:
 371         if (res)
 372                 post_log ("uart%d test failed\n", index);
 373
 374         return res;
 375 }
 376
 377 int uart_post_test (int flags)
 378 {
 379         int i, res = 0;
 380         static unsigned long base[] = CFG_POST_UART_TABLE;
 381
 382         for (i = 0; i < sizeof (base) / sizeof (base[0]); i++) {
 383                 if (test_ctlr (base[i], i))
 384                         res = -1;
 385         }
 386         serial_reinit_all ();
 387
 388         return res;
 389 }
 390
 391 #endif /* CONFIG_POST & CFG_POST_UART */
 392 #endif /* CONFIG_POST */