post/cpu/ppc4xx/uart.c

   1 /*
   2  * (C) Copyright 2007
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25
  26 /*
  27  * UART test
  28  *
  29  * The controllers are configured to loopback mode and several
  30  * characters are transmitted.
  31  */
  32
  33 #ifdef CONFIG_POST
  34
  35 #include <post.h>
  36
  37 #if CONFIG_POST & CFG_POST_UART
  38
  39 #include <asm/processor.h>
  40 #include <serial.h>
  41
  42 #define UART0_BASE  CFG_PERIPHERAL_BASE + 0x00000300
  43 #define UART1_BASE  CFG_PERIPHERAL_BASE + 0x00000400
  44 #define UART2_BASE  CFG_PERIPHERAL_BASE + 0x00000500
  45 #define UART3_BASE  CFG_PERIPHERAL_BASE + 0x00000600
  46
  47 #define CR0_MASK        0xdfffffff
  48 #define CR0_EXTCLK_ENA  0x00800000
  49 #define CR0_UDIV_POS    0
  50 #define UDIV_SUBTRACT   0
  51 #define UART0_SDR       sdr_uart0
  52 #define UART1_SDR       sdr_uart1
  53 #define UART2_SDR       sdr_uart2
  54 #define UART3_SDR       sdr_uart3
  55 #define MFREG(a, d)     mfsdr(a, d)
  56 #define MTREG(a, d)     mtsdr(a, d)
  57
  58 #define UART_RBR    0x00
  59 #define UART_THR    0x00
  60 #define UART_IER    0x01
  61 #define UART_IIR    0x02
  62 #define UART_FCR    0x02
  63 #define UART_LCR    0x03
  64 #define UART_MCR    0x04
  65 #define UART_LSR    0x05
  66 #define UART_MSR    0x06
  67 #define UART_SCR    0x07
  68 #define UART_DLL    0x00
  69 #define UART_DLM    0x01
  70
  71 /*
  72   Line Status Register.
  73 */
  74 #define asyncLSRDataReady1            0x01
  75 #define asyncLSROverrunError1         0x02
  76 #define asyncLSRParityError1          0x04
  77 #define asyncLSRFramingError1         0x08
  78 #define asyncLSRBreakInterrupt1       0x10
  79 #define asyncLSRTxHoldEmpty1          0x20
  80 #define asyncLSRTxShiftEmpty1         0x40
  81 #define asyncLSRRxFifoError1          0x80
  82
  83 DECLARE_GLOBAL_DATA_PTR;
  84
  85 static int uart_post_init (unsigned long dev_base)
  86 {
  87         unsigned long reg;
  88         unsigned long udiv;
  89         unsigned short bdiv;
  90         volatile char val;
  91 #ifdef CFG_EXT_SERIAL_CLOCK
  92         unsigned long tmp;
  93 #endif
  94         int i;
  95
  96         for (i = 0; i < 3500; i++) {
  97                 if (in8 (dev_base + UART_LSR) & asyncLSRTxHoldEmpty1)
  98                         break;
  99                 udelay (100);
 100         }
 101         MFREG(UART0_SDR, reg);
 102         reg &= ~CR0_MASK;
 103
 104 #ifdef CFG_EXT_SERIAL_CLOCK
 105         reg |= CR0_EXTCLK_ENA;
 106         udiv = 1;
 107         tmp  = gd->baudrate * 16;
 108         bdiv = (CFG_EXT_SERIAL_CLOCK + tmp / 2) / tmp;
 109 #else
 110         /* For 440, the cpu clock is on divider chain A, UART on divider
 111          * chain B ... so cpu clock is irrelevant. Get the "optimized"
 112          * values that are subject to the 1/2 opb clock constraint
 113          */
 114         serial_divs (gd->baudrate, &udiv, &bdiv);
 115 #endif
 116
 117         reg |= (udiv - UDIV_SUBTRACT) << CR0_UDIV_POS;  /* set the UART divisor */
 118
 119         /*
 120          * Configure input clock to baudrate generator for all
 121          * available serial ports here
 122          */
 123         MTREG(UART0_SDR, reg);
 124 #if defined(UART1_SDR)
 125         MTREG(UART1_SDR, reg);
 126 #endif
 127 #if defined(UART2_SDR)
 128         MTREG(UART2_SDR, reg);
 129 #endif
 130 #if defined(UART3_SDR)
 131         MTREG(UART3_SDR, reg);
 132 #endif
 133
 134         out8(dev_base + UART_LCR, 0x80);        /* set DLAB bit */
 135         out8(dev_base + UART_DLL, bdiv);        /* set baudrate divisor */
 136         out8(dev_base + UART_DLM, bdiv >> 8);   /* set baudrate divisor */
 137         out8(dev_base + UART_LCR, 0x03);        /* clear DLAB; set 8 bits, no parity */
 138         out8(dev_base + UART_FCR, 0x00);        /* disable FIFO */
 139         out8(dev_base + UART_MCR, 0x10);        /* enable loopback mode */
 140         val = in8(dev_base + UART_LSR);         /* clear line status */
 141         val = in8(dev_base + UART_RBR);         /* read receive buffer */
 142         out8(dev_base + UART_SCR, 0x00);        /* set scratchpad */
 143         out8(dev_base + UART_IER, 0x00);        /* set interrupt enable reg */
 144
 145         return 0;
 146 }
 147
 148 static void uart_post_putc (unsigned long dev_base, char c)
 149 {
 150         int i;
 151
 152         out8 (dev_base + UART_THR, c);  /* put character out */
 153
 154         /* Wait for transfer completion */
 155         for (i = 0; i < 3500; i++) {
 156                 if (in8 (dev_base + UART_LSR) & asyncLSRTxHoldEmpty1)
 157                         break;
 158                 udelay (100);
 159         }
 160 }
 161
 162 static int uart_post_getc (unsigned long dev_base)
 163 {
 164         int i;
 165
 166         /* Wait for character available */
 167         for (i = 0; i < 3500; i++) {
 168                 if (in8 (dev_base + UART_LSR) & asyncLSRDataReady1)
 169                         break;
 170                 udelay (100);
 171         }
 172         return 0xff & in8 (dev_base + UART_RBR);
 173 }
 174
 175 static int test_ctlr (unsigned long dev_base, int index)
 176 {
 177         int res = -1;
 178         char test_str[] = "*** UART Test String ***\r\n";
 179         int i;
 180
 181         uart_post_init (dev_base);
 182
 183         for (i = 0; i < sizeof (test_str) - 1; i++) {
 184                 uart_post_putc (dev_base, test_str[i]);
 185                 if (uart_post_getc (dev_base) != test_str[i])
 186                         goto done;
 187         }
 188         res = 0;
 189 done:
 190         if (res)
 191                 post_log ("uart%d test failed\n", index);
 192
 193         return res;
 194 }
 195
 196 int uart_post_test (int flags)
 197 {
 198         int i, res = 0;
 199         static unsigned long base[] = {
 200                 UART0_BASE, UART1_BASE, UART2_BASE, UART3_BASE
 201         };
 202
 203         for (i = 0; i < sizeof (base) / sizeof (base[0]); i++) {
 204                 if (test_ctlr (base[i], i))
 205                         res = -1;
 206         }
 207         serial_reinit_all ();
 208
 209         return res;
 210 }
 211
 212 #endif /* CONFIG_POST & CFG_POST_UART */
 213
 214 #endif /* CONFIG_POST */