post/cpu/ppc4xx/uart.c

   1 /*
   2  * (C) Copyright 2007
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * Author: Igor Lisitsin <igor@emcraft.com>
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 #include <common.h>
  27
  28 /*
  29  * UART test
  30  *
  31  * The controllers are configured to loopback mode and several
  32  * characters are transmitted.
  33  */
  34
  35 #ifdef CONFIG_POST
  36
  37 #include <post.h>
  38
  39 #if CONFIG_POST & CFG_POST_UART
  40
  41 /*
  42  * This table defines the UART's that should be tested and can
  43  * be overridden in the board config file
  44  */
  45 #ifndef CFG_POST_UART_TABLE
  46 #define CFG_POST_UART_TABLE     {UART0_BASE, UART1_BASE, UART2_BASE, UART3_BASE}
  47 #endif
  48
  49 #include <asm/processor.h>
  50 #include <serial.h>
  51
  52 #if defined(CONFIG_440)
  53 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
  54     defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
  55 #define UART0_BASE  CFG_PERIPHERAL_BASE + 0x00000300
  56 #define UART1_BASE  CFG_PERIPHERAL_BASE + 0x00000400
  57 #define UART2_BASE  CFG_PERIPHERAL_BASE + 0x00000500
  58 #define UART3_BASE  CFG_PERIPHERAL_BASE + 0x00000600
  59 #else
  60 #define UART0_BASE  CFG_PERIPHERAL_BASE + 0x00000200
  61 #define UART1_BASE  CFG_PERIPHERAL_BASE + 0x00000300
  62 #endif
  63
  64 #if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
  65 #define UART2_BASE  CFG_PERIPHERAL_BASE + 0x00000600
  66 #endif
  67
  68 #if defined(CONFIG_440GP)
  69 #define CR0_MASK        0x3fff0000
  70 #define CR0_EXTCLK_ENA  0x00600000
  71 #define CR0_UDIV_POS    16
  72 #define UDIV_SUBTRACT   1
  73 #define UART0_SDR       cntrl0
  74 #define MFREG(a, d)     d = mfdcr(a)
  75 #define MTREG(a, d)     mtdcr(a, d)
  76 #else /* #if defined(CONFIG_440GP) */
  77 /* all other 440 PPC's access clock divider via sdr register */
  78 #define CR0_MASK        0xdfffffff
  79 #define CR0_EXTCLK_ENA  0x00800000
  80 #define CR0_UDIV_POS    0
  81 #define UDIV_SUBTRACT   0
  82 #define UART0_SDR       sdr_uart0
  83 #define UART1_SDR       sdr_uart1
  84 #if defined(CONFIG_440EP) || defined(CONFIG_440EPx) || \
  85     defined(CONFIG_440GR) || defined(CONFIG_440GRx) || \
  86     defined(CONFIG_440SP) || defined(CONFIG_440SPe)
  87 #define UART2_SDR       sdr_uart2
  88 #endif
  89 #if defined(CONFIG_440EP) || defined(CONFIG_440EPx) || \
  90     defined(CONFIG_440GR) || defined(CONFIG_440GRx)
  91 #define UART3_SDR       sdr_uart3
  92 #endif
  93 #define MFREG(a, d)     mfsdr(a, d)
  94 #define MTREG(a, d)     mtsdr(a, d)
  95 #endif /* #if defined(CONFIG_440GP) */
  96 #elif defined(CONFIG_405EP) || defined(CONFIG_405EZ)
  97 #define UART0_BASE      0xef600300
  98 #define UART1_BASE      0xef600400
  99 #define UCR0_MASK       0x0000007f
 100 #define UCR1_MASK       0x00007f00
 101 #define UCR0_UDIV_POS   0
 102 #define UCR1_UDIV_POS   8
 103 #define UDIV_MAX        127
 104 #else /* CONFIG_405GP || CONFIG_405CR */
 105 #define UART0_BASE      0xef600300
 106 #define UART1_BASE      0xef600400
 107 #define CR0_MASK        0x00001fff
 108 #define CR0_EXTCLK_ENA  0x000000c0
 109 #define CR0_UDIV_POS    1
 110 #define UDIV_MAX        32
 111 #endif
 112
 113 #define UART_RBR    0x00
 114 #define UART_THR    0x00
 115 #define UART_IER    0x01
 116 #define UART_IIR    0x02
 117 #define UART_FCR    0x02
 118 #define UART_LCR    0x03
 119 #define UART_MCR    0x04
 120 #define UART_LSR    0x05
 121 #define UART_MSR    0x06
 122 #define UART_SCR    0x07
 123 #define UART_DLL    0x00
 124 #define UART_DLM    0x01
 125
 126 /*
 127  * Line Status Register.
 128  */
 129 #define asyncLSRDataReady1            0x01
 130 #define asyncLSROverrunError1         0x02
 131 #define asyncLSRParityError1          0x04
 132 #define asyncLSRFramingError1         0x08
 133 #define asyncLSRBreakInterrupt1       0x10
 134 #define asyncLSRTxHoldEmpty1          0x20
 135 #define asyncLSRTxShiftEmpty1         0x40
 136 #define asyncLSRRxFifoError1          0x80
 137
 138 DECLARE_GLOBAL_DATA_PTR;
 139
 140 #if defined(CONFIG_440)
 141 #if !defined(CFG_EXT_SERIAL_CLOCK)
 142 static void serial_divs (int baudrate, unsigned long *pudiv,
 143                          unsigned short *pbdiv)
 144 {
 145         sys_info_t sysinfo;
 146         unsigned long div;              /* total divisor udiv * bdiv */
 147         unsigned long umin;             /* minimum udiv */
 148         unsigned short diff;            /* smallest diff */
 149         unsigned long udiv;             /* best udiv */
 150         unsigned short idiff;           /* current diff */
 151         unsigned short ibdiv;           /* current bdiv */
 152         unsigned long i;
 153         unsigned long est;              /* current estimate */
 154
 155         get_sys_info(&sysinfo);
 156
 157         udiv = 32;                      /* Assume lowest possible serial clk */
 158         div = sysinfo.freqPLB / (16 * baudrate); /* total divisor */
 159         umin = sysinfo.pllOpbDiv << 1;  /* 2 x OPB divisor */
 160         diff = 32;                      /* highest possible */
 161
 162         /* i is the test udiv value -- start with the largest
 163          * possible (32) to minimize serial clock and constrain
 164          * search to umin.
 165          */
 166         for (i = 32; i > umin; i--) {
 167                 ibdiv = div / i;
 168                 est = i * ibdiv;
 169                 idiff = (est > div) ? (est-div) : (div-est);
 170                 if (idiff == 0) {
 171                         udiv = i;
 172                         break;  /* can't do better */
 173                 } else if (idiff < diff) {
 174                         udiv = i;       /* best so far */
 175                         diff = idiff;   /* update lowest diff*/
 176                 }
 177         }
 178
 179         *pudiv = udiv;
 180         *pbdiv = div / udiv;
 181 }
 182 #endif
 183
 184 static int uart_post_init (unsigned long dev_base)
 185 {
 186         unsigned long reg;
 187         unsigned long udiv;
 188         unsigned short bdiv;
 189         volatile char val;
 190 #ifdef CFG_EXT_SERIAL_CLOCK
 191         unsigned long tmp;
 192 #endif
 193         int i;
 194
 195         for (i = 0; i < 3500; i++) {
 196                 if (in8 (dev_base + UART_LSR) & asyncLSRTxHoldEmpty1)
 197                         break;
 198                 udelay (100);
 199         }
 200         MFREG(UART0_SDR, reg);
 201         reg &= ~CR0_MASK;
 202
 203 #ifdef CFG_EXT_SERIAL_CLOCK
 204         reg |= CR0_EXTCLK_ENA;
 205         udiv = 1;
 206         tmp  = gd->baudrate * 16;
 207         bdiv = (CFG_EXT_SERIAL_CLOCK + tmp / 2) / tmp;
 208 #else
 209         /* For 440, the cpu clock is on divider chain A, UART on divider
 210          * chain B ... so cpu clock is irrelevant. Get the "optimized"
 211          * values that are subject to the 1/2 opb clock constraint
 212          */
 213         serial_divs (gd->baudrate, &udiv, &bdiv);
 214 #endif
 215
 216         reg |= (udiv - UDIV_SUBTRACT) << CR0_UDIV_POS;  /* set the UART divisor */
 217
 218         /*
 219          * Configure input clock to baudrate generator for all
 220          * available serial ports here
 221          */
 222         MTREG(UART0_SDR, reg);
 223 #if defined(UART1_SDR)
 224         MTREG(UART1_SDR, reg);
 225 #endif
 226 #if defined(UART2_SDR)
 227         MTREG(UART2_SDR, reg);
 228 #endif
 229 #if defined(UART3_SDR)
 230         MTREG(UART3_SDR, reg);
 231 #endif
 232
 233         out8(dev_base + UART_LCR, 0x80);        /* set DLAB bit */
 234         out8(dev_base + UART_DLL, bdiv);        /* set baudrate divisor */
 235         out8(dev_base + UART_DLM, bdiv >> 8);   /* set baudrate divisor */
 236         out8(dev_base + UART_LCR, 0x03);        /* clear DLAB; set 8 bits, no parity */
 237         out8(dev_base + UART_FCR, 0x00);        /* disable FIFO */
 238         out8(dev_base + UART_MCR, 0x10);        /* enable loopback mode */
 239         val = in8(dev_base + UART_LSR);         /* clear line status */
 240         val = in8(dev_base + UART_RBR);         /* read receive buffer */
 241         out8(dev_base + UART_SCR, 0x00);        /* set scratchpad */
 242         out8(dev_base + UART_IER, 0x00);        /* set interrupt enable reg */
 243
 244         return 0;
 245 }
 246
 247 #else /* CONFIG_440 */
 248
 249 static int uart_post_init (unsigned long dev_base)
 250 {
 251         unsigned long reg;
 252         unsigned long tmp;
 253         unsigned long clk;
 254         unsigned long udiv;
 255         unsigned short bdiv;
 256         volatile char val;
 257         int i;
 258
 259         for (i = 0; i < 3500; i++) {
 260                 if (in8 (dev_base + UART_LSR) & asyncLSRTxHoldEmpty1)
 261                         break;
 262                 udelay (100);
 263         }
 264
 265 #if defined(CONFIG_405EZ)
 266         serial_divs(gd->baudrate, &udiv, &bdiv);
 267         clk = tmp = reg = 0;
 268 #else
 269 #ifdef CONFIG_405EP
 270         reg = mfdcr(cpc0_ucr) & ~(UCR0_MASK | UCR1_MASK);
 271         clk = gd->cpu_clk;
 272         tmp = CFG_BASE_BAUD * 16;
 273         udiv = (clk + tmp / 2) / tmp;
 274         if (udiv > UDIV_MAX)                    /* max. n bits for udiv */
 275                 udiv = UDIV_MAX;
 276         reg |= (udiv) << UCR0_UDIV_POS;         /* set the UART divisor */
 277         reg |= (udiv) << UCR1_UDIV_POS;         /* set the UART divisor */
 278         mtdcr (cpc0_ucr, reg);
 279 #else /* CONFIG_405EP */
 280         reg = mfdcr(cntrl0) & ~CR0_MASK;
 281 #ifdef CFG_EXT_SERIAL_CLOCK
 282         clk = CFG_EXT_SERIAL_CLOCK;
 283         udiv = 1;
 284         reg |= CR0_EXTCLK_ENA;
 285 #else
 286         clk = gd->cpu_clk;
 287 #ifdef CFG_405_UART_ERRATA_59
 288         udiv = 31;                      /* Errata 59: stuck at 31 */
 289 #else
 290         tmp = CFG_BASE_BAUD * 16;
 291         udiv = (clk + tmp / 2) / tmp;
 292         if (udiv > UDIV_MAX)                    /* max. n bits for udiv */
 293                 udiv = UDIV_MAX;
 294 #endif
 295 #endif
 296         reg |= (udiv - 1) << CR0_UDIV_POS;      /* set the UART divisor */
 297         mtdcr (cntrl0, reg);
 298 #endif /* CONFIG_405EP */
 299         tmp = gd->baudrate * udiv * 16;
 300         bdiv = (clk + tmp / 2) / tmp;
 301 #endif /* CONFIG_405EZ */
 302
 303         out8(dev_base + UART_LCR, 0x80);        /* set DLAB bit */
 304         out8(dev_base + UART_DLL, bdiv);        /* set baudrate divisor */
 305         out8(dev_base + UART_DLM, bdiv >> 8);   /* set baudrate divisor */
 306         out8(dev_base + UART_LCR, 0x03);        /* clear DLAB; set 8 bits, no parity */
 307         out8(dev_base + UART_FCR, 0x00);        /* disable FIFO */
 308         out8(dev_base + UART_MCR, 0x10);        /* enable loopback mode */
 309         val = in8(dev_base + UART_LSR); /* clear line status */
 310         val = in8(dev_base + UART_RBR); /* read receive buffer */
 311         out8(dev_base + UART_SCR, 0x00);        /* set scratchpad */
 312         out8(dev_base + UART_IER, 0x00);        /* set interrupt enable reg */
 313
 314         return (0);
 315 }
 316 #endif /* CONFIG_440 */
 317
 318 static void uart_post_putc (unsigned long dev_base, char c)
 319 {
 320         int i;
 321
 322         out8 (dev_base + UART_THR, c);  /* put character out */
 323
 324         /* Wait for transfer completion */
 325         for (i = 0; i < 3500; i++) {
 326                 if (in8 (dev_base + UART_LSR) & asyncLSRTxHoldEmpty1)
 327                         break;
 328                 udelay (100);
 329         }
 330 }
 331
 332 static int uart_post_getc (unsigned long dev_base)
 333 {
 334         int i;
 335
 336         /* Wait for character available */
 337         for (i = 0; i < 3500; i++) {
 338                 if (in8 (dev_base + UART_LSR) & asyncLSRDataReady1)
 339                         break;
 340                 udelay (100);
 341         }
 342         return 0xff & in8 (dev_base + UART_RBR);
 343 }
 344
 345 static int test_ctlr (unsigned long dev_base, int index)
 346 {
 347         int res = -1;
 348         char test_str[] = "*** UART Test String ***\r\n";
 349         int i;
 350
 351         uart_post_init (dev_base);
 352
 353         for (i = 0; i < sizeof (test_str) - 1; i++) {
 354                 uart_post_putc (dev_base, test_str[i]);
 355                 if (uart_post_getc (dev_base) != test_str[i])
 356                         goto done;
 357         }
 358         res = 0;
 359 done:
 360         if (res)
 361                 post_log ("uart%d test failed\n", index);
 362
 363         return res;
 364 }
 365
 366 int uart_post_test (int flags)
 367 {
 368         int i, res = 0;
 369         static unsigned long base[] = CFG_POST_UART_TABLE;
 370
 371         for (i = 0; i < sizeof (base) / sizeof (base[0]); i++) {
 372                 if (test_ctlr (base[i], i))
 373                         res = -1;
 374         }
 375         serial_reinit_all ();
 376
 377         return res;
 378 }
 379
 380 #endif /* CONFIG_POST & CFG_POST_UART */
 381 #endif /* CONFIG_POST */