post/lib_powerpc/rlwimi.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2002
   4  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   5  */
   6
   7 #include <common.h>
   8
   9 /*
  10  * CPU test
  11  * Shift instructions:          rlwimi
  12  *
  13  * The test contains a pre-built table of instructions, operands and
  14  * expected results. For each table entry, the test will cyclically use
  15  * different sets of operand registers and result registers.
  16  */
  17
  18 #include <post.h>
  19 #include "cpu_asm.h"
  20
  21 #if CONFIG_POST & CONFIG_SYS_POST_CPU
  22
  23 extern void cpu_post_exec_22 (ulong *code, ulong *cr, ulong *res, ulong op1,
  24     ulong op2);
  25 extern ulong cpu_post_makecr (long v);
  26
  27 static struct cpu_post_rlwimi_s
  28 {
  29     ulong cmd;
  30     ulong op0;
  31     ulong op1;
  32     uchar op2;
  33     uchar mb;
  34     uchar me;
  35     ulong res;
  36 } cpu_post_rlwimi_table[] =
  37 {
  38     {
  39         OP_RLWIMI,
  40         0xff00ffff,
  41         0x0000aa00,
  42         8,
  43         8,
  44         15,
  45         0xffaaffff
  46     },
  47 };
  48 static unsigned int cpu_post_rlwimi_size = ARRAY_SIZE(cpu_post_rlwimi_table);
  49
  50 int cpu_post_test_rlwimi (void)
  51 {
  52     int ret = 0;
  53     unsigned int i, reg;
  54     int flag = disable_interrupts();
  55
  56     for (i = 0; i < cpu_post_rlwimi_size && ret == 0; i++)
  57     {
  58         struct cpu_post_rlwimi_s *test = cpu_post_rlwimi_table + i;
  59
  60         for (reg = 0; reg < 32 && ret == 0; reg++)
  61         {
  62             unsigned int reg0 = (reg + 0) % 32;
  63             unsigned int reg1 = (reg + 1) % 32;
  64             unsigned int stk = reg < 16 ? 31 : 15;
  65             unsigned long code[] =
  66             {
  67                 ASM_STW(stk, 1, -4),
  68                 ASM_ADDI(stk, 1, -20),
  69                 ASM_STW(3, stk, 8),
  70                 ASM_STW(4, stk, 12),
  71                 ASM_STW(reg0, stk, 4),
  72                 ASM_STW(reg1, stk, 0),
  73                 ASM_LWZ(reg1, stk, 8),
  74                 ASM_LWZ(reg0, stk, 12),
  75                 ASM_113(test->cmd, reg1, reg0, test->op2, test->mb, test->me),
  76                 ASM_STW(reg1, stk, 8),
  77                 ASM_LWZ(reg1, stk, 0),
  78                 ASM_LWZ(reg0, stk, 4),
  79                 ASM_LWZ(3, stk, 8),
  80                 ASM_ADDI(1, stk, 20),
  81                 ASM_LWZ(stk, 1, -4),
  82                 ASM_BLR,
  83             };
  84             unsigned long codecr[] =
  85             {
  86                 ASM_STW(stk, 1, -4),
  87                 ASM_ADDI(stk, 1, -20),
  88                 ASM_STW(3, stk, 8),
  89                 ASM_STW(4, stk, 12),
  90                 ASM_STW(reg0, stk, 4),
  91                 ASM_STW(reg1, stk, 0),
  92                 ASM_LWZ(reg1, stk, 8),
  93                 ASM_LWZ(reg0, stk, 12),
  94                 ASM_113(test->cmd, reg1, reg0, test->op2, test->mb, test->me) |
  95                     BIT_C,
  96                 ASM_STW(reg1, stk, 8),
  97                 ASM_LWZ(reg1, stk, 0),
  98                 ASM_LWZ(reg0, stk, 4),
  99                 ASM_LWZ(3, stk, 8),
 100                 ASM_ADDI(1, stk, 20),
 101                 ASM_LWZ(stk, 1, -4),
 102                 ASM_BLR,
 103             };
 104             ulong res;
 105             ulong cr;
 106
 107             if (ret == 0)
 108             {
 109                 cr = 0;
 110                 cpu_post_exec_22 (code, & cr, & res, test->op0, test->op1);
 111
 112                 ret = res == test->res && cr == 0 ? 0 : -1;
 113
 114                 if (ret != 0)
 115                 {
 116                     post_log ("Error at rlwimi test %d !\n", i);
 117                 }
 118             }
 119
 120             if (ret == 0)
 121             {
 122                 cpu_post_exec_22 (codecr, & cr, & res, test->op0, test->op1);
 123
 124                 ret = res == test->res &&
 125                       (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1;
 126
 127                 if (ret != 0)
 128                 {
 129                     post_log ("Error at rlwimi test %d !\n", i);
 130                 }
 131             }
 132         }
 133     }
 134
 135     if (flag)
 136         enable_interrupts();
 137
 138     return ret;
 139 }
 140
 141 #endif