post/lib_powerpc/rlwinm.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2002
   4  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   5  */
   6
   7 #include <common.h>
   8
   9 /*
  10  * CPU test
  11  * Shift instructions:          rlwinm
  12  *
  13  * The test contains a pre-built table of instructions, operands and
  14  * expected results. For each table entry, the test will cyclically use
  15  * different sets of operand registers and result registers.
  16  */
  17
  18 #include <post.h>
  19 #include "cpu_asm.h"
  20
  21 #if CONFIG_POST & CONFIG_SYS_POST_CPU
  22
  23 extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op1);
  24 extern ulong cpu_post_makecr (long v);
  25
  26 static struct cpu_post_rlwinm_s
  27 {
  28     ulong cmd;
  29     ulong op1;
  30     uchar op2;
  31     uchar mb;
  32     uchar me;
  33     ulong res;
  34 } cpu_post_rlwinm_table[] =
  35 {
  36    {
  37         OP_RLWINM,
  38         0xffff0000,
  39         24,
  40         16,
  41         23,
  42         0x0000ff00
  43    },
  44 };
  45 static unsigned int cpu_post_rlwinm_size = ARRAY_SIZE(cpu_post_rlwinm_table);
  46
  47 int cpu_post_test_rlwinm (void)
  48 {
  49     int ret = 0;
  50     unsigned int i, reg;
  51     int flag = disable_interrupts();
  52
  53     for (i = 0; i < cpu_post_rlwinm_size && ret == 0; i++)
  54     {
  55         struct cpu_post_rlwinm_s *test = cpu_post_rlwinm_table + i;
  56
  57         for (reg = 0; reg < 32 && ret == 0; reg++)
  58         {
  59             unsigned int reg0 = (reg + 0) % 32;
  60             unsigned int reg1 = (reg + 1) % 32;
  61             unsigned int stk = reg < 16 ? 31 : 15;
  62             unsigned long code[] =
  63             {
  64                 ASM_STW(stk, 1, -4),
  65                 ASM_ADDI(stk, 1, -16),
  66                 ASM_STW(3, stk, 8),
  67                 ASM_STW(reg0, stk, 4),
  68                 ASM_STW(reg1, stk, 0),
  69                 ASM_LWZ(reg0, stk, 8),
  70                 ASM_113(test->cmd, reg1, reg0, test->op2, test->mb, test->me),
  71                 ASM_STW(reg1, stk, 8),
  72                 ASM_LWZ(reg1, stk, 0),
  73                 ASM_LWZ(reg0, stk, 4),
  74                 ASM_LWZ(3, stk, 8),
  75                 ASM_ADDI(1, stk, 16),
  76                 ASM_LWZ(stk, 1, -4),
  77                 ASM_BLR,
  78             };
  79             unsigned long codecr[] =
  80             {
  81                 ASM_STW(stk, 1, -4),
  82                 ASM_ADDI(stk, 1, -16),
  83                 ASM_STW(3, stk, 8),
  84                 ASM_STW(reg0, stk, 4),
  85                 ASM_STW(reg1, stk, 0),
  86                 ASM_LWZ(reg0, stk, 8),
  87                 ASM_113(test->cmd, reg1, reg0, test->op2, test->mb,
  88                     test->me) | BIT_C,
  89                 ASM_STW(reg1, stk, 8),
  90                 ASM_LWZ(reg1, stk, 0),
  91                 ASM_LWZ(reg0, stk, 4),
  92                 ASM_LWZ(3, stk, 8),
  93                 ASM_ADDI(1, stk, 16),
  94                 ASM_LWZ(stk, 1, -4),
  95                 ASM_BLR,
  96             };
  97             ulong res;
  98             ulong cr;
  99
 100             if (ret == 0)
 101             {
 102                 cr = 0;
 103                 cpu_post_exec_21 (code, & cr, & res, test->op1);
 104
 105                 ret = res == test->res && cr == 0 ? 0 : -1;
 106
 107                 if (ret != 0)
 108                 {
 109                     post_log ("Error at rlwinm test %d !\n", i);
 110                 }
 111             }
 112
 113             if (ret == 0)
 114             {
 115                 cpu_post_exec_21 (codecr, & cr, & res, test->op1);
 116
 117                 ret = res == test->res &&
 118                       (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1;
 119
 120                 if (ret != 0)
 121                 {
 122                     post_log ("Error at rlwinm test %d !\n", i);
 123                 }
 124             }
 125         }
 126     }
 127
 128     if (flag)
 129         enable_interrupts();
 130
 131     return ret;
 132 }
 133
 134 #endif