post/lib_ppc/andi.c

   1 /*
   2  * (C) Copyright 2002
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25
  26 /*
  27  * CPU test
  28  * Logic instructions:          andi., andis.
  29  *
  30  * The test contains a pre-built table of instructions, operands and
  31  * expected results. For each table entry, the test will cyclically use
  32  * different sets of operand registers and result registers.
  33  */
  34
  35 #ifdef CONFIG_POST
  36
  37 #include <post.h>
  38 #include "cpu_asm.h"
  39
  40 #if CONFIG_POST & CFG_POST_CPU
  41
  42 extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op);
  43 extern ulong cpu_post_makecr (long v);
  44
  45 static struct cpu_post_andi_s
  46 {
  47     ulong cmd;
  48     ulong op1;
  49     ushort op2;
  50     ulong res;
  51 } cpu_post_andi_table[] =
  52 {
  53     {
  54         OP_ANDI_,
  55         0x80008000,
  56         0xffff,
  57         0x00008000
  58     },
  59     {
  60         OP_ANDIS_,
  61         0x80008000,
  62         0xffff,
  63         0x80000000
  64     },
  65 };
  66 static unsigned int cpu_post_andi_size =
  67     sizeof (cpu_post_andi_table) / sizeof (struct cpu_post_andi_s);
  68
  69 int cpu_post_test_andi (void)
  70 {
  71     int ret = 0;
  72     unsigned int i, reg;
  73     int flag = disable_interrupts();
  74
  75     for (i = 0; i < cpu_post_andi_size && ret == 0; i++)
  76     {
  77         struct cpu_post_andi_s *test = cpu_post_andi_table + i;
  78
  79         for (reg = 0; reg < 32 && ret == 0; reg++)
  80         {
  81             unsigned int reg0 = (reg + 0) % 32;
  82             unsigned int reg1 = (reg + 1) % 32;
  83             unsigned int stk = reg < 16 ? 31 : 15;
  84             unsigned long codecr[] =
  85             {
  86                 ASM_STW(stk, 1, -4),
  87                 ASM_ADDI(stk, 1, -16),
  88                 ASM_STW(3, stk, 8),
  89                 ASM_STW(reg0, stk, 4),
  90                 ASM_STW(reg1, stk, 0),
  91                 ASM_LWZ(reg0, stk, 8),
  92                 ASM_11IX(test->cmd, reg1, reg0, test->op2),
  93                 ASM_STW(reg1, stk, 8),
  94                 ASM_LWZ(reg1, stk, 0),
  95                 ASM_LWZ(reg0, stk, 4),
  96                 ASM_LWZ(3, stk, 8),
  97                 ASM_ADDI(1, stk, 16),
  98                 ASM_LWZ(stk, 1, -4),
  99                 ASM_BLR,
 100             };
 101             ulong res;
 102             ulong cr;
 103
 104             cpu_post_exec_21 (codecr, & cr, & res, test->op1);
 105
 106             ret = res == test->res &&
 107                   (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1;
 108
 109             if (ret != 0)
 110             {
 111                 post_log ("Error at andi test %d !\n", i);
 112             }
 113         }
 114     }
 115
 116     if (flag)
 117         enable_interrupts();
 118
 119     return ret;
 120 }
 121
 122 #endif
 123 #endif