queue-4.14/drm-arm-hdlcd-allow-a-bit-of-clock-tolerance.patch

   1 From c2f907a5c0c54919d984eca5c19784a44a623571 Mon Sep 17 00:00:00 2001
   2 From: Robin Murphy <robin.murphy@arm.com>
   3 Date: Fri, 17 May 2019 17:37:22 +0100
   4 Subject: drm/arm/hdlcd: Allow a bit of clock tolerance
   5
   6 [ Upstream commit 1c810739097fdeb31b393b67a0a1e3d7ffdd9f63 ]
   7
   8 On the Arm Juno platform, the HDLCD pixel clock is constrained to 250KHz
   9 resolution in order to avoid the tiny System Control Processor spending
  10 aeons trying to calculate exact PLL coefficients. This means that modes
  11 like my oddball 1600x1200 with 130.89MHz clock get rejected since the
  12 rate cannot be matched exactly. In practice, though, this mode works
  13 quite happily with the clock at 131MHz, so let's relax the check to
  14 allow a little bit of slop.
  15
  16 Signed-off-by: Robin Murphy <robin.murphy@arm.com>
  17 Signed-off-by: Liviu Dudau <liviu.dudau@arm.com>
  18 Signed-off-by: Sasha Levin <sashal@kernel.org>
  19 ---
  20  drivers/gpu/drm/arm/hdlcd_crtc.c | 3 ++-
  21  1 file changed, 2 insertions(+), 1 deletion(-)
  22
  23 diff --git a/drivers/gpu/drm/arm/hdlcd_crtc.c b/drivers/gpu/drm/arm/hdlcd_crtc.c
  24 index 4a108660cc8f..6f03700a94be 100644
  25 --- a/drivers/gpu/drm/arm/hdlcd_crtc.c
  26 +++ b/drivers/gpu/drm/arm/hdlcd_crtc.c
  27 @@ -193,7 +193,8 @@ static enum drm_mode_status hdlcd_crtc_mode_valid(struct drm_crtc *crtc,
  28         long rate, clk_rate = mode->clock * 1000;
  29
  30         rate = clk_round_rate(hdlcd->clk, clk_rate);
  31 -       if (rate != clk_rate) {
  32 +       /* 0.1% seems a close enough tolerance for the TDA19988 on Juno */
  33 +       if (abs(rate - clk_rate) * 1000 > clk_rate) {
  34                 /* clock required by mode not supported by hardware */
  35                 return MODE_NOCLOCK;
  36         }
  37 --
  38 2.20.1
  39