queue-4.14/gpu-ipu-v3-fix-i.mx51-csi-control-registers-offset.patch

   1 From 74bfe808e60d0a6546b80a5acf56c107d3a71379 Mon Sep 17 00:00:00 2001
   2 From: Alexander Shiyan <shc_work@mail.ru>
   3 Date: Thu, 20 Dec 2018 11:06:38 +0300
   4 Subject: gpu: ipu-v3: Fix i.MX51 CSI control registers offset
   5
   6 [ Upstream commit 2c0408dd0d8906b26fe8023889af7adf5e68b2c2 ]
   7
   8 The CSI0/CSI1 registers offset is at +0xe030000/+0xe038000 relative
   9 to the control module registers on IPUv3EX.
  10 This patch fixes wrong values for i.MX51 CSI0/CSI1.
  11
  12 Fixes: 2ffd48f2e7 ("gpu: ipu-v3: Add Camera Sensor Interface unit")
  13
  14 Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
  15 Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
  16 Signed-off-by: Sasha Levin <sashal@kernel.org>
  17 ---
  18  drivers/gpu/ipu-v3/ipu-common.c | 4 ++--
  19  1 file changed, 2 insertions(+), 2 deletions(-)
  20
  21 diff --git a/drivers/gpu/ipu-v3/ipu-common.c b/drivers/gpu/ipu-v3/ipu-common.c
  22 index 2c8411b8d050..5f8b31f879ca 100644
  23 --- a/drivers/gpu/ipu-v3/ipu-common.c
  24 +++ b/drivers/gpu/ipu-v3/ipu-common.c
  25 @@ -894,8 +894,8 @@ static struct ipu_devtype ipu_type_imx51 = {
  26         .cpmem_ofs = 0x1f000000,
  27         .srm_ofs = 0x1f040000,
  28         .tpm_ofs = 0x1f060000,
  29 -       .csi0_ofs = 0x1f030000,
  30 -       .csi1_ofs = 0x1f038000,
  31 +       .csi0_ofs = 0x1e030000,
  32 +       .csi1_ofs = 0x1e038000,
  33         .ic_ofs = 0x1e020000,
  34         .disp0_ofs = 0x1e040000,
  35         .disp1_ofs = 0x1e048000,
  36 --
  37 2.19.1
  38