queue-4.14/i2c-cadence-fix-the-hold-bit-setting.patch

   1 From 37c1a9f2b599b18d1a0569c9d7caafffeca43436 Mon Sep 17 00:00:00 2001
   2 From: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
   3 Date: Tue, 5 Feb 2019 16:42:53 +0530
   4 Subject: i2c: cadence: Fix the hold bit setting
   5
   6 [ Upstream commit d358def706880defa4c9e87381c5bf086a97d5f9 ]
   7
   8 In case the hold bit is not needed we are carrying the old values.
   9 Fix the same by resetting the bit when not needed.
  10
  11 Fixes the sporadic i2c bus lockups on National Instruments
  12 Zynq-based devices.
  13
  14 Fixes: df8eb5691c48 ("i2c: Add driver for Cadence I2C controller")
  15 Reported-by: Kyle Roeschley <kyle.roeschley@ni.com>
  16 Acked-by: Michal Simek <michal.simek@xilinx.com>
  17 Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
  18 Tested-by: Kyle Roeschley <kyle.roeschley@ni.com>
  19 Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
  20 Signed-off-by: Sasha Levin <sashal@kernel.org>
  21 ---
  22  drivers/i2c/busses/i2c-cadence.c | 9 +++++++--
  23  1 file changed, 7 insertions(+), 2 deletions(-)
  24
  25 diff --git a/drivers/i2c/busses/i2c-cadence.c b/drivers/i2c/busses/i2c-cadence.c
  26 index b13605718291..d917cefc5a19 100644
  27 --- a/drivers/i2c/busses/i2c-cadence.c
  28 +++ b/drivers/i2c/busses/i2c-cadence.c
  29 @@ -382,8 +382,10 @@ static void cdns_i2c_mrecv(struct cdns_i2c *id)
  30          * Check for the message size against FIFO depth and set the
  31          * 'hold bus' bit if it is greater than FIFO depth.
  32          */
  33 -       if (id->recv_count > CDNS_I2C_FIFO_DEPTH)
  34 +       if ((id->recv_count > CDNS_I2C_FIFO_DEPTH)  || id->bus_hold_flag)
  35                 ctrl_reg |= CDNS_I2C_CR_HOLD;
  36 +       else
  37 +               ctrl_reg = ctrl_reg & ~CDNS_I2C_CR_HOLD;
  38
  39         cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET);
  40
  41 @@ -440,8 +442,11 @@ static void cdns_i2c_msend(struct cdns_i2c *id)
  42          * Check for the message size against FIFO depth and set the
  43          * 'hold bus' bit if it is greater than FIFO depth.
  44          */
  45 -       if (id->send_count > CDNS_I2C_FIFO_DEPTH)
  46 +       if ((id->send_count > CDNS_I2C_FIFO_DEPTH) || id->bus_hold_flag)
  47                 ctrl_reg |= CDNS_I2C_CR_HOLD;
  48 +       else
  49 +               ctrl_reg = ctrl_reg & ~CDNS_I2C_CR_HOLD;
  50 +
  51         cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET);
  52
  53         /* Clear the interrupts in interrupt status register. */
  54 --
  55 2.19.1
  56