queue-4.19/clk-mediatek-disable-tuner_en-before-change-pll-rate.patch

   1 From be17ca6ac76a5cfd07cc3a0397dd05d6929fcbbb Mon Sep 17 00:00:00 2001
   2 From: Owen Chen <owen.chen@mediatek.com>
   3 Date: Tue, 5 Mar 2019 13:05:38 +0800
   4 Subject: clk: mediatek: Disable tuner_en before change PLL rate
   5
   6 From: Owen Chen <owen.chen@mediatek.com>
   7
   8 commit be17ca6ac76a5cfd07cc3a0397dd05d6929fcbbb upstream.
   9
  10 PLLs with tuner_en bit, such as APLL1, need to disable
  11 tuner_en before apply new frequency settings, or the new frequency
  12 settings (pcw) will not be applied.
  13 The tuner_en bit will be disabled during changing PLL rate
  14 and be restored after new settings applied.
  15
  16 Fixes: e2f744a82d725 (clk: mediatek: Add MT2712 clock support)
  17 Cc: <stable@vger.kernel.org>
  18 Signed-off-by: Owen Chen <owen.chen@mediatek.com>
  19 Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
  20 Reviewed-by: James Liao <jamesjj.liao@mediatek.com>
  21 Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
  22 Signed-off-by: Stephen Boyd <sboyd@kernel.org>
  23 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
  24
  25 ---
  26  drivers/clk/mediatek/clk-pll.c |   48 +++++++++++++++++++++++++++++------------
  27  1 file changed, 34 insertions(+), 14 deletions(-)
  28
  29 --- a/drivers/clk/mediatek/clk-pll.c
  30 +++ b/drivers/clk/mediatek/clk-pll.c
  31 @@ -88,6 +88,32 @@ static unsigned long __mtk_pll_recalc_ra
  32         return ((unsigned long)vco + postdiv - 1) / postdiv;
  33  }
  34
  35 +static void __mtk_pll_tuner_enable(struct mtk_clk_pll *pll)
  36 +{
  37 +       u32 r;
  38 +
  39 +       if (pll->tuner_en_addr) {
  40 +               r = readl(pll->tuner_en_addr) | BIT(pll->data->tuner_en_bit);
  41 +               writel(r, pll->tuner_en_addr);
  42 +       } else if (pll->tuner_addr) {
  43 +               r = readl(pll->tuner_addr) | AUDPLL_TUNER_EN;
  44 +               writel(r, pll->tuner_addr);
  45 +       }
  46 +}
  47 +
  48 +static void __mtk_pll_tuner_disable(struct mtk_clk_pll *pll)
  49 +{
  50 +       u32 r;
  51 +
  52 +       if (pll->tuner_en_addr) {
  53 +               r = readl(pll->tuner_en_addr) & ~BIT(pll->data->tuner_en_bit);
  54 +               writel(r, pll->tuner_en_addr);
  55 +       } else if (pll->tuner_addr) {
  56 +               r = readl(pll->tuner_addr) & ~AUDPLL_TUNER_EN;
  57 +               writel(r, pll->tuner_addr);
  58 +       }
  59 +}
  60 +
  61  static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw,
  62                 int postdiv)
  63  {
  64 @@ -96,6 +122,9 @@ static void mtk_pll_set_rate_regs(struct
  65
  66         pll_en = readl(pll->base_addr + REG_CON0) & CON0_BASE_EN;
  67
  68 +       /* disable tuner */
  69 +       __mtk_pll_tuner_disable(pll);
  70 +
  71         /* set postdiv */
  72         val = readl(pll->pd_addr);
  73         val &= ~(POSTDIV_MASK << pll->data->pd_shift);
  74 @@ -122,6 +151,9 @@ static void mtk_pll_set_rate_regs(struct
  75         if (pll->tuner_addr)
  76                 writel(con1 + 1, pll->tuner_addr);
  77
  78 +       /* restore tuner_en */
  79 +       __mtk_pll_tuner_enable(pll);
  80 +
  81         if (pll_en)
  82                 udelay(20);
  83  }
  84 @@ -228,13 +260,7 @@ static int mtk_pll_prepare(struct clk_hw
  85         r |= pll->data->en_mask;
  86         writel(r, pll->base_addr + REG_CON0);
  87
  88 -       if (pll->tuner_en_addr) {
  89 -               r = readl(pll->tuner_en_addr) | BIT(pll->data->tuner_en_bit);
  90 -               writel(r, pll->tuner_en_addr);
  91 -       } else if (pll->tuner_addr) {
  92 -               r = readl(pll->tuner_addr) | AUDPLL_TUNER_EN;
  93 -               writel(r, pll->tuner_addr);
  94 -       }
  95 +       __mtk_pll_tuner_enable(pll);
  96
  97         udelay(20);
  98
  99 @@ -258,13 +284,7 @@ static void mtk_pll_unprepare(struct clk
 100                 writel(r, pll->base_addr + REG_CON0);
 101         }
 102
 103 -       if (pll->tuner_en_addr) {
 104 -               r = readl(pll->tuner_en_addr) & ~BIT(pll->data->tuner_en_bit);
 105 -               writel(r, pll->tuner_en_addr);
 106 -       } else if (pll->tuner_addr) {
 107 -               r = readl(pll->tuner_addr) & ~AUDPLL_TUNER_EN;
 108 -               writel(r, pll->tuner_addr);
 109 -       }
 110 +       __mtk_pll_tuner_disable(pll);
 111
 112         r = readl(pll->base_addr + REG_CON0);
 113         r &= ~CON0_BASE_EN;