queue-4.19/drm-amd-powerplay-correct-power-reading-on-fiji.patch

   1 From f5742ec36422a39b57f0256e4847f61b3c432f8c Mon Sep 17 00:00:00 2001
   2 From: Evan Quan <evan.quan@amd.com>
   3 Date: Mon, 25 Feb 2019 16:44:36 +0800
   4 Subject: drm/amd/powerplay: correct power reading on fiji
   5
   6 From: Evan Quan <evan.quan@amd.com>
   7
   8 commit f5742ec36422a39b57f0256e4847f61b3c432f8c upstream.
   9
  10 Set sampling period as 500ms to provide a smooth power
  11 reading output. Also, correct the register for power
  12 reading.
  13
  14 Signed-off-by: Evan Quan <evan.quan@amd.com>
  15 Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
  16 Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
  17 Cc: stable@vger.kernel.org
  18 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
  19
  20 ---
  21  drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c |    6 +++---
  22  1 file changed, 3 insertions(+), 3 deletions(-)
  23
  24 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
  25 +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
  26 @@ -3487,14 +3487,14 @@ static int smu7_get_gpu_power(struct pp_
  27
  28         smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PmStatusLogStart);
  29         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
  30 -                                                       ixSMU_PM_STATUS_94, 0);
  31 +                                                       ixSMU_PM_STATUS_95, 0);
  32
  33         for (i = 0; i < 10; i++) {
  34 -               mdelay(1);
  35 +               mdelay(500);
  36                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PmStatusLogSample);
  37                 tmp = cgs_read_ind_register(hwmgr->device,
  38                                                 CGS_IND_REG__SMC,
  39 -                                               ixSMU_PM_STATUS_94);
  40 +                                               ixSMU_PM_STATUS_95);
  41                 if (tmp != 0)
  42                         break;
  43         }