queue-4.19/drm-omap-hdmi4_cec-fix-cec-clock-handling-for-pm.patch

   1 From ab478ee0c3f290c40dac5d1e42be49223a54a6c2 Mon Sep 17 00:00:00 2001
   2 From: Tony Lindgren <tony@atomide.com>
   3 Date: Tue, 26 Mar 2019 08:14:37 -0700
   4 Subject: drm/omap: hdmi4_cec: Fix CEC clock handling for PM
   5
   6 [ Upstream commit 36a1da15b5df493241b0011d2185fdd724ac1ed1 ]
   7
   8 If CONFIG_OMAP4_DSS_HDMI_CEC is enabled in .config, deeper SoC idle
   9 states are blocked because the CEC clock gets always enabled on init.
  10
  11 Let's fix the issue by moving the CEC clock handling to happen later in
  12 hdmi_cec_adap_enable() as suggested by Hans Verkuil <hverkuil@xs4all.nl>.
  13 This way the CEC clock gets only enabled when needed. This can be tested
  14 by doing cec-ctl --playback to enable the CEC, and doing cec-ctl --clear
  15 to disable it.
  16
  17 Let's also fix the typo for "divider" in the comments while at it.
  18
  19 Fixes: 8d7f934df8d8 ("omapdrm: hdmi4_cec: add OMAP4 HDMI CEC support")
  20 Suggested-by: Hans Verkuil <hverkuil@xs4all.nl>
  21 Cc: Hans Verkuil <hverkuil@xs4all.nl>
  22 Cc: Jyri Sarha <jsarha@ti.com>
  23 Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
  24 Signed-off-by: Tony Lindgren <tony@atomide.com>
  25 Reviewed-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
  26 Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
  27 Link: https://patchwork.freedesktop.org/patch/msgid/20190326151438.32414-1-tony@atomide.com
  28 Signed-off-by: Sasha Levin <sashal@kernel.org>
  29 ---
  30  drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c | 26 ++++++++++++++++++-------
  31  1 file changed, 19 insertions(+), 7 deletions(-)
  32
  33 diff --git a/drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c b/drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c
  34 index 340383150fb98..ebf9c96d43eee 100644
  35 --- a/drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c
  36 +++ b/drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c
  37 @@ -175,6 +175,7 @@ static int hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable)
  38                 REG_FLD_MOD(core->base, HDMI_CORE_SYS_INTR_UNMASK4, 0, 3, 3);
  39                 hdmi_wp_clear_irqenable(core->wp, HDMI_IRQ_CORE);
  40                 hdmi_wp_set_irqstatus(core->wp, HDMI_IRQ_CORE);
  41 +               REG_FLD_MOD(core->wp->base, HDMI_WP_CLK, 0, 5, 0);
  42                 hdmi4_core_disable(core);
  43                 return 0;
  44         }
  45 @@ -182,16 +183,24 @@ static int hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable)
  46         if (err)
  47                 return err;
  48
  49 +       /*
  50 +        * Initialize CEC clock divider: CEC needs 2MHz clock hence
  51 +        * set the divider to 24 to get 48/24=2MHz clock
  52 +        */
  53 +       REG_FLD_MOD(core->wp->base, HDMI_WP_CLK, 0x18, 5, 0);
  54 +
  55         /* Clear TX FIFO */
  56         if (!hdmi_cec_clear_tx_fifo(adap)) {
  57                 pr_err("cec-%s: could not clear TX FIFO\n", adap->name);
  58 -               return -EIO;
  59 +               err = -EIO;
  60 +               goto err_disable_clk;
  61         }
  62
  63         /* Clear RX FIFO */
  64         if (!hdmi_cec_clear_rx_fifo(adap)) {
  65                 pr_err("cec-%s: could not clear RX FIFO\n", adap->name);
  66 -               return -EIO;
  67 +               err = -EIO;
  68 +               goto err_disable_clk;
  69         }
  70
  71         /* Clear CEC interrupts */
  72 @@ -236,6 +245,12 @@ static int hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable)
  73                 hdmi_write_reg(core->base, HDMI_CEC_INT_STATUS_1, temp);
  74         }
  75         return 0;
  76 +
  77 +err_disable_clk:
  78 +       REG_FLD_MOD(core->wp->base, HDMI_WP_CLK, 0, 5, 0);
  79 +       hdmi4_core_disable(core);
  80 +
  81 +       return err;
  82  }
  83
  84  static int hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr)
  85 @@ -333,11 +348,8 @@ int hdmi4_cec_init(struct platform_device *pdev, struct hdmi_core_data *core,
  86                 return ret;
  87         core->wp = wp;
  88
  89 -       /*
  90 -        * Initialize CEC clock divider: CEC needs 2MHz clock hence
  91 -        * set the devider to 24 to get 48/24=2MHz clock
  92 -        */
  93 -       REG_FLD_MOD(core->wp->base, HDMI_WP_CLK, 0x18, 5, 0);
  94 +       /* Disable clock initially, hdmi_cec_adap_enable() manages it */
  95 +       REG_FLD_MOD(core->wp->base, HDMI_WP_CLK, 0, 5, 0);
  96
  97         ret = cec_register_adapter(core->adap, &pdev->dev);
  98         if (ret < 0) {
  99 --
 100 2.20.1
 101