queue-4.4/asoc-cs4270-set-auto-increment-bit-for-register-writ.patch

   1 From 7e966c62929d0013fe907c1668bcebb519d3b248 Mon Sep 17 00:00:00 2001
   2 From: Daniel Mack <daniel@zonque.org>
   3 Date: Wed, 20 Mar 2019 22:41:56 +0100
   4 Subject: ASoC: cs4270: Set auto-increment bit for register writes
   5
   6 [ Upstream commit f0f2338a9cfaf71db895fa989ea7234e8a9b471d ]
   7
   8 The CS4270 does not by default increment the register address on
   9 consecutive writes. During normal operation it doesn't matter as all
  10 register accesses are done individually. At resume time after suspend,
  11 however, the regcache code gathers the biggest possible block of
  12 registers to sync and sends them one on one go.
  13
  14 To fix this, set the INCR bit in all cases.
  15
  16 Signed-off-by: Daniel Mack <daniel@zonque.org>
  17 Signed-off-by: Mark Brown <broonie@kernel.org>
  18 Signed-off-by: Sasha Levin <sashal@kernel.org>
  19 ---
  20  sound/soc/codecs/cs4270.c | 1 +
  21  1 file changed, 1 insertion(+)
  22
  23 diff --git a/sound/soc/codecs/cs4270.c b/sound/soc/codecs/cs4270.c
  24 index 3670086b9227c..f273533c66535 100644
  25 --- a/sound/soc/codecs/cs4270.c
  26 +++ b/sound/soc/codecs/cs4270.c
  27 @@ -641,6 +641,7 @@ static const struct regmap_config cs4270_regmap = {
  28         .reg_defaults =         cs4270_reg_defaults,
  29         .num_reg_defaults =     ARRAY_SIZE(cs4270_reg_defaults),
  30         .cache_type =           REGCACHE_RBTREE,
  31 +       .write_flag_mask =      CS4270_I2C_INCR,
  32
  33         .readable_reg =         cs4270_reg_is_readable,
  34         .volatile_reg =         cs4270_reg_is_volatile,
  35 --
  36 2.20.1
  37