queue-4.4/drm-exynos-gsc-fix-support-for-nv16-61-yuv420-yvu420-and-yuv422-modes.patch

   1 From foo@baz Wed Aug 22 10:28:26 CEST 2018
   2 From: Marek Szyprowski <m.szyprowski@samsung.com>
   3 Date: Thu, 7 Jun 2018 13:06:13 +0200
   4 Subject: drm/exynos: gsc: Fix support for NV16/61, YUV420/YVU420 and YUV422 modes
   5
   6 From: Marek Szyprowski <m.szyprowski@samsung.com>
   7
   8 [ Upstream commit dd209ef809080ced903e7747ee3ef640c923a1d2 ]
   9
  10 Fix following issues related to planar YUV pixel format configuration:
  11 - NV16/61 modes were incorrectly programmed as NV12/21,
  12 - YVU420 was programmed as YUV420 on source,
  13 - YVU420 and YUV422 were programmed as YUV420 on output.
  14
  15 Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
  16 Signed-off-by: Inki Dae <inki.dae@samsung.com>
  17 Signed-off-by: Sasha Levin <alexander.levin@microsoft.com>
  18 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
  19 ---
  20  drivers/gpu/drm/exynos/exynos_drm_gsc.c |   29 ++++++++++++++++++++---------
  21  drivers/gpu/drm/exynos/regs-gsc.h       |    1 +
  22  2 files changed, 21 insertions(+), 9 deletions(-)
  23
  24 --- a/drivers/gpu/drm/exynos/exynos_drm_gsc.c
  25 +++ b/drivers/gpu/drm/exynos/exynos_drm_gsc.c
  26 @@ -526,21 +526,25 @@ static int gsc_src_set_fmt(struct device
  27                         GSC_IN_CHROMA_ORDER_CRCB);
  28                 break;
  29         case DRM_FORMAT_NV21:
  30 +               cfg |= (GSC_IN_CHROMA_ORDER_CRCB | GSC_IN_YUV420_2P);
  31 +               break;
  32         case DRM_FORMAT_NV61:
  33 -               cfg |= (GSC_IN_CHROMA_ORDER_CRCB |
  34 -                       GSC_IN_YUV420_2P);
  35 +               cfg |= (GSC_IN_CHROMA_ORDER_CRCB | GSC_IN_YUV422_2P);
  36                 break;
  37         case DRM_FORMAT_YUV422:
  38                 cfg |= GSC_IN_YUV422_3P;
  39                 break;
  40         case DRM_FORMAT_YUV420:
  41 +               cfg |= (GSC_IN_CHROMA_ORDER_CBCR | GSC_IN_YUV420_3P);
  42 +               break;
  43         case DRM_FORMAT_YVU420:
  44 -               cfg |= GSC_IN_YUV420_3P;
  45 +               cfg |= (GSC_IN_CHROMA_ORDER_CRCB | GSC_IN_YUV420_3P);
  46                 break;
  47         case DRM_FORMAT_NV12:
  48 +               cfg |= (GSC_IN_CHROMA_ORDER_CBCR | GSC_IN_YUV420_2P);
  49 +               break;
  50         case DRM_FORMAT_NV16:
  51 -               cfg |= (GSC_IN_CHROMA_ORDER_CBCR |
  52 -                       GSC_IN_YUV420_2P);
  53 +               cfg |= (GSC_IN_CHROMA_ORDER_CBCR | GSC_IN_YUV422_2P);
  54                 break;
  55         default:
  56                 dev_err(ippdrv->dev, "invalid target yuv order 0x%x.\n", fmt);
  57 @@ -800,18 +804,25 @@ static int gsc_dst_set_fmt(struct device
  58                         GSC_OUT_CHROMA_ORDER_CRCB);
  59                 break;
  60         case DRM_FORMAT_NV21:
  61 -       case DRM_FORMAT_NV61:
  62                 cfg |= (GSC_OUT_CHROMA_ORDER_CRCB | GSC_OUT_YUV420_2P);
  63                 break;
  64 +       case DRM_FORMAT_NV61:
  65 +               cfg |= (GSC_OUT_CHROMA_ORDER_CRCB | GSC_OUT_YUV422_2P);
  66 +               break;
  67         case DRM_FORMAT_YUV422:
  68 +               cfg |= GSC_OUT_YUV422_3P;
  69 +               break;
  70         case DRM_FORMAT_YUV420:
  71 +               cfg |= (GSC_OUT_CHROMA_ORDER_CBCR | GSC_OUT_YUV420_3P);
  72 +               break;
  73         case DRM_FORMAT_YVU420:
  74 -               cfg |= GSC_OUT_YUV420_3P;
  75 +               cfg |= (GSC_OUT_CHROMA_ORDER_CRCB | GSC_OUT_YUV420_3P);
  76                 break;
  77         case DRM_FORMAT_NV12:
  78 +               cfg |= (GSC_OUT_CHROMA_ORDER_CBCR | GSC_OUT_YUV420_2P);
  79 +               break;
  80         case DRM_FORMAT_NV16:
  81 -               cfg |= (GSC_OUT_CHROMA_ORDER_CBCR |
  82 -                       GSC_OUT_YUV420_2P);
  83 +               cfg |= (GSC_OUT_CHROMA_ORDER_CBCR | GSC_OUT_YUV422_2P);
  84                 break;
  85         default:
  86                 dev_err(ippdrv->dev, "invalid target yuv order 0x%x.\n", fmt);
  87 --- a/drivers/gpu/drm/exynos/regs-gsc.h
  88 +++ b/drivers/gpu/drm/exynos/regs-gsc.h
  89 @@ -138,6 +138,7 @@
  90  #define GSC_OUT_YUV420_3P              (3 << 4)
  91  #define GSC_OUT_YUV422_1P              (4 << 4)
  92  #define GSC_OUT_YUV422_2P              (5 << 4)
  93 +#define GSC_OUT_YUV422_3P              (6 << 4)
  94  #define GSC_OUT_YUV444                 (7 << 4)
  95  #define GSC_OUT_TILE_TYPE_MASK         (1 << 2)
  96  #define GSC_OUT_TILE_C_16x8            (0 << 2)