queue-4.4/x86-bugs-fix-the-amd-ssbd-usage-of-the-spec_ctrl-msr.patch

   1 From foo@baz Tue 14 May 2019 08:29:35 PM CEST
   2 From: Tom Lendacky <thomas.lendacky@amd.com>
   3 Date: Mon, 2 Jul 2018 16:36:02 -0500
   4 Subject: x86/bugs: Fix the AMD SSBD usage of the SPEC_CTRL MSR
   5
   6 From: Tom Lendacky <thomas.lendacky@amd.com>
   7
   8 commit 612bc3b3d4be749f73a513a17d9b3ee1330d3487 upstream.
   9
  10 On AMD, the presence of the MSR_SPEC_CTRL feature does not imply that the
  11 SSBD mitigation support should use the SPEC_CTRL MSR. Other features could
  12 have caused the MSR_SPEC_CTRL feature to be set, while a different SSBD
  13 mitigation option is in place.
  14
  15 Update the SSBD support to check for the actual SSBD features that will
  16 use the SPEC_CTRL MSR.
  17
  18 Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
  19 Cc: Borislav Petkov <bpetkov@suse.de>
  20 Cc: David Woodhouse <dwmw@amazon.co.uk>
  21 Cc: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
  22 Cc: Linus Torvalds <torvalds@linux-foundation.org>
  23 Cc: Peter Zijlstra <peterz@infradead.org>
  24 Cc: Thomas Gleixner <tglx@linutronix.de>
  25 Fixes: 6ac2f49edb1e ("x86/bugs: Add AMD's SPEC_CTRL MSR usage")
  26 Link: http://lkml.kernel.org/r/20180702213602.29202.33151.stgit@tlendack-t1.amdoffice.net
  27 Signed-off-by: Ingo Molnar <mingo@kernel.org>
  28 Signed-off-by: Ben Hutchings <ben@decadent.org.uk>
  29 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
  30 ---
  31  arch/x86/kernel/cpu/bugs.c |    8 +++++---
  32  1 file changed, 5 insertions(+), 3 deletions(-)
  33
  34 --- a/arch/x86/kernel/cpu/bugs.c
  35 +++ b/arch/x86/kernel/cpu/bugs.c
  36 @@ -157,7 +157,8 @@ x86_virt_spec_ctrl(u64 guest_spec_ctrl,
  37                 guestval |= guest_spec_ctrl & x86_spec_ctrl_mask;
  38
  39                 /* SSBD controlled in MSR_SPEC_CTRL */
  40 -               if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD))
  41 +               if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) ||
  42 +                   static_cpu_has(X86_FEATURE_AMD_SSBD))
  43                         hostval |= ssbd_tif_to_spec_ctrl(ti->flags);
  44
  45                 if (hostval != guestval) {
  46 @@ -526,9 +527,10 @@ static enum ssb_mitigation __init __ssb_
  47                  * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD may
  48                  * use a completely different MSR and bit dependent on family.
  49                  */
  50 -               if (!static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
  51 +               if (!static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) &&
  52 +                   !static_cpu_has(X86_FEATURE_AMD_SSBD)) {
  53                         x86_amd_ssb_disable();
  54 -               else {
  55 +               } else {
  56                         x86_spec_ctrl_base |= SPEC_CTRL_SSBD;
  57                         x86_spec_ctrl_mask |= SPEC_CTRL_SSBD;
  58                         wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);