queue-4.4/x86-speculation-mds-add-mds_clear_cpu_buffers.patch

   1 From foo@baz Tue 14 May 2019 08:29:35 PM CEST
   2 From: Thomas Gleixner <tglx@linutronix.de>
   3 Date: Mon, 18 Feb 2019 23:13:06 +0100
   4 Subject: x86/speculation/mds: Add mds_clear_cpu_buffers()
   5
   6 From: Thomas Gleixner <tglx@linutronix.de>
   7
   8 commit 6a9e529272517755904b7afa639f6db59ddb793e upstream.
   9
  10 The Microarchitectural Data Sampling (MDS) vulernabilities are mitigated by
  11 clearing the affected CPU buffers. The mechanism for clearing the buffers
  12 uses the unused and obsolete VERW instruction in combination with a
  13 microcode update which triggers a CPU buffer clear when VERW is executed.
  14
  15 Provide a inline function with the assembly magic. The argument of the VERW
  16 instruction must be a memory operand as documented:
  17
  18   "MD_CLEAR enumerates that the memory-operand variant of VERW (for
  19    example, VERW m16) has been extended to also overwrite buffers affected
  20    by MDS. This buffer overwriting functionality is not guaranteed for the
  21    register operand variant of VERW."
  22
  23 Documentation also recommends to use a writable data segment selector:
  24
  25   "The buffer overwriting occurs regardless of the result of the VERW
  26    permission check, as well as when the selector is null or causes a
  27    descriptor load segment violation. However, for lowest latency we
  28    recommend using a selector that indicates a valid writable data
  29    segment."
  30
  31 Add x86 specific documentation about MDS and the internal workings of the
  32 mitigation.
  33
  34 Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
  35 Reviewed-by: Borislav Petkov <bp@suse.de>
  36 Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
  37 Reviewed-by: Frederic Weisbecker <frederic@kernel.org>
  38 Reviewed-by: Jon Masters <jcm@redhat.com>
  39 Tested-by: Jon Masters <jcm@redhat.com>
  40 [bwh: Backported to 4.4: drop changes to doc index and configuration]
  41 Signed-off-by: Ben Hutchings <ben@decadent.org.uk>
  42 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
  43 ---
  44  Documentation/x86/mds.rst            |   99 +++++++++++++++++++++++++++++++++++
  45  arch/x86/include/asm/nospec-branch.h |   25 ++++++++
  46  2 files changed, 124 insertions(+)
  47  create mode 100644 Documentation/x86/mds.rst
  48
  49 --- /dev/null
  50 +++ b/Documentation/x86/mds.rst
  51 @@ -0,0 +1,99 @@
  52 +Microarchitectural Data Sampling (MDS) mitigation
  53 +=================================================
  54 +
  55 +.. _mds:
  56 +
  57 +Overview
  58 +--------
  59 +
  60 +Microarchitectural Data Sampling (MDS) is a family of side channel attacks
  61 +on internal buffers in Intel CPUs. The variants are:
  62 +
  63 + - Microarchitectural Store Buffer Data Sampling (MSBDS) (CVE-2018-12126)
  64 + - Microarchitectural Fill Buffer Data Sampling (MFBDS) (CVE-2018-12130)
  65 + - Microarchitectural Load Port Data Sampling (MLPDS) (CVE-2018-12127)
  66 +
  67 +MSBDS leaks Store Buffer Entries which can be speculatively forwarded to a
  68 +dependent load (store-to-load forwarding) as an optimization. The forward
  69 +can also happen to a faulting or assisting load operation for a different
  70 +memory address, which can be exploited under certain conditions. Store
  71 +buffers are partitioned between Hyper-Threads so cross thread forwarding is
  72 +not possible. But if a thread enters or exits a sleep state the store
  73 +buffer is repartitioned which can expose data from one thread to the other.
  74 +
  75 +MFBDS leaks Fill Buffer Entries. Fill buffers are used internally to manage
  76 +L1 miss situations and to hold data which is returned or sent in response
  77 +to a memory or I/O operation. Fill buffers can forward data to a load
  78 +operation and also write data to the cache. When the fill buffer is
  79 +deallocated it can retain the stale data of the preceding operations which
  80 +can then be forwarded to a faulting or assisting load operation, which can
  81 +be exploited under certain conditions. Fill buffers are shared between
  82 +Hyper-Threads so cross thread leakage is possible.
  83 +
  84 +MLPDS leaks Load Port Data. Load ports are used to perform load operations
  85 +from memory or I/O. The received data is then forwarded to the register
  86 +file or a subsequent operation. In some implementations the Load Port can
  87 +contain stale data from a previous operation which can be forwarded to
  88 +faulting or assisting loads under certain conditions, which again can be
  89 +exploited eventually. Load ports are shared between Hyper-Threads so cross
  90 +thread leakage is possible.
  91 +
  92 +
  93 +Exposure assumptions
  94 +--------------------
  95 +
  96 +It is assumed that attack code resides in user space or in a guest with one
  97 +exception. The rationale behind this assumption is that the code construct
  98 +needed for exploiting MDS requires:
  99 +
 100 + - to control the load to trigger a fault or assist
 101 +
 102 + - to have a disclosure gadget which exposes the speculatively accessed
 103 +   data for consumption through a side channel.
 104 +
 105 + - to control the pointer through which the disclosure gadget exposes the
 106 +   data
 107 +
 108 +The existence of such a construct in the kernel cannot be excluded with
 109 +100% certainty, but the complexity involved makes it extremly unlikely.
 110 +
 111 +There is one exception, which is untrusted BPF. The functionality of
 112 +untrusted BPF is limited, but it needs to be thoroughly investigated
 113 +whether it can be used to create such a construct.
 114 +
 115 +
 116 +Mitigation strategy
 117 +-------------------
 118 +
 119 +All variants have the same mitigation strategy at least for the single CPU
 120 +thread case (SMT off): Force the CPU to clear the affected buffers.
 121 +
 122 +This is achieved by using the otherwise unused and obsolete VERW
 123 +instruction in combination with a microcode update. The microcode clears
 124 +the affected CPU buffers when the VERW instruction is executed.
 125 +
 126 +For virtualization there are two ways to achieve CPU buffer
 127 +clearing. Either the modified VERW instruction or via the L1D Flush
 128 +command. The latter is issued when L1TF mitigation is enabled so the extra
 129 +VERW can be avoided. If the CPU is not affected by L1TF then VERW needs to
 130 +be issued.
 131 +
 132 +If the VERW instruction with the supplied segment selector argument is
 133 +executed on a CPU without the microcode update there is no side effect
 134 +other than a small number of pointlessly wasted CPU cycles.
 135 +
 136 +This does not protect against cross Hyper-Thread attacks except for MSBDS
 137 +which is only exploitable cross Hyper-thread when one of the Hyper-Threads
 138 +enters a C-state.
 139 +
 140 +The kernel provides a function to invoke the buffer clearing:
 141 +
 142 +    mds_clear_cpu_buffers()
 143 +
 144 +The mitigation is invoked on kernel/userspace, hypervisor/guest and C-state
 145 +(idle) transitions.
 146 +
 147 +According to current knowledge additional mitigations inside the kernel
 148 +itself are not required because the necessary gadgets to expose the leaked
 149 +data cannot be controlled in a way which allows exploitation from malicious
 150 +user space or VM guests.
 151 --- a/arch/x86/include/asm/nospec-branch.h
 152 +++ b/arch/x86/include/asm/nospec-branch.h
 153 @@ -262,6 +262,31 @@ DECLARE_STATIC_KEY_FALSE(switch_to_cond_
 154  DECLARE_STATIC_KEY_FALSE(switch_mm_cond_ibpb);
 155  DECLARE_STATIC_KEY_FALSE(switch_mm_always_ibpb);
 156
 157 +#include <asm/segment.h>
 158 +
 159 +/**
 160 + * mds_clear_cpu_buffers - Mitigation for MDS vulnerability
 161 + *
 162 + * This uses the otherwise unused and obsolete VERW instruction in
 163 + * combination with microcode which triggers a CPU buffer flush when the
 164 + * instruction is executed.
 165 + */
 166 +static inline void mds_clear_cpu_buffers(void)
 167 +{
 168 +       static const u16 ds = __KERNEL_DS;
 169 +
 170 +       /*
 171 +        * Has to be the memory-operand variant because only that
 172 +        * guarantees the CPU buffer flush functionality according to
 173 +        * documentation. The register-operand variant does not.
 174 +        * Works with any segment selector, but a valid writable
 175 +        * data segment is the fastest variant.
 176 +        *
 177 +        * "cc" clobber is required because VERW modifies ZF.
 178 +        */
 179 +       asm volatile("verw %[ds]" : : [ds] "m" (ds) : "cc");
 180 +}
 181 +
 182  #endif /* __ASSEMBLY__ */
 183
 184  /*