queue-4.4/x86-speculation-rename-ssbd-update-functions.patch

   1 From foo@baz Tue 14 May 2019 08:29:35 PM CEST
   2 From: Thomas Gleixner <tglx@linutronix.de>
   3 Date: Sun, 25 Nov 2018 19:33:34 +0100
   4 Subject: x86/speculation: Rename SSBD update functions
   5
   6 From: Thomas Gleixner <tglx@linutronix.de>
   7
   8 commit 26c4d75b234040c11728a8acb796b3a85ba7507c upstream.
   9
  10 During context switch, the SSBD bit in SPEC_CTRL MSR is updated according
  11 to changes of the TIF_SSBD flag in the current and next running task.
  12
  13 Currently, only the bit controlling speculative store bypass disable in
  14 SPEC_CTRL MSR is updated and the related update functions all have
  15 "speculative_store" or "ssb" in their names.
  16
  17 For enhanced mitigation control other bits in SPEC_CTRL MSR need to be
  18 updated as well, which makes the SSB names inadequate.
  19
  20 Rename the "speculative_store*" functions to a more generic name. No
  21 functional change.
  22
  23 Signed-off-by: Tim Chen <tim.c.chen@linux.intel.com>
  24 Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
  25 Reviewed-by: Ingo Molnar <mingo@kernel.org>
  26 Cc: Peter Zijlstra <peterz@infradead.org>
  27 Cc: Andy Lutomirski <luto@kernel.org>
  28 Cc: Linus Torvalds <torvalds@linux-foundation.org>
  29 Cc: Jiri Kosina <jkosina@suse.cz>
  30 Cc: Tom Lendacky <thomas.lendacky@amd.com>
  31 Cc: Josh Poimboeuf <jpoimboe@redhat.com>
  32 Cc: Andrea Arcangeli <aarcange@redhat.com>
  33 Cc: David Woodhouse <dwmw@amazon.co.uk>
  34 Cc: Andi Kleen <ak@linux.intel.com>
  35 Cc: Dave Hansen <dave.hansen@intel.com>
  36 Cc: Casey Schaufler <casey.schaufler@intel.com>
  37 Cc: Asit Mallick <asit.k.mallick@intel.com>
  38 Cc: Arjan van de Ven <arjan@linux.intel.com>
  39 Cc: Jon Masters <jcm@redhat.com>
  40 Cc: Waiman Long <longman9394@gmail.com>
  41 Cc: Greg KH <gregkh@linuxfoundation.org>
  42 Cc: Dave Stewart <david.c.stewart@intel.com>
  43 Cc: Kees Cook <keescook@chromium.org>
  44 Link: https://lkml.kernel.org/r/20181125185004.058866968@linutronix.de
  45 Signed-off-by: Ben Hutchings <ben@decadent.org.uk>
  46 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
  47 ---
  48  arch/x86/include/asm/spec-ctrl.h |    6 +++---
  49  arch/x86/kernel/cpu/bugs.c       |    4 ++--
  50  arch/x86/kernel/process.c        |   12 ++++++------
  51  3 files changed, 11 insertions(+), 11 deletions(-)
  52
  53 --- a/arch/x86/include/asm/spec-ctrl.h
  54 +++ b/arch/x86/include/asm/spec-ctrl.h
  55 @@ -70,11 +70,11 @@ extern void speculative_store_bypass_ht_
  56  static inline void speculative_store_bypass_ht_init(void) { }
  57  #endif
  58
  59 -extern void speculative_store_bypass_update(unsigned long tif);
  60 +extern void speculation_ctrl_update(unsigned long tif);
  61
  62 -static inline void speculative_store_bypass_update_current(void)
  63 +static inline void speculation_ctrl_update_current(void)
  64  {
  65 -       speculative_store_bypass_update(current_thread_info()->flags);
  66 +       speculation_ctrl_update(current_thread_info()->flags);
  67  }
  68
  69  #endif
  70 --- a/arch/x86/kernel/cpu/bugs.c
  71 +++ b/arch/x86/kernel/cpu/bugs.c
  72 @@ -192,7 +192,7 @@ x86_virt_spec_ctrl(u64 guest_spec_ctrl,
  73                 tif = setguest ? ssbd_spec_ctrl_to_tif(guestval) :
  74                                  ssbd_spec_ctrl_to_tif(hostval);
  75
  76 -               speculative_store_bypass_update(tif);
  77 +               speculation_ctrl_update(tif);
  78         }
  79  }
  80  EXPORT_SYMBOL_GPL(x86_virt_spec_ctrl);
  81 @@ -629,7 +629,7 @@ static int ssb_prctl_set(struct task_str
  82          * mitigation until it is next scheduled.
  83          */
  84         if (task == current && update)
  85 -               speculative_store_bypass_update_current();
  86 +               speculation_ctrl_update_current();
  87
  88         return 0;
  89  }
  90 --- a/arch/x86/kernel/process.c
  91 +++ b/arch/x86/kernel/process.c
  92 @@ -317,27 +317,27 @@ static __always_inline void amd_set_ssb_
  93         wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, ssbd_tif_to_spec_ctrl(tifn));
  94  }
  95
  96 -static __always_inline void intel_set_ssb_state(unsigned long tifn)
  97 +static __always_inline void spec_ctrl_update_msr(unsigned long tifn)
  98  {
  99         u64 msr = x86_spec_ctrl_base | ssbd_tif_to_spec_ctrl(tifn);
 100
 101         wrmsrl(MSR_IA32_SPEC_CTRL, msr);
 102  }
 103
 104 -static __always_inline void __speculative_store_bypass_update(unsigned long tifn)
 105 +static __always_inline void __speculation_ctrl_update(unsigned long tifn)
 106  {
 107         if (static_cpu_has(X86_FEATURE_VIRT_SSBD))
 108                 amd_set_ssb_virt_state(tifn);
 109         else if (static_cpu_has(X86_FEATURE_LS_CFG_SSBD))
 110                 amd_set_core_ssb_state(tifn);
 111         else
 112 -               intel_set_ssb_state(tifn);
 113 +               spec_ctrl_update_msr(tifn);
 114  }
 115
 116 -void speculative_store_bypass_update(unsigned long tif)
 117 +void speculation_ctrl_update(unsigned long tif)
 118  {
 119         preempt_disable();
 120 -       __speculative_store_bypass_update(tif);
 121 +       __speculation_ctrl_update(tif);
 122         preempt_enable();
 123  }
 124
 125 @@ -371,7 +371,7 @@ void __switch_to_xtra(struct task_struct
 126                 cr4_toggle_bits(X86_CR4_TSD);
 127
 128         if ((tifp ^ tifn) & _TIF_SSBD)
 129 -               __speculative_store_bypass_update(tifn);
 130 +               __speculation_ctrl_update(tifn);
 131  }
 132
 133  /*