queue-4.9/0003-x86-bugs-Add-AMD-s-variant-of-SSB_NO.patch

   1 From 47f09ebcbbea9b9ddd3140a8b63ce42a2879ec75 Mon Sep 17 00:00:00 2001
   2 From: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
   3 Date: Fri, 1 Jun 2018 10:59:19 -0400
   4 Subject: [PATCH 03/76] x86/bugs: Add AMD's variant of SSB_NO
   5
   6 commit 24809860012e0130fbafe536709e08a22b3e959e upstream.
   7
   8 The AMD document outlining the SSBD handling
   9 124441_AMD64_SpeculativeStoreBypassDisable_Whitepaper_final.pdf
  10 mentions that the CPUID 8000_0008.EBX[26] will mean that the
  11 speculative store bypass disable is no longer needed.
  12
  13 A copy of this document is available at:
  14     https://bugzilla.kernel.org/show_bug.cgi?id=199889
  15
  16 Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
  17 Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
  18 Cc: Tom Lendacky <thomas.lendacky@amd.com>
  19 Cc: Janakarajan Natarajan <Janakarajan.Natarajan@amd.com>
  20 Cc: kvm@vger.kernel.org
  21 Cc: andrew.cooper3@citrix.com
  22 Cc: Andy Lutomirski <luto@kernel.org>
  23 Cc: "H. Peter Anvin" <hpa@zytor.com>
  24 Cc: Borislav Petkov <bp@suse.de>
  25 Cc: David Woodhouse <dwmw@amazon.co.uk>
  26 Link: https://lkml.kernel.org/r/20180601145921.9500-2-konrad.wilk@oracle.com
  27 [bwh: Backported to 4.9: adjust context, indentation]
  28 Signed-off-by: Ben Hutchings <ben@decadent.org.uk>
  29 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
  30 ---
  31  arch/x86/include/asm/cpufeatures.h | 1 +
  32  arch/x86/kernel/cpu/common.c       | 3 ++-
  33  arch/x86/kvm/cpuid.c               | 2 +-
  34  3 files changed, 4 insertions(+), 2 deletions(-)
  35
  36 diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
  37 index e493a5836ff1..453ab6f3bca0 100644
  38 --- a/arch/x86/include/asm/cpufeatures.h
  39 +++ b/arch/x86/include/asm/cpufeatures.h
  40 @@ -275,6 +275,7 @@
  41  #define X86_FEATURE_AMD_IBRS   (13*32+14) /* "" Indirect Branch Restricted Speculation */
  42  #define X86_FEATURE_AMD_STIBP  (13*32+15) /* "" Single Thread Indirect Branch Predictors */
  43  #define X86_FEATURE_VIRT_SSBD  (13*32+25) /* Virtualized Speculative Store Bypass Disable */
  44 +#define X86_FEATURE_AMD_SSB_NO (13*32+26) /* "" Speculative Store Bypass is fixed in hardware. */
  45
  46  /* Thermal and Power Management Leaf, CPUID level 0x00000006 (eax), word 14 */
  47  #define X86_FEATURE_DTHERM     (14*32+ 0) /* Digital Thermal Sensor */
  48 diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
  49 index 3c01610c5ba9..9b8e912fd840 100644
  50 --- a/arch/x86/kernel/cpu/common.c
  51 +++ b/arch/x86/kernel/cpu/common.c
  52 @@ -950,7 +950,8 @@ static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c)
  53                 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, ia32_cap);
  54
  55         if (!x86_match_cpu(cpu_no_spec_store_bypass) &&
  56 -          !(ia32_cap & ARCH_CAP_SSB_NO))
  57 +          !(ia32_cap & ARCH_CAP_SSB_NO) &&
  58 +          !cpu_has(c, X86_FEATURE_AMD_SSB_NO))
  59                 setup_force_cpu_bug(X86_BUG_SPEC_STORE_BYPASS);
  60
  61         if (x86_match_cpu(cpu_no_speculation))
  62 diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
  63 index c17d3893ae60..f1f1a128bbdb 100644
  64 --- a/arch/x86/kvm/cpuid.c
  65 +++ b/arch/x86/kvm/cpuid.c
  66 @@ -355,7 +355,7 @@ static inline int __do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
  67
  68         /* cpuid 0x80000008.ebx */
  69         const u32 kvm_cpuid_8000_0008_ebx_x86_features =
  70 -               F(AMD_IBPB) | F(AMD_IBRS) | F(VIRT_SSBD);
  71 +               F(AMD_IBPB) | F(AMD_IBRS) | F(VIRT_SSBD) | F(AMD_SSB_NO);
  72
  73         /* cpuid 0xC0000001.edx */
  74         const u32 kvm_cpuid_C000_0001_edx_x86_features =
  75 --
  76 2.21.0
  77