queue-4.9/0028-x86-speculation-Reorganize-speculation-control-MSRs-.patch

   1 From 2a87265c37507a65d0476c6bc13280a3e3123e72 Mon Sep 17 00:00:00 2001
   2 From: Tim Chen <tim.c.chen@linux.intel.com>
   3 Date: Sun, 25 Nov 2018 19:33:35 +0100
   4 Subject: [PATCH 28/76] x86/speculation: Reorganize speculation control MSRs
   5  update
   6
   7 commit 01daf56875ee0cd50ed496a09b20eb369b45dfa5 upstream.
   8
   9 The logic to detect whether there's a change in the previous and next
  10 task's flag relevant to update speculation control MSRs is spread out
  11 across multiple functions.
  12
  13 Consolidate all checks needed for updating speculation control MSRs into
  14 the new __speculation_ctrl_update() helper function.
  15
  16 This makes it easy to pick the right speculation control MSR and the bits
  17 in MSR_IA32_SPEC_CTRL that need updating based on TIF flags changes.
  18
  19 Originally-by: Thomas Lendacky <Thomas.Lendacky@amd.com>
  20 Signed-off-by: Tim Chen <tim.c.chen@linux.intel.com>
  21 Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
  22 Reviewed-by: Ingo Molnar <mingo@kernel.org>
  23 Cc: Peter Zijlstra <peterz@infradead.org>
  24 Cc: Andy Lutomirski <luto@kernel.org>
  25 Cc: Linus Torvalds <torvalds@linux-foundation.org>
  26 Cc: Jiri Kosina <jkosina@suse.cz>
  27 Cc: Tom Lendacky <thomas.lendacky@amd.com>
  28 Cc: Josh Poimboeuf <jpoimboe@redhat.com>
  29 Cc: Andrea Arcangeli <aarcange@redhat.com>
  30 Cc: David Woodhouse <dwmw@amazon.co.uk>
  31 Cc: Andi Kleen <ak@linux.intel.com>
  32 Cc: Dave Hansen <dave.hansen@intel.com>
  33 Cc: Casey Schaufler <casey.schaufler@intel.com>
  34 Cc: Asit Mallick <asit.k.mallick@intel.com>
  35 Cc: Arjan van de Ven <arjan@linux.intel.com>
  36 Cc: Jon Masters <jcm@redhat.com>
  37 Cc: Waiman Long <longman9394@gmail.com>
  38 Cc: Greg KH <gregkh@linuxfoundation.org>
  39 Cc: Dave Stewart <david.c.stewart@intel.com>
  40 Cc: Kees Cook <keescook@chromium.org>
  41 Link: https://lkml.kernel.org/r/20181125185004.151077005@linutronix.de
  42 Signed-off-by: Ben Hutchings <ben@decadent.org.uk>
  43 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
  44 ---
  45  arch/x86/kernel/process.c | 46 ++++++++++++++++++++++++---------------
  46  1 file changed, 29 insertions(+), 17 deletions(-)
  47
  48 diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c
  49 index 36ab44270a82..8ab00560e27d 100644
  50 --- a/arch/x86/kernel/process.c
  51 +++ b/arch/x86/kernel/process.c
  52 @@ -321,27 +321,40 @@ static __always_inline void amd_set_ssb_virt_state(unsigned long tifn)
  53         wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, ssbd_tif_to_spec_ctrl(tifn));
  54  }
  55
  56 -static __always_inline void spec_ctrl_update_msr(unsigned long tifn)
  57 -{
  58 -       u64 msr = x86_spec_ctrl_base | ssbd_tif_to_spec_ctrl(tifn);
  59 -
  60 -       wrmsrl(MSR_IA32_SPEC_CTRL, msr);
  61 -}
  62 +/*
  63 + * Update the MSRs managing speculation control, during context switch.
  64 + *
  65 + * tifp: Previous task's thread flags
  66 + * tifn: Next task's thread flags
  67 + */
  68 +static __always_inline void __speculation_ctrl_update(unsigned long tifp,
  69 +                                                     unsigned long tifn)
  70 +{
  71 +       u64 msr = x86_spec_ctrl_base;
  72 +       bool updmsr = false;
  73 +
  74 +       /* If TIF_SSBD is different, select the proper mitigation method */
  75 +       if ((tifp ^ tifn) & _TIF_SSBD) {
  76 +               if (static_cpu_has(X86_FEATURE_VIRT_SSBD)) {
  77 +                       amd_set_ssb_virt_state(tifn);
  78 +               } else if (static_cpu_has(X86_FEATURE_LS_CFG_SSBD)) {
  79 +                       amd_set_core_ssb_state(tifn);
  80 +               } else if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) ||
  81 +                          static_cpu_has(X86_FEATURE_AMD_SSBD)) {
  82 +                       msr |= ssbd_tif_to_spec_ctrl(tifn);
  83 +                       updmsr  = true;
  84 +               }
  85 +       }
  86
  87 -static __always_inline void __speculation_ctrl_update(unsigned long tifn)
  88 -{
  89 -       if (static_cpu_has(X86_FEATURE_VIRT_SSBD))
  90 -               amd_set_ssb_virt_state(tifn);
  91 -       else if (static_cpu_has(X86_FEATURE_LS_CFG_SSBD))
  92 -               amd_set_core_ssb_state(tifn);
  93 -       else
  94 -               spec_ctrl_update_msr(tifn);
  95 +       if (updmsr)
  96 +               wrmsrl(MSR_IA32_SPEC_CTRL, msr);
  97  }
  98
  99  void speculation_ctrl_update(unsigned long tif)
 100  {
 101 +       /* Forced update. Make sure all relevant TIF flags are different */
 102         preempt_disable();
 103 -       __speculation_ctrl_update(tif);
 104 +       __speculation_ctrl_update(~tif, tif);
 105         preempt_enable();
 106  }
 107
 108 @@ -374,8 +387,7 @@ void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p,
 109         if ((tifp ^ tifn) & _TIF_NOTSC)
 110                 cr4_toggle_bits(X86_CR4_TSD);
 111
 112 -       if ((tifp ^ tifn) & _TIF_SSBD)
 113 -               __speculation_ctrl_update(tifn);
 114 +       __speculation_ctrl_update(tifp, tifn);
 115  }
 116
 117  /*
 118 --
 119 2.21.0
 120