queue-4.9/0050-x86-msr-index-Cleanup-bit-defines.patch

   1 From f51b16c5efb39753dbb678c102ae390d9567927c Mon Sep 17 00:00:00 2001
   2 From: Thomas Gleixner <tglx@linutronix.de>
   3 Date: Thu, 21 Feb 2019 12:36:50 +0100
   4 Subject: [PATCH 50/76] x86/msr-index: Cleanup bit defines
   5
   6 commit d8eabc37310a92df40d07c5a8afc53cebf996716 upstream.
   7
   8 Greg pointed out that speculation related bit defines are using (1 << N)
   9 format instead of BIT(N). Aside of that (1 << N) is wrong as it should use
  10 1UL at least.
  11
  12 Clean it up.
  13
  14 [ Josh Poimboeuf: Fix tools build ]
  15
  16 Reported-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
  17 Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
  18 Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
  19 Reviewed-by: Borislav Petkov <bp@suse.de>
  20 Reviewed-by: Frederic Weisbecker <frederic@kernel.org>
  21 Reviewed-by: Jon Masters <jcm@redhat.com>
  22 Tested-by: Jon Masters <jcm@redhat.com>
  23 [bwh: Backported to 4.9: Drop change to x86_energy_perf_policy, which doesn't
  24  use msr-index.h here]
  25 Signed-off-by: Ben Hutchings <ben@decadent.org.uk>
  26 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
  27 ---
  28  arch/x86/include/asm/msr-index.h   | 34 ++++++++++++++++--------------
  29  tools/power/x86/turbostat/Makefile |  2 +-
  30  2 files changed, 19 insertions(+), 17 deletions(-)
  31
  32 diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
  33 index d7813b118ac8..dc582c10586c 100644
  34 --- a/arch/x86/include/asm/msr-index.h
  35 +++ b/arch/x86/include/asm/msr-index.h
  36 @@ -1,6 +1,8 @@
  37  #ifndef _ASM_X86_MSR_INDEX_H
  38  #define _ASM_X86_MSR_INDEX_H
  39
  40 +#include <linux/bits.h>
  41 +
  42  /*
  43   * CPU model specific register (MSR) numbers.
  44   *
  45 @@ -38,14 +40,14 @@
  46
  47  /* Intel MSRs. Some also available on other CPUs */
  48  #define MSR_IA32_SPEC_CTRL             0x00000048 /* Speculation Control */
  49 -#define SPEC_CTRL_IBRS                 (1 << 0)   /* Indirect Branch Restricted Speculation */
  50 +#define SPEC_CTRL_IBRS                 BIT(0)     /* Indirect Branch Restricted Speculation */
  51  #define SPEC_CTRL_STIBP_SHIFT          1          /* Single Thread Indirect Branch Predictor (STIBP) bit */
  52 -#define SPEC_CTRL_STIBP                        (1 << SPEC_CTRL_STIBP_SHIFT)    /* STIBP mask */
  53 +#define SPEC_CTRL_STIBP                        BIT(SPEC_CTRL_STIBP_SHIFT)      /* STIBP mask */
  54  #define SPEC_CTRL_SSBD_SHIFT           2          /* Speculative Store Bypass Disable bit */
  55 -#define SPEC_CTRL_SSBD                 (1 << SPEC_CTRL_SSBD_SHIFT)     /* Speculative Store Bypass Disable */
  56 +#define SPEC_CTRL_SSBD                 BIT(SPEC_CTRL_SSBD_SHIFT)       /* Speculative Store Bypass Disable */
  57
  58  #define MSR_IA32_PRED_CMD              0x00000049 /* Prediction Command */
  59 -#define PRED_CMD_IBPB                  (1 << 0)   /* Indirect Branch Prediction Barrier */
  60 +#define PRED_CMD_IBPB                  BIT(0)     /* Indirect Branch Prediction Barrier */
  61
  62  #define MSR_IA32_PERFCTR0              0x000000c1
  63  #define MSR_IA32_PERFCTR1              0x000000c2
  64 @@ -62,20 +64,20 @@
  65  #define MSR_MTRRcap                    0x000000fe
  66
  67  #define MSR_IA32_ARCH_CAPABILITIES     0x0000010a
  68 -#define ARCH_CAP_RDCL_NO               (1 << 0)   /* Not susceptible to Meltdown */
  69 -#define ARCH_CAP_IBRS_ALL              (1 << 1)   /* Enhanced IBRS support */
  70 -#define ARCH_CAP_SKIP_VMENTRY_L1DFLUSH (1 << 3)   /* Skip L1D flush on vmentry */
  71 -#define ARCH_CAP_SSB_NO                        (1 << 4)   /*
  72 -                                                   * Not susceptible to Speculative Store Bypass
  73 -                                                   * attack, so no Speculative Store Bypass
  74 -                                                   * control required.
  75 -                                                   */
  76 +#define ARCH_CAP_RDCL_NO               BIT(0)  /* Not susceptible to Meltdown */
  77 +#define ARCH_CAP_IBRS_ALL              BIT(1)  /* Enhanced IBRS support */
  78 +#define ARCH_CAP_SKIP_VMENTRY_L1DFLUSH BIT(3)  /* Skip L1D flush on vmentry */
  79 +#define ARCH_CAP_SSB_NO                        BIT(4)  /*
  80 +                                                * Not susceptible to Speculative Store Bypass
  81 +                                                * attack, so no Speculative Store Bypass
  82 +                                                * control required.
  83 +                                                */
  84
  85  #define MSR_IA32_FLUSH_CMD             0x0000010b
  86 -#define L1D_FLUSH                      (1 << 0)   /*
  87 -                                                   * Writeback and invalidate the
  88 -                                                   * L1 data cache.
  89 -                                                   */
  90 +#define L1D_FLUSH                      BIT(0)  /*
  91 +                                                * Writeback and invalidate the
  92 +                                                * L1 data cache.
  93 +                                                */
  94
  95  #define MSR_IA32_BBL_CR_CTL            0x00000119
  96  #define MSR_IA32_BBL_CR_CTL3           0x0000011e
  97 diff --git a/tools/power/x86/turbostat/Makefile b/tools/power/x86/turbostat/Makefile
  98 index 8561e7ddca59..92be948c922d 100644
  99 --- a/tools/power/x86/turbostat/Makefile
 100 +++ b/tools/power/x86/turbostat/Makefile
 101 @@ -8,7 +8,7 @@ ifeq ("$(origin O)", "command line")
 102  endif
 103
 104  turbostat : turbostat.c
 105 -CFLAGS +=      -Wall
 106 +CFLAGS +=      -Wall -I../../../include
 107  CFLAGS +=      -DMSRHEADER='"../../../../arch/x86/include/asm/msr-index.h"'
 108
 109  %: %.c
 110 --
 111 2.21.0
 112