queue-4.9/iommu-tegra-smmu-fix-invalid-asid-bits-on-tegra30-114.patch

   1 From 43a0541e312f7136e081e6bf58f6c8a2e9672688 Mon Sep 17 00:00:00 2001
   2 From: Dmitry Osipenko <digetx@gmail.com>
   3 Date: Thu, 7 Mar 2019 01:50:07 +0300
   4 Subject: iommu/tegra-smmu: Fix invalid ASID bits on Tegra30/114
   5
   6 From: Dmitry Osipenko <digetx@gmail.com>
   7
   8 commit 43a0541e312f7136e081e6bf58f6c8a2e9672688 upstream.
   9
  10 Both Tegra30 and Tegra114 have 4 ASID's and the corresponding bitfield of
  11 the TLB_FLUSH register differs from later Tegra generations that have 128
  12 ASID's.
  13
  14 In a result the PTE's are now flushed correctly from TLB and this fixes
  15 problems with graphics (randomly failing tests) on Tegra30.
  16
  17 Cc: stable <stable@vger.kernel.org>
  18 Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
  19 Acked-by: Thierry Reding <treding@nvidia.com>
  20 Signed-off-by: Joerg Roedel <jroedel@suse.de>
  21 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
  22
  23 ---
  24  drivers/iommu/tegra-smmu.c |   25 ++++++++++++++++++-------
  25  1 file changed, 18 insertions(+), 7 deletions(-)
  26
  27 --- a/drivers/iommu/tegra-smmu.c
  28 +++ b/drivers/iommu/tegra-smmu.c
  29 @@ -91,7 +91,6 @@ static inline u32 smmu_readl(struct tegr
  30  #define  SMMU_TLB_FLUSH_VA_MATCH_ALL     (0 << 0)
  31  #define  SMMU_TLB_FLUSH_VA_MATCH_SECTION (2 << 0)
  32  #define  SMMU_TLB_FLUSH_VA_MATCH_GROUP   (3 << 0)
  33 -#define  SMMU_TLB_FLUSH_ASID(x)          (((x) & 0x7f) << 24)
  34  #define  SMMU_TLB_FLUSH_VA_SECTION(addr) ((((addr) & 0xffc00000) >> 12) | \
  35                                           SMMU_TLB_FLUSH_VA_MATCH_SECTION)
  36  #define  SMMU_TLB_FLUSH_VA_GROUP(addr)   ((((addr) & 0xffffc000) >> 12) | \
  37 @@ -194,8 +193,12 @@ static inline void smmu_flush_tlb_asid(s
  38  {
  39         u32 value;
  40
  41 -       value = SMMU_TLB_FLUSH_ASID_MATCH | SMMU_TLB_FLUSH_ASID(asid) |
  42 -               SMMU_TLB_FLUSH_VA_MATCH_ALL;
  43 +       if (smmu->soc->num_asids == 4)
  44 +               value = (asid & 0x3) << 29;
  45 +       else
  46 +               value = (asid & 0x7f) << 24;
  47 +
  48 +       value |= SMMU_TLB_FLUSH_ASID_MATCH | SMMU_TLB_FLUSH_VA_MATCH_ALL;
  49         smmu_writel(smmu, value, SMMU_TLB_FLUSH);
  50  }
  51
  52 @@ -205,8 +208,12 @@ static inline void smmu_flush_tlb_sectio
  53  {
  54         u32 value;
  55
  56 -       value = SMMU_TLB_FLUSH_ASID_MATCH | SMMU_TLB_FLUSH_ASID(asid) |
  57 -               SMMU_TLB_FLUSH_VA_SECTION(iova);
  58 +       if (smmu->soc->num_asids == 4)
  59 +               value = (asid & 0x3) << 29;
  60 +       else
  61 +               value = (asid & 0x7f) << 24;
  62 +
  63 +       value |= SMMU_TLB_FLUSH_ASID_MATCH | SMMU_TLB_FLUSH_VA_SECTION(iova);
  64         smmu_writel(smmu, value, SMMU_TLB_FLUSH);
  65  }
  66
  67 @@ -216,8 +223,12 @@ static inline void smmu_flush_tlb_group(
  68  {
  69         u32 value;
  70
  71 -       value = SMMU_TLB_FLUSH_ASID_MATCH | SMMU_TLB_FLUSH_ASID(asid) |
  72 -               SMMU_TLB_FLUSH_VA_GROUP(iova);
  73 +       if (smmu->soc->num_asids == 4)
  74 +               value = (asid & 0x3) << 29;
  75 +       else
  76 +               value = (asid & 0x7f) << 24;
  77 +
  78 +       value |= SMMU_TLB_FLUSH_ASID_MATCH | SMMU_TLB_FLUSH_VA_GROUP(iova);
  79         smmu_writel(smmu, value, SMMU_TLB_FLUSH);
  80  }
  81