queue-5.0/0003-x86-speculation-mds-Add-basic-bug-infrastructure-for.patch

   1 From 85e507546d6f6cc4fd77dbcbffc67cecc7d8428f Mon Sep 17 00:00:00 2001
   2 From: Andi Kleen <ak@linux.intel.com>
   3 Date: Fri, 18 Jan 2019 16:50:16 -0800
   4 Subject: [PATCH 03/27] x86/speculation/mds: Add basic bug infrastructure for
   5  MDS
   6
   7 commit ed5194c2732c8084af9fd159c146ea92bf137128 upstream
   8
   9 Microarchitectural Data Sampling (MDS), is a class of side channel attacks
  10 on internal buffers in Intel CPUs. The variants are:
  11
  12  - Microarchitectural Store Buffer Data Sampling (MSBDS) (CVE-2018-12126)
  13  - Microarchitectural Fill Buffer Data Sampling (MFBDS) (CVE-2018-12130)
  14  - Microarchitectural Load Port Data Sampling (MLPDS) (CVE-2018-12127)
  15
  16 MSBDS leaks Store Buffer Entries which can be speculatively forwarded to a
  17 dependent load (store-to-load forwarding) as an optimization. The forward
  18 can also happen to a faulting or assisting load operation for a different
  19 memory address, which can be exploited under certain conditions. Store
  20 buffers are partitioned between Hyper-Threads so cross thread forwarding is
  21 not possible. But if a thread enters or exits a sleep state the store
  22 buffer is repartitioned which can expose data from one thread to the other.
  23
  24 MFBDS leaks Fill Buffer Entries. Fill buffers are used internally to manage
  25 L1 miss situations and to hold data which is returned or sent in response
  26 to a memory or I/O operation. Fill buffers can forward data to a load
  27 operation and also write data to the cache. When the fill buffer is
  28 deallocated it can retain the stale data of the preceding operations which
  29 can then be forwarded to a faulting or assisting load operation, which can
  30 be exploited under certain conditions. Fill buffers are shared between
  31 Hyper-Threads so cross thread leakage is possible.
  32
  33 MLDPS leaks Load Port Data. Load ports are used to perform load operations
  34 from memory or I/O. The received data is then forwarded to the register
  35 file or a subsequent operation. In some implementations the Load Port can
  36 contain stale data from a previous operation which can be forwarded to
  37 faulting or assisting loads under certain conditions, which again can be
  38 exploited eventually. Load ports are shared between Hyper-Threads so cross
  39 thread leakage is possible.
  40
  41 All variants have the same mitigation for single CPU thread case (SMT off),
  42 so the kernel can treat them as one MDS issue.
  43
  44 Add the basic infrastructure to detect if the current CPU is affected by
  45 MDS.
  46
  47 [ tglx: Rewrote changelog ]
  48
  49 Signed-off-by: Andi Kleen <ak@linux.intel.com>
  50 Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
  51 Reviewed-by: Borislav Petkov <bp@suse.de>
  52 Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
  53 Reviewed-by: Frederic Weisbecker <frederic@kernel.org>
  54 Reviewed-by: Jon Masters <jcm@redhat.com>
  55 Tested-by: Jon Masters <jcm@redhat.com>
  56 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
  57 ---
  58  arch/x86/include/asm/cpufeatures.h |  2 ++
  59  arch/x86/include/asm/msr-index.h   |  5 +++++
  60  arch/x86/kernel/cpu/common.c       | 25 ++++++++++++++++---------
  61  3 files changed, 23 insertions(+), 9 deletions(-)
  62
  63 diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
  64 index 981ff9479648..71375c827f4f 100644
  65 --- a/arch/x86/include/asm/cpufeatures.h
  66 +++ b/arch/x86/include/asm/cpufeatures.h
  67 @@ -344,6 +344,7 @@
  68  /* Intel-defined CPU features, CPUID level 0x00000007:0 (EDX), word 18 */
  69  #define X86_FEATURE_AVX512_4VNNIW      (18*32+ 2) /* AVX-512 Neural Network Instructions */
  70  #define X86_FEATURE_AVX512_4FMAPS      (18*32+ 3) /* AVX-512 Multiply Accumulation Single precision */
  71 +#define X86_FEATURE_MD_CLEAR           (18*32+10) /* VERW clears CPU buffers */
  72  #define X86_FEATURE_TSX_FORCE_ABORT    (18*32+13) /* "" TSX_FORCE_ABORT */
  73  #define X86_FEATURE_PCONFIG            (18*32+18) /* Intel PCONFIG */
  74  #define X86_FEATURE_SPEC_CTRL          (18*32+26) /* "" Speculation Control (IBRS + IBPB) */
  75 @@ -382,5 +383,6 @@
  76  #define X86_BUG_SPECTRE_V2             X86_BUG(16) /* CPU is affected by Spectre variant 2 attack with indirect branches */
  77  #define X86_BUG_SPEC_STORE_BYPASS      X86_BUG(17) /* CPU is affected by speculative store bypass attack */
  78  #define X86_BUG_L1TF                   X86_BUG(18) /* CPU is affected by L1 Terminal Fault */
  79 +#define X86_BUG_MDS                    X86_BUG(19) /* CPU is affected by Microarchitectural data sampling */
  80
  81  #endif /* _ASM_X86_CPUFEATURES_H */
  82 diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
  83 index 4f1e8b28daa0..20f7da552e90 100644
  84 --- a/arch/x86/include/asm/msr-index.h
  85 +++ b/arch/x86/include/asm/msr-index.h
  86 @@ -79,6 +79,11 @@
  87                                                  * attack, so no Speculative Store Bypass
  88                                                  * control required.
  89                                                  */
  90 +#define ARCH_CAP_MDS_NO                        BIT(5)   /*
  91 +                                                 * Not susceptible to
  92 +                                                 * Microarchitectural Data
  93 +                                                 * Sampling (MDS) vulnerabilities.
  94 +                                                 */
  95
  96  #define MSR_IA32_FLUSH_CMD             0x0000010b
  97  #define L1D_FLUSH                      BIT(0)  /*
  98 diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
  99 index 26ec15034f86..e34817bca504 100644
 100 --- a/arch/x86/kernel/cpu/common.c
 101 +++ b/arch/x86/kernel/cpu/common.c
 102 @@ -952,6 +952,7 @@ static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c)
 103  #define NO_MELTDOWN    BIT(1)
 104  #define NO_SSB         BIT(2)
 105  #define NO_L1TF                BIT(3)
 106 +#define NO_MDS         BIT(4)
 107
 108  #define VULNWL(_vendor, _family, _model, _whitelist)   \
 109         { X86_VENDOR_##_vendor, _family, _model, X86_FEATURE_ANY, _whitelist }
 110 @@ -971,6 +972,7 @@ static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = {
 111         VULNWL(INTEL,   5, X86_MODEL_ANY,       NO_SPECULATION),
 112         VULNWL(NSC,     5, X86_MODEL_ANY,       NO_SPECULATION),
 113
 114 +       /* Intel Family 6 */
 115         VULNWL_INTEL(ATOM_SALTWELL,             NO_SPECULATION),
 116         VULNWL_INTEL(ATOM_SALTWELL_TABLET,      NO_SPECULATION),
 117         VULNWL_INTEL(ATOM_SALTWELL_MID,         NO_SPECULATION),
 118 @@ -987,18 +989,20 @@ static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = {
 119         VULNWL_INTEL(CORE_YONAH,                NO_SSB),
 120
 121         VULNWL_INTEL(ATOM_AIRMONT_MID,          NO_L1TF),
 122 -       VULNWL_INTEL(ATOM_GOLDMONT,             NO_L1TF),
 123 -       VULNWL_INTEL(ATOM_GOLDMONT_X,           NO_L1TF),
 124 -       VULNWL_INTEL(ATOM_GOLDMONT_PLUS,        NO_L1TF),
 125
 126 -       VULNWL_AMD(0x0f,                NO_MELTDOWN | NO_SSB | NO_L1TF),
 127 -       VULNWL_AMD(0x10,                NO_MELTDOWN | NO_SSB | NO_L1TF),
 128 -       VULNWL_AMD(0x11,                NO_MELTDOWN | NO_SSB | NO_L1TF),
 129 -       VULNWL_AMD(0x12,                NO_MELTDOWN | NO_SSB | NO_L1TF),
 130 +       VULNWL_INTEL(ATOM_GOLDMONT,             NO_MDS | NO_L1TF),
 131 +       VULNWL_INTEL(ATOM_GOLDMONT_X,           NO_MDS | NO_L1TF),
 132 +       VULNWL_INTEL(ATOM_GOLDMONT_PLUS,        NO_MDS | NO_L1TF),
 133 +
 134 +       /* AMD Family 0xf - 0x12 */
 135 +       VULNWL_AMD(0x0f,        NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS),
 136 +       VULNWL_AMD(0x10,        NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS),
 137 +       VULNWL_AMD(0x11,        NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS),
 138 +       VULNWL_AMD(0x12,        NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS),
 139
 140         /* FAMILY_ANY must be last, otherwise 0x0f - 0x12 matches won't work */
 141 -       VULNWL_AMD(X86_FAMILY_ANY,      NO_MELTDOWN | NO_L1TF),
 142 -       VULNWL_HYGON(X86_FAMILY_ANY,    NO_MELTDOWN | NO_L1TF),
 143 +       VULNWL_AMD(X86_FAMILY_ANY,      NO_MELTDOWN | NO_L1TF | NO_MDS),
 144 +       VULNWL_HYGON(X86_FAMILY_ANY,    NO_MELTDOWN | NO_L1TF | NO_MDS),
 145         {}
 146  };
 147
 148 @@ -1029,6 +1033,9 @@ static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c)
 149         if (ia32_cap & ARCH_CAP_IBRS_ALL)
 150                 setup_force_cpu_cap(X86_FEATURE_IBRS_ENHANCED);
 151
 152 +       if (!cpu_matches(NO_MDS) && !(ia32_cap & ARCH_CAP_MDS_NO))
 153 +               setup_force_cpu_bug(X86_BUG_MDS);
 154 +
 155         if (cpu_matches(NO_MELTDOWN))
 156                 return;
 157
 158 --
 159 2.21.0
 160