queue-5.0/x86-mce-amd-carve-out-the-mc4_misc-thresholding-quirk.patch

   1 From 30aa3d26edb0f3d7992757287eec0ca588a5c259 Mon Sep 17 00:00:00 2001
   2 From: Shirish S <Shirish.S@amd.com>
   3 Date: Wed, 16 Jan 2019 15:10:40 +0000
   4 Subject: x86/MCE/AMD: Carve out the MC4_MISC thresholding quirk
   5
   6 From: Shirish S <Shirish.S@amd.com>
   7
   8 commit 30aa3d26edb0f3d7992757287eec0ca588a5c259 upstream.
   9
  10 The MC4_MISC thresholding quirk needs to be applied during S5 -> S0 and
  11 S3 -> S0 state transitions, which follow different code paths. Carve it
  12 out into a separate function and call it mce_amd_feature_init() where
  13 the two code paths of the state transitions converge.
  14
  15  [ bp: massage commit message and the carved out function. ]
  16
  17 Signed-off-by: Shirish S <shirish.s@amd.com>
  18 Signed-off-by: Borislav Petkov <bp@suse.de>
  19 Cc: "H. Peter Anvin" <hpa@zytor.com>
  20 Cc: Ingo Molnar <mingo@redhat.com>
  21 Cc: Kees Cook <keescook@chromium.org>
  22 Cc: Thomas Gleixner <tglx@linutronix.de>
  23 Cc: Tony Luck <tony.luck@intel.com>
  24 Cc: Vishal Verma <vishal.l.verma@intel.com>
  25 Cc: Yazen Ghannam <yazen.ghannam@amd.com>
  26 Cc: x86-ml <x86@kernel.org>
  27 Link: https://lkml.kernel.org/r/1547651417-23583-3-git-send-email-shirish.s@amd.com
  28 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
  29
  30 ---
  31  arch/x86/kernel/cpu/mce/amd.c  |   36 ++++++++++++++++++++++++++++++++++++
  32  arch/x86/kernel/cpu/mce/core.c |   29 -----------------------------
  33  2 files changed, 36 insertions(+), 29 deletions(-)
  34
  35 --- a/arch/x86/kernel/cpu/mce/amd.c
  36 +++ b/arch/x86/kernel/cpu/mce/amd.c
  37 @@ -545,6 +545,40 @@ out:
  38         return offset;
  39  }
  40
  41 +/*
  42 + * Turn off MC4_MISC thresholding banks on all family 0x15 models since
  43 + * they're not supported there.
  44 + */
  45 +void disable_err_thresholding(struct cpuinfo_x86 *c)
  46 +{
  47 +       int i;
  48 +       u64 hwcr;
  49 +       bool need_toggle;
  50 +       u32 msrs[] = {
  51 +               0x00000413, /* MC4_MISC0 */
  52 +               0xc0000408, /* MC4_MISC1 */
  53 +       };
  54 +
  55 +       if (c->x86 != 0x15)
  56 +               return;
  57 +
  58 +       rdmsrl(MSR_K7_HWCR, hwcr);
  59 +
  60 +       /* McStatusWrEn has to be set */
  61 +       need_toggle = !(hwcr & BIT(18));
  62 +
  63 +       if (need_toggle)
  64 +               wrmsrl(MSR_K7_HWCR, hwcr | BIT(18));
  65 +
  66 +       /* Clear CntP bit safely */
  67 +       for (i = 0; i < ARRAY_SIZE(msrs); i++)
  68 +               msr_clear_bit(msrs[i], 62);
  69 +
  70 +       /* restore old settings */
  71 +       if (need_toggle)
  72 +               wrmsrl(MSR_K7_HWCR, hwcr);
  73 +}
  74 +
  75  /* cpu init entry point, called from mce.c with preempt off */
  76  void mce_amd_feature_init(struct cpuinfo_x86 *c)
  77  {
  78 @@ -552,6 +586,8 @@ void mce_amd_feature_init(struct cpuinfo
  79         unsigned int bank, block, cpu = smp_processor_id();
  80         int offset = -1;
  81
  82 +       disable_err_thresholding(c);
  83 +
  84         for (bank = 0; bank < mca_cfg.banks; ++bank) {
  85                 if (mce_flags.smca)
  86                         smca_configure(bank, cpu);
  87 --- a/arch/x86/kernel/cpu/mce/core.c
  88 +++ b/arch/x86/kernel/cpu/mce/core.c
  89 @@ -1612,35 +1612,6 @@ static int __mcheck_cpu_apply_quirks(str
  90                 if (c->x86 == 0x15 && c->x86_model <= 0xf)
  91                         mce_flags.overflow_recov = 1;
  92
  93 -               /*
  94 -                * Turn off MC4_MISC thresholding banks on all models since
  95 -                * they're not supported there.
  96 -                */
  97 -               if (c->x86 == 0x15) {
  98 -                       int i;
  99 -                       u64 hwcr;
 100 -                       bool need_toggle;
 101 -                       u32 msrs[] = {
 102 -                               0x00000413, /* MC4_MISC0 */
 103 -                               0xc0000408, /* MC4_MISC1 */
 104 -                       };
 105 -
 106 -                       rdmsrl(MSR_K7_HWCR, hwcr);
 107 -
 108 -                       /* McStatusWrEn has to be set */
 109 -                       need_toggle = !(hwcr & BIT(18));
 110 -
 111 -                       if (need_toggle)
 112 -                               wrmsrl(MSR_K7_HWCR, hwcr | BIT(18));
 113 -
 114 -                       /* Clear CntP bit safely */
 115 -                       for (i = 0; i < ARRAY_SIZE(msrs); i++)
 116 -                               msr_clear_bit(msrs[i], 62);
 117 -
 118 -                       /* restore old settings */
 119 -                       if (need_toggle)
 120 -                               wrmsrl(MSR_K7_HWCR, hwcr);
 121 -               }
 122         }
 123
 124         if (c->x86_vendor == X86_VENDOR_INTEL) {