1 From bc9a1ec01289e6e7259dc5030b413a9c6654a99a Mon Sep 17 00:00:00 2001
2 From: Andi Shyti <andi.shyti@linux.intel.com>
3 Date: Thu, 28 Mar 2024 08:34:03 +0100
4 Subject: drm/i915/gt: Disable HW load balancing for CCS
6 From: Andi Shyti <andi.shyti@linux.intel.com>
8 commit bc9a1ec01289e6e7259dc5030b413a9c6654a99a upstream.
10 The hardware should not dynamically balance the load between CCS
11 engines. Wa_14019159160 recommends disabling it across all
14 Fixes: d2eae8e98d59 ("drm/i915/dg2: Drop force_probe requirement")
15 Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
16 Cc: Chris Wilson <chris.p.wilson@linux.intel.com>
17 Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
18 Cc: Matt Roper <matthew.d.roper@intel.com>
19 Cc: <stable@vger.kernel.org> # v6.2+
20 Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
21 Acked-by: Michal Mrozek <michal.mrozek@intel.com>
22 Link: https://patchwork.freedesktop.org/patch/msgid/20240328073409.674098-2-andi.shyti@linux.intel.com
23 (cherry picked from commit f5d2904cf814f20b79e3e4c1b24a4ccc2411b7e0)
24 Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
25 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
27 drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
28 drivers/gpu/drm/i915/gt/intel_workarounds.c | 23 +++++++++++++++++++++--
29 2 files changed, 22 insertions(+), 2 deletions(-)
31 --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
32 +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
34 #define ECOBITS_PPGTT_CACHE4B (0 << 8)
36 #define GEN12_RCU_MODE _MMIO(0x14800)
37 +#define XEHP_RCU_MODE_FIXED_SLICE_CCS_MODE REG_BIT(1)
38 #define GEN12_RCU_MODE_CCS_ENABLE REG_BIT(0)
40 #define CHV_FUSE_GT _MMIO(VLV_GUNIT_BASE + 0x2168)
41 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
42 +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
44 * registers belonging to BCS, VCS or VECS should be implemented in
45 * xcs_engine_wa_init(). Workarounds for registers not belonging to a specific
46 * engine's MMIO range but that are part of of the common RCS/CCS reset domain
47 - * should be implemented in general_render_compute_wa_init().
48 + * should be implemented in general_render_compute_wa_init(). The settings
49 + * about the CCS load balancing should be added in ccs_engine_wa_mode().
51 * - GT workarounds: the list of these WAs is applied whenever these registers
52 * revert to their default values: on GPU reset, suspend/resume [1]_, etc.
53 @@ -2823,6 +2824,22 @@ add_render_compute_tuning_settings(struc
54 wa_write_clr(wal, GEN8_GARBCNTL, GEN12_BUS_HASH_CTL_BIT_EXC);
57 +static void ccs_engine_wa_mode(struct intel_engine_cs *engine, struct i915_wa_list *wal)
59 + struct intel_gt *gt = engine->gt;
61 + if (!IS_DG2(gt->i915))
65 + * Wa_14019159160: This workaround, along with others, leads to
66 + * significant challenges in utilizing load balancing among the
67 + * CCS slices. Consequently, an architectural decision has been
68 + * made to completely disable automatic CCS load balancing.
70 + wa_masked_en(wal, GEN12_RCU_MODE, XEHP_RCU_MODE_FIXED_SLICE_CCS_MODE);
74 * The workarounds in this function apply to shared registers in
75 * the general render reset domain that aren't tied to a
76 @@ -2970,8 +2987,10 @@ engine_init_workarounds(struct intel_eng
77 * to a single RCS/CCS engine's workaround list since
78 * they're reset as part of the general render domain reset.
80 - if (engine->flags & I915_ENGINE_FIRST_RENDER_COMPUTE)
81 + if (engine->flags & I915_ENGINE_FIRST_RENDER_COMPUTE) {
82 general_render_compute_wa_init(engine, wal);
83 + ccs_engine_wa_mode(engine, wal);
86 if (engine->class == COMPUTE_CLASS)
87 ccs_engine_wa_init(engine, wal);