queue-6.6/drm-i915-gt-enable-only-one-ccs-for-compute-workload.patch

   1 From 6db31251bb265813994bfb104eb4b4d0f44d64fb Mon Sep 17 00:00:00 2001
   2 From: Andi Shyti <andi.shyti@linux.intel.com>
   3 Date: Thu, 28 Mar 2024 08:34:05 +0100
   4 Subject: drm/i915/gt: Enable only one CCS for compute workload
   5
   6 From: Andi Shyti <andi.shyti@linux.intel.com>
   7
   8 commit 6db31251bb265813994bfb104eb4b4d0f44d64fb upstream.
   9
  10 Enable only one CCS engine by default with all the compute sices
  11 allocated to it.
  12
  13 While generating the list of UABI engines to be exposed to the
  14 user, exclude any additional CCS engines beyond the first
  15 instance.
  16
  17 This change can be tested with igt i915_query.
  18
  19 Fixes: d2eae8e98d59 ("drm/i915/dg2: Drop force_probe requirement")
  20 Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
  21 Cc: Chris Wilson <chris.p.wilson@linux.intel.com>
  22 Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
  23 Cc: Matt Roper <matthew.d.roper@intel.com>
  24 Cc: <stable@vger.kernel.org> # v6.2+
  25 Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
  26 Acked-by: Michal Mrozek <michal.mrozek@intel.com>
  27 Link: https://patchwork.freedesktop.org/patch/msgid/20240328073409.674098-4-andi.shyti@linux.intel.com
  28 (cherry picked from commit 2bebae0112b117de7e8a7289277a4bd2403b9e17)
  29 Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
  30 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
  31 ---
  32  drivers/gpu/drm/i915/Makefile               |    1
  33  drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c |   39 ++++++++++++++++++++++++++++
  34  drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h |   13 +++++++++
  35  drivers/gpu/drm/i915/gt/intel_gt_regs.h     |    5 +++
  36  drivers/gpu/drm/i915/gt/intel_workarounds.c |    7 +++++
  37  5 files changed, 65 insertions(+)
  38  create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c
  39  create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h
  40
  41 --- a/drivers/gpu/drm/i915/Makefile
  42 +++ b/drivers/gpu/drm/i915/Makefile
  43 @@ -104,6 +104,7 @@ gt-y += \
  44         gt/intel_ggtt_fencing.o \
  45         gt/intel_gt.o \
  46         gt/intel_gt_buffer_pool.o \
  47 +       gt/intel_gt_ccs_mode.o \
  48         gt/intel_gt_clock_utils.o \
  49         gt/intel_gt_debugfs.o \
  50         gt/intel_gt_engines_debugfs.o \
  51 --- /dev/null
  52 +++ b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c
  53 @@ -0,0 +1,39 @@
  54 +// SPDX-License-Identifier: MIT
  55 +/*
  56 + * Copyright © 2024 Intel Corporation
  57 + */
  58 +
  59 +#include "i915_drv.h"
  60 +#include "intel_gt.h"
  61 +#include "intel_gt_ccs_mode.h"
  62 +#include "intel_gt_regs.h"
  63 +
  64 +void intel_gt_apply_ccs_mode(struct intel_gt *gt)
  65 +{
  66 +       int cslice;
  67 +       u32 mode = 0;
  68 +       int first_ccs = __ffs(CCS_MASK(gt));
  69 +
  70 +       if (!IS_DG2(gt->i915))
  71 +               return;
  72 +
  73 +       /* Build the value for the fixed CCS load balancing */
  74 +       for (cslice = 0; cslice < I915_MAX_CCS; cslice++) {
  75 +               if (CCS_MASK(gt) & BIT(cslice))
  76 +                       /*
  77 +                        * If available, assign the cslice
  78 +                        * to the first available engine...
  79 +                        */
  80 +                       mode |= XEHP_CCS_MODE_CSLICE(cslice, first_ccs);
  81 +
  82 +               else
  83 +                       /*
  84 +                        * ... otherwise, mark the cslice as
  85 +                        * unavailable if no CCS dispatches here
  86 +                        */
  87 +                       mode |= XEHP_CCS_MODE_CSLICE(cslice,
  88 +                                                    XEHP_CCS_MODE_CSLICE_MASK);
  89 +       }
  90 +
  91 +       intel_uncore_write(gt->uncore, XEHP_CCS_MODE, mode);
  92 +}
  93 --- /dev/null
  94 +++ b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h
  95 @@ -0,0 +1,13 @@
  96 +/* SPDX-License-Identifier: MIT */
  97 +/*
  98 + * Copyright © 2024 Intel Corporation
  99 + */
 100 +
 101 +#ifndef __INTEL_GT_CCS_MODE_H__
 102 +#define __INTEL_GT_CCS_MODE_H__
 103 +
 104 +struct intel_gt;
 105 +
 106 +void intel_gt_apply_ccs_mode(struct intel_gt *gt);
 107 +
 108 +#endif /* __INTEL_GT_CCS_MODE_H__ */
 109 --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
 110 +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
 111 @@ -1471,6 +1471,11 @@
 112  #define   XEHP_RCU_MODE_FIXED_SLICE_CCS_MODE   REG_BIT(1)
 113  #define   GEN12_RCU_MODE_CCS_ENABLE            REG_BIT(0)
 114
 115 +#define XEHP_CCS_MODE                          _MMIO(0x14804)
 116 +#define   XEHP_CCS_MODE_CSLICE_MASK            REG_GENMASK(2, 0) /* CCS0-3 + rsvd */
 117 +#define   XEHP_CCS_MODE_CSLICE_WIDTH           ilog2(XEHP_CCS_MODE_CSLICE_MASK + 1)
 118 +#define   XEHP_CCS_MODE_CSLICE(cslice, ccs)    (ccs << (cslice * XEHP_CCS_MODE_CSLICE_WIDTH))
 119 +
 120  #define CHV_FUSE_GT                            _MMIO(VLV_GUNIT_BASE + 0x2168)
 121  #define   CHV_FGT_DISABLE_SS0                  (1 << 10)
 122  #define   CHV_FGT_DISABLE_SS1                  (1 << 11)
 123 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
 124 +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
 125 @@ -10,6 +10,7 @@
 126  #include "intel_engine_regs.h"
 127  #include "intel_gpu_commands.h"
 128  #include "intel_gt.h"
 129 +#include "intel_gt_ccs_mode.h"
 130  #include "intel_gt_mcr.h"
 131  #include "intel_gt_regs.h"
 132  #include "intel_ring.h"
 133 @@ -2838,6 +2839,12 @@ static void ccs_engine_wa_mode(struct in
 134          * made to completely disable automatic CCS load balancing.
 135          */
 136         wa_masked_en(wal, GEN12_RCU_MODE, XEHP_RCU_MODE_FIXED_SLICE_CCS_MODE);
 137 +
 138 +       /*
 139 +        * After having disabled automatic load balancing we need to
 140 +        * assign all slices to a single CCS. We will call it CCS mode 1
 141 +        */
 142 +       intel_gt_apply_ccs_mode(gt);
 143  }
 144
 145  /*