queue-6.6/drm-i915-mtl-update-workaround-14018575942.patch

   1 From cb9cf56909d46edc86a0b60e3fe816bf1ef97ebc Mon Sep 17 00:00:00 2001
   2 From: Sasha Levin <sashal@kernel.org>
   3 Date: Wed, 28 Feb 2024 16:07:38 +0530
   4 Subject: drm/i915/mtl: Update workaround 14018575942
   5
   6 From: Tejas Upadhyay <tejas.upadhyay@intel.com>
   7
   8 [ Upstream commit 186bce682772e7346bf7ced5325b5f4ff050ccfb ]
   9
  10 Applying WA 14018575942 only on Compute engine has impact on
  11 some apps like chrome. Updating this WA to apply on Render
  12 engine as well as it is helping with performance on Chrome.
  13
  14 Note: There is no concern from media team thus not applying
  15 WA on media engines. We will revisit if any issues reported
  16 from media team.
  17
  18 V2(Matt):
  19  - Use correct WA number
  20
  21 Fixes: 668f37e1ee11 ("drm/i915/mtl: Update workaround 14018778641")
  22 Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
  23 Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
  24 Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
  25 Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
  26 Link: https://patchwork.freedesktop.org/patch/msgid/20240228103738.2018458-1-tejas.upadhyay@intel.com
  27 (cherry picked from commit 71271280175aa0ed6673e40cce7c01296bcd05f6)
  28 Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
  29 Signed-off-by: Sasha Levin <sashal@kernel.org>
  30 ---
  31  drivers/gpu/drm/i915/gt/intel_workarounds.c | 1 +
  32  1 file changed, 1 insertion(+)
  33
  34 diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
  35 index 37b2b0440923f..0ea52f77b4c72 100644
  36 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
  37 +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
  38 @@ -1644,6 +1644,7 @@ static void
  39  xelpg_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
  40  {
  41         /* Wa_14018575942 / Wa_18018781329 */
  42 +       wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB);
  43         wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB);
  44
  45         /* Wa_22016670082 */
  46 --
  47 2.43.0
  48