queue-6.6/drm-i915-xelpg-extend-some-workarounds-tuning-to-gfx.patch

   1 From 1af0cdb70b1c060acd34e53cf0e46659d803b02a Mon Sep 17 00:00:00 2001
   2 From: Sasha Levin <sashal@kernel.org>
   3 Date: Mon, 8 Jan 2024 17:57:38 +0530
   4 Subject: drm/i915/xelpg: Extend some workarounds/tuning to gfx version 12.74
   5
   6 From: Matt Roper <matthew.d.roper@intel.com>
   7
   8 [ Upstream commit c44d4ef47fdad0a33966de89f9064e19736bb52f ]
   9
  10 Some of our existing Xe_LPG workarounds and tuning are also applicable
  11 to the version 12.74 variant.  Extend the condition bounds accordingly.
  12 Also fix the comment on Wa_14018575942 while we're at it.
  13
  14 v2: Extend some more workarounds (Harish)
  15
  16 Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
  17 Signed-off-by: Harish Chegondi <harish.chegondi@intel.com>
  18 Signed-off-by: Haridhar Kalvala <haridhar.kalvala@intel.com>
  19 Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
  20 Link: https://patchwork.freedesktop.org/patch/msgid/20240108122738.14399-4-haridhar.kalvala@intel.com
  21 Stable-dep-of: 186bce682772 ("drm/i915/mtl: Update workaround 14018575942")
  22 Signed-off-by: Sasha Levin <sashal@kernel.org>
  23 ---
  24  drivers/gpu/drm/i915/gt/gen8_engine_cs.c    |  4 ++--
  25  drivers/gpu/drm/i915/gt/intel_workarounds.c | 24 +++++++++++++--------
  26  drivers/gpu/drm/i915/i915_perf.c            |  2 +-
  27  3 files changed, 18 insertions(+), 12 deletions(-)
  28
  29 diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
  30 index ba4c2422b3402..cddf8c16e9a72 100644
  31 --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
  32 +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
  33 @@ -226,7 +226,7 @@ u32 *gen12_emit_aux_table_inv(struct intel_engine_cs *engine, u32 *cs)
  34  static int mtl_dummy_pipe_control(struct i915_request *rq)
  35  {
  36         /* Wa_14016712196 */
  37 -       if (IS_GFX_GT_IP_RANGE(rq->engine->gt, IP_VER(12, 70), IP_VER(12, 71)) ||
  38 +       if (IS_GFX_GT_IP_RANGE(rq->engine->gt, IP_VER(12, 70), IP_VER(12, 74)) ||
  39             IS_DG2(rq->i915)) {
  40                 u32 *cs;
  41
  42 @@ -819,7 +819,7 @@ u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
  43                      PIPE_CONTROL_FLUSH_ENABLE);
  44
  45         /* Wa_14016712196 */
  46 -       if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71)) || IS_DG2(i915))
  47 +       if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 74)) || IS_DG2(i915))
  48                 /* dummy PIPE_CONTROL + depth flush */
  49                 cs = gen12_emit_pipe_control(cs, 0,
  50                                              PIPE_CONTROL_DEPTH_CACHE_FLUSH, 0);
  51 diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
  52 index b6237e999be93..37b2b0440923f 100644
  53 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
  54 +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
  55 @@ -788,8 +788,13 @@ static void xelpg_ctx_gt_tuning_init(struct intel_engine_cs *engine,
  56
  57         dg2_ctx_gt_tuning_init(engine, wal);
  58
  59 -       if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_B0, STEP_FOREVER) ||
  60 -           IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_B0, STEP_FOREVER))
  61 +       /*
  62 +        * Due to Wa_16014892111, the DRAW_WATERMARK tuning must be done in
  63 +        * gen12_emit_indirect_ctx_rcs() rather than here on some early
  64 +        * steppings.
  65 +        */
  66 +       if (!(IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
  67 +             IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0)))
  68                 wa_add(wal, DRAW_WATERMARK, VERT_WM_VAL, 0x3FF, 0, false);
  69  }
  70
  71 @@ -907,7 +912,7 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
  72         if (engine->class != RENDER_CLASS)
  73                 goto done;
  74
  75 -       if (IS_GFX_GT_IP_RANGE(engine->gt, IP_VER(12, 70), IP_VER(12, 71)))
  76 +       if (IS_GFX_GT_IP_RANGE(engine->gt, IP_VER(12, 70), IP_VER(12, 74)))
  77                 xelpg_ctx_workarounds_init(engine, wal);
  78         else if (IS_PONTEVECCHIO(i915))
  79                 ; /* noop; none at this time */
  80 @@ -1638,7 +1643,7 @@ pvc_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
  81  static void
  82  xelpg_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
  83  {
  84 -       /* Wa_14018778641 / Wa_18018781329 */
  85 +       /* Wa_14018575942 / Wa_18018781329 */
  86         wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB);
  87
  88         /* Wa_22016670082 */
  89 @@ -1688,7 +1693,7 @@ xelpmp_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
  90   */
  91  static void gt_tuning_settings(struct intel_gt *gt, struct i915_wa_list *wal)
  92  {
  93 -       if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71))) {
  94 +       if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 74))) {
  95                 wa_mcr_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS);
  96                 wa_mcr_write_or(wal, XEHP_SQCM, EN_32B_ACCESS);
  97         }
  98 @@ -1721,7 +1726,7 @@ gt_init_workarounds(struct intel_gt *gt, struct i915_wa_list *wal)
  99                 return;
 100         }
 101
 102 -       if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71)))
 103 +       if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 74)))
 104                 xelpg_gt_workarounds_init(gt, wal);
 105         else if (IS_PONTEVECCHIO(i915))
 106                 pvc_gt_workarounds_init(gt, wal);
 107 @@ -2194,7 +2199,7 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine)
 108
 109         if (engine->gt->type == GT_MEDIA)
 110                 ; /* none yet */
 111 -       else if (IS_GFX_GT_IP_RANGE(engine->gt, IP_VER(12, 70), IP_VER(12, 71)))
 112 +       else if (IS_GFX_GT_IP_RANGE(engine->gt, IP_VER(12, 70), IP_VER(12, 74)))
 113                 xelpg_whitelist_build(engine);
 114         else if (IS_PONTEVECCHIO(i915))
 115                 pvc_whitelist_build(engine);
 116 @@ -2801,7 +2806,7 @@ add_render_compute_tuning_settings(struct intel_gt *gt,
 117  {
 118         struct drm_i915_private *i915 = gt->i915;
 119
 120 -       if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71)) || IS_DG2(i915))
 121 +       if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 74)) || IS_DG2(i915))
 122                 wa_mcr_write_clr_set(wal, RT_CTRL, STACKID_CTRL, STACKID_CTRL_512);
 123
 124         /*
 125 @@ -2854,7 +2859,8 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
 126         }
 127
 128         if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_B0, STEP_FOREVER) ||
 129 -           IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_B0, STEP_FOREVER))
 130 +           IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_B0, STEP_FOREVER) ||
 131 +           IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 74), IP_VER(12, 74)))
 132                 /* Wa_14017856879 */
 133                 wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN3, MTL_DISABLE_FIX_FOR_EOT_FLUSH);
 134
 135 diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
 136 index 48ea17b49b3a0..3f90403d86cb4 100644
 137 --- a/drivers/gpu/drm/i915/i915_perf.c
 138 +++ b/drivers/gpu/drm/i915/i915_perf.c
 139 @@ -3258,7 +3258,7 @@ u32 i915_perf_oa_timestamp_frequency(struct drm_i915_private *i915)
 140         struct intel_gt *gt = to_gt(i915);
 141
 142         /* Wa_18013179988 */
 143 -       if (IS_DG2(i915) || IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71))) {
 144 +       if (IS_DG2(i915) || IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 74))) {
 145                 intel_wakeref_t wakeref;
 146                 u32 reg, shift;
 147
 148 --
 149 2.43.0
 150