queue-6.6/net-lan743x-add-set-rfe-read-fifo-threshold-for-pci1.patch

   1 From 6d74a63c024e3f4cdef05223e4d223af2c757b8c Mon Sep 17 00:00:00 2001
   2 From: Sasha Levin <sashal@kernel.org>
   3 Date: Tue, 26 Mar 2024 12:28:05 +0530
   4 Subject: net: lan743x: Add set RFE read fifo threshold for PCI1x1x chips
   5
   6 From: Raju Lakkaraju <Raju.Lakkaraju@microchip.com>
   7
   8 [ Upstream commit e4a58989f5c839316ac63675e8800b9eed7dbe96 ]
   9
  10 PCI11x1x Rev B0 devices might drop packets when receiving back to back frames
  11 at 2.5G link speed. Change the B0 Rev device's Receive filtering Engine FIFO
  12 threshold parameter from its hardware default of 4 to 3 dwords to prevent the
  13 problem. Rev C0 and later hardware already defaults to 3 dwords.
  14
  15 Fixes: bb4f6bffe33c ("net: lan743x: Add PCI11010 / PCI11414 device IDs")
  16 Signed-off-by: Raju Lakkaraju <Raju.Lakkaraju@microchip.com>
  17 Reviewed-by: Simon Horman <horms@kernel.org>
  18 Link: https://lore.kernel.org/r/20240326065805.686128-1-Raju.Lakkaraju@microchip.com
  19 Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  20 Signed-off-by: Sasha Levin <sashal@kernel.org>
  21 ---
  22  drivers/net/ethernet/microchip/lan743x_main.c | 18 ++++++++++++++++++
  23  drivers/net/ethernet/microchip/lan743x_main.h |  4 ++++
  24  2 files changed, 22 insertions(+)
  25
  26 diff --git a/drivers/net/ethernet/microchip/lan743x_main.c b/drivers/net/ethernet/microchip/lan743x_main.c
  27 index c81cdeb4d4e7e..0b6174748d2b4 100644
  28 --- a/drivers/net/ethernet/microchip/lan743x_main.c
  29 +++ b/drivers/net/ethernet/microchip/lan743x_main.c
  30 @@ -25,6 +25,8 @@
  31  #define PCS_POWER_STATE_DOWN   0x6
  32  #define PCS_POWER_STATE_UP     0x4
  33
  34 +#define RFE_RD_FIFO_TH_3_DWORDS        0x3
  35 +
  36  static void pci11x1x_strap_get_status(struct lan743x_adapter *adapter)
  37  {
  38         u32 chip_rev;
  39 @@ -3223,6 +3225,21 @@ static void lan743x_full_cleanup(struct lan743x_adapter *adapter)
  40         lan743x_pci_cleanup(adapter);
  41  }
  42
  43 +static void pci11x1x_set_rfe_rd_fifo_threshold(struct lan743x_adapter *adapter)
  44 +{
  45 +       u16 rev = adapter->csr.id_rev & ID_REV_CHIP_REV_MASK_;
  46 +
  47 +       if (rev == ID_REV_CHIP_REV_PCI11X1X_B0_) {
  48 +               u32 misc_ctl;
  49 +
  50 +               misc_ctl = lan743x_csr_read(adapter, MISC_CTL_0);
  51 +               misc_ctl &= ~MISC_CTL_0_RFE_READ_FIFO_MASK_;
  52 +               misc_ctl |= FIELD_PREP(MISC_CTL_0_RFE_READ_FIFO_MASK_,
  53 +                                      RFE_RD_FIFO_TH_3_DWORDS);
  54 +               lan743x_csr_write(adapter, MISC_CTL_0, misc_ctl);
  55 +       }
  56 +}
  57 +
  58  static int lan743x_hardware_init(struct lan743x_adapter *adapter,
  59                                  struct pci_dev *pdev)
  60  {
  61 @@ -3238,6 +3255,7 @@ static int lan743x_hardware_init(struct lan743x_adapter *adapter,
  62                 pci11x1x_strap_get_status(adapter);
  63                 spin_lock_init(&adapter->eth_syslock_spinlock);
  64                 mutex_init(&adapter->sgmii_rw_lock);
  65 +               pci11x1x_set_rfe_rd_fifo_threshold(adapter);
  66         } else {
  67                 adapter->max_tx_channels = LAN743X_MAX_TX_CHANNELS;
  68                 adapter->used_tx_channels = LAN743X_USED_TX_CHANNELS;
  69 diff --git a/drivers/net/ethernet/microchip/lan743x_main.h b/drivers/net/ethernet/microchip/lan743x_main.h
  70 index 52609fc13ad95..f0b486f85450e 100644
  71 --- a/drivers/net/ethernet/microchip/lan743x_main.h
  72 +++ b/drivers/net/ethernet/microchip/lan743x_main.h
  73 @@ -26,6 +26,7 @@
  74  #define ID_REV_CHIP_REV_MASK_          (0x0000FFFF)
  75  #define ID_REV_CHIP_REV_A0_            (0x00000000)
  76  #define ID_REV_CHIP_REV_B0_            (0x00000010)
  77 +#define ID_REV_CHIP_REV_PCI11X1X_B0_   (0x000000B0)
  78
  79  #define FPGA_REV                       (0x04)
  80  #define FPGA_REV_GET_MINOR_(fpga_rev)  (((fpga_rev) >> 8) & 0x000000FF)
  81 @@ -311,6 +312,9 @@
  82  #define SGMII_CTL_LINK_STATUS_SOURCE_  BIT(8)
  83  #define SGMII_CTL_SGMII_POWER_DN_      BIT(1)
  84
  85 +#define MISC_CTL_0                     (0x920)
  86 +#define MISC_CTL_0_RFE_READ_FIFO_MASK_ GENMASK(6, 4)
  87 +
  88  /* Vendor Specific SGMII MMD details */
  89  #define SR_VSMMD_PCS_ID1               0x0004
  90  #define SR_VSMMD_PCS_ID2               0x0005
  91 --
  92 2.43.0
  93