1 From ffb6b40bbab6f6805ba28ebc111da405c2cebaa0 Mon Sep 17 00:00:00 2001
2 From: Sasha Levin <sashal@kernel.org>
3 Date: Tue, 31 Oct 2023 23:30:59 +0100
4 Subject: x86/CPU/AMD: Add ZenX generations flags
6 From: Borislav Petkov (AMD) <bp@alien8.de>
8 [ Upstream commit 30fa92832f405d5ac9f263e99f62445fa3084008 ]
10 Add X86_FEATURE flags for each Zen generation. They should be used from
11 now on instead of checking f/m/s.
13 Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
14 Reviewed-by: Nikolay Borisov <nik.borisov@suse.com>
15 Acked-by: Thomas Gleixner <tglx@linutronix.de>
16 Link: http://lore.kernel.org/r/20231120104152.13740-2-bp@alien8.de
17 Stable-dep-of: c7b2edd8377b ("perf/x86/amd/core: Update and fix stalled-cycles-* events for Zen 2 and later")
18 Signed-off-by: Sasha Levin <sashal@kernel.org>
20 arch/x86/include/asm/cpufeatures.h | 5 ++-
21 arch/x86/kernel/cpu/amd.c | 70 +++++++++++++++++++++++++++++-
22 2 files changed, 72 insertions(+), 3 deletions(-)
24 diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
25 index bd33f6366c80d..1f9db287165ac 100644
26 --- a/arch/x86/include/asm/cpufeatures.h
27 +++ b/arch/x86/include/asm/cpufeatures.h
29 #define X86_FEATURE_IBRS ( 7*32+25) /* Indirect Branch Restricted Speculation */
30 #define X86_FEATURE_IBPB ( 7*32+26) /* Indirect Branch Prediction Barrier */
31 #define X86_FEATURE_STIBP ( 7*32+27) /* Single Thread Indirect Branch Predictors */
32 -#define X86_FEATURE_ZEN (7*32+28) /* "" CPU based on Zen microarchitecture */
33 +#define X86_FEATURE_ZEN ( 7*32+28) /* "" CPU based on Zen microarchitecture */
34 #define X86_FEATURE_L1TF_PTEINV ( 7*32+29) /* "" L1TF workaround PTE inversion */
35 #define X86_FEATURE_IBRS_ENHANCED ( 7*32+30) /* Enhanced IBRS */
36 #define X86_FEATURE_MSR_IA32_FEAT_CTL ( 7*32+31) /* "" MSR IA32_FEAT_CTL configured */
38 #define X86_FEATURE_SRSO_ALIAS (11*32+25) /* "" AMD BTB untrain RETs through aliasing */
39 #define X86_FEATURE_IBPB_ON_VMEXIT (11*32+26) /* "" Issue an IBPB only on VMEXIT */
40 #define X86_FEATURE_APIC_MSRS_FENCE (11*32+27) /* "" IA32_TSC_DEADLINE and X2APIC MSRs need fencing */
41 +#define X86_FEATURE_ZEN2 (11*32+28) /* "" CPU based on Zen2 microarchitecture */
42 +#define X86_FEATURE_ZEN3 (11*32+29) /* "" CPU based on Zen3 microarchitecture */
43 +#define X86_FEATURE_ZEN4 (11*32+30) /* "" CPU based on Zen4 microarchitecture */
45 /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */
46 #define X86_FEATURE_AVX_VNNI (12*32+ 4) /* AVX VNNI instructions */
47 diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
48 index 031bca974fbf3..5391385707b3f 100644
49 --- a/arch/x86/kernel/cpu/amd.c
50 +++ b/arch/x86/kernel/cpu/amd.c
51 @@ -620,6 +620,49 @@ static void bsp_init_amd(struct cpuinfo_x86 *c)
54 resctrl_cpu_detect(c);
56 + /* Figure out Zen generations: */
59 + switch (c->x86_model) {
62 + setup_force_cpu_cap(X86_FEATURE_ZEN);
68 + setup_force_cpu_cap(X86_FEATURE_ZEN2);
76 + switch (c->x86_model) {
79 + setup_force_cpu_cap(X86_FEATURE_ZEN3);
83 + setup_force_cpu_cap(X86_FEATURE_ZEN4);
97 + WARN_ONCE(1, "Family 0x%x, model: 0x%x??\n", c->x86, c->x86_model);
100 static void early_detect_mem_encrypt(struct cpuinfo_x86 *c)
101 @@ -978,8 +1021,6 @@ void init_spectral_chicken(struct cpuinfo_x86 *c)
103 static void init_amd_zn(struct cpuinfo_x86 *c)
105 - set_cpu_cap(c, X86_FEATURE_ZEN);
108 node_reclaim_distance = 32;
110 @@ -1042,6 +1083,22 @@ static void zenbleed_check(struct cpuinfo_x86 *c)
114 +static void init_amd_zen(struct cpuinfo_x86 *c)
118 +static void init_amd_zen2(struct cpuinfo_x86 *c)
122 +static void init_amd_zen3(struct cpuinfo_x86 *c)
126 +static void init_amd_zen4(struct cpuinfo_x86 *c)
130 static void init_amd(struct cpuinfo_x86 *c)
133 @@ -1080,6 +1137,15 @@ static void init_amd(struct cpuinfo_x86 *c)
134 case 0x19: init_amd_zn(c); break;
137 + if (boot_cpu_has(X86_FEATURE_ZEN))
139 + else if (boot_cpu_has(X86_FEATURE_ZEN2))
141 + else if (boot_cpu_has(X86_FEATURE_ZEN3))
143 + else if (boot_cpu_has(X86_FEATURE_ZEN4))
147 * Enable workaround for FXSAVE leak on CPUs
148 * without a XSaveErPtr feature