releases/2.6.20.14/sparc64-fix-_page_exec_4u-check-in-sun4u-i-tlb-miss-handler.patch

   1 From stable-bounces@linux.kernel.org  Wed Jun  6 22:56:08 2007
   2 Date: Wed, 06 Jun 2007 22:56:19 -0700 (PDT)
   3 Message-Id: <20070606.225619.91314293.davem@davemloft.net>
   4 To: stable@kernel.org
   5 From: David Miller <davem@davemloft.net>
   6 Cc: bunk@stusta.de
   7 Subject: SPARC64: Fix _PAGE_EXEC_4U check in sun4u I-TLB miss handler.
   8
   9 It was using an immediate _PAGE_EXEC_4U value in an 'and'
  10 instruction to perform the test.  This doesn't work because
  11 the immediate field is signed 13-bit, this the mask being
  12 tested against the PTE was 0x1000 sign-extended to 32-bits
  13 instead of just plain 0x1000.
  14
  15 Signed-off-by: David S. Miller <davem@davemloft.net>
  16 Signed-off-by: Chris Wright <chrisw@sous-sol.org>
  17
  18 ---
  19  arch/sparc64/kernel/itlb_miss.S |    4 ++--
  20  1 file changed, 2 insertions(+), 2 deletions(-)
  21
  22 --- linux-2.6.20.13.orig/arch/sparc64/kernel/itlb_miss.S
  23 +++ linux-2.6.20.13/arch/sparc64/kernel/itlb_miss.S
  24 @@ -11,12 +11,12 @@
  25  /* ITLB ** ICACHE line 2: TSB compare and TLB load     */
  26         bne,pn  %xcc, tsb_miss_itlb             ! Miss
  27          mov    FAULT_CODE_ITLB, %g3
  28 -       andcc   %g5, _PAGE_EXEC_4U, %g0         ! Executable?
  29 +       sethi   %hi(_PAGE_EXEC_4U), %g4
  30 +       andcc   %g5, %g4, %g0                   ! Executable?
  31         be,pn   %xcc, tsb_do_fault
  32          nop                                    ! Delay slot, fill me
  33         stxa    %g5, [%g0] ASI_ITLB_DATA_IN     ! Load TLB
  34         retry                                   ! Trap done
  35 -       nop
  36
  37  /* ITLB ** ICACHE line 3:                              */
  38         nop