releases/2.6.32.12/0004-KVM-allow-bit-10-to-be-cleared-in-MSR_IA32_MC4_CTL.patch

   1 From 5e2da0660782ef33de03e9da84f64223730500d1 Mon Sep 17 00:00:00 2001
   2 From: Andre Przywara <andre.przywara@amd.com>
   3 Date: Wed, 24 Mar 2010 17:46:42 +0100
   4 Subject: KVM: allow bit 10 to be cleared in MSR_IA32_MC4_CTL
   5
   6 From: Andre Przywara <andre.przywara@amd.com>
   7
   8 (Cherry-picked from commit 114be429c8cd44e57f312af2bbd6734e5a185b0d)
   9
  10 There is a quirk for AMD K8 CPUs in many Linux kernels (see
  11 arch/x86/kernel/cpu/mcheck/mce.c:__mcheck_cpu_apply_quirks()) that
  12 clears bit 10 in that MCE related MSR. KVM can only cope with all
  13 zeros or all ones, so it will inject a #GP into the guest, which
  14 will let it panic.
  15 So lets add a quirk to the quirk and ignore this single cleared bit.
  16 This fixes -cpu kvm64 on all machines and -cpu host on K8 machines
  17 with some guest Linux kernels.
  18
  19 Signed-off-by: Andre Przywara <andre.przywara@amd.com>
  20 Signed-off-by: Avi Kivity <avi@redhat.com>
  21 Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
  22
  23 ---
  24  arch/x86/kvm/x86.c |    8 ++++++--
  25  1 file changed, 6 insertions(+), 2 deletions(-)
  26
  27 --- a/arch/x86/kvm/x86.c
  28 +++ b/arch/x86/kvm/x86.c
  29 @@ -799,9 +799,13 @@ static int set_msr_mce(struct kvm_vcpu *
  30                 if (msr >= MSR_IA32_MC0_CTL &&
  31                     msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
  32                         u32 offset = msr - MSR_IA32_MC0_CTL;
  33 -                       /* only 0 or all 1s can be written to IA32_MCi_CTL */
  34 +                       /* only 0 or all 1s can be written to IA32_MCi_CTL
  35 +                        * some Linux kernels though clear bit 10 in bank 4 to
  36 +                        * workaround a BIOS/GART TBL issue on AMD K8s, ignore
  37 +                        * this to avoid an uncatched #GP in the guest
  38 +                        */
  39                         if ((offset & 0x3) == 0 &&
  40 -                           data != 0 && data != ~(u64)0)
  41 +                           data != 0 && (data | (1 << 10)) != ~(u64)0)
  42                                 return -1;
  43                         vcpu->arch.mce_banks[offset] = data;
  44                         break;