releases/2.6.32.12/drm-radeon-kms-fix-pal-tv-out-support-on-legacy-igp-chips.patch

   1 From 15f7207761cfcf8f53fb6e5cacffe060478782c3 Mon Sep 17 00:00:00 2001
   2 From: Alex Deucher <alexdeucher@gmail.com>
   3 Date: Wed, 10 Mar 2010 18:33:03 -0500
   4 Subject: drm/radeon/kms: fix pal tv-out support on legacy IGP chips
   5
   6 From: Alex Deucher <alexdeucher@gmail.com>
   7
   8 commit 15f7207761cfcf8f53fb6e5cacffe060478782c3 upstream.
   9
  10 Based on ddx patch by Andrzej Hajda.
  11
  12 Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
  13 Signed-off-by: Dave Airlie <airlied@redhat.com>
  14 Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
  15
  16 ---
  17  drivers/gpu/drm/radeon/radeon_legacy_tv.c |   29 ++++++++++++++++++++++++-----
  18  1 file changed, 24 insertions(+), 5 deletions(-)
  19
  20 --- a/drivers/gpu/drm/radeon/radeon_legacy_tv.c
  21 +++ b/drivers/gpu/drm/radeon/radeon_legacy_tv.c
  22 @@ -57,6 +57,10 @@
  23  #define NTSC_TV_PLL_N_14 693
  24  #define NTSC_TV_PLL_P_14 7
  25
  26 +#define PAL_TV_PLL_M_14 19
  27 +#define PAL_TV_PLL_N_14 353
  28 +#define PAL_TV_PLL_P_14 5
  29 +
  30  #define VERT_LEAD_IN_LINES 2
  31  #define FRAC_BITS 0xe
  32  #define FRAC_MASK 0x3fff
  33 @@ -205,9 +209,24 @@ static const struct radeon_tv_mode_const
  34                 630627,             /* defRestart */
  35                 347,                /* crtcPLL_N */
  36                 14,                 /* crtcPLL_M */
  37 -                       8,                  /* crtcPLL_postDiv */
  38 +               8,                  /* crtcPLL_postDiv */
  39                 1022,               /* pixToTV */
  40         },
  41 +       { /* PAL timing for 14 Mhz ref clk */
  42 +               800,                /* horResolution */
  43 +               600,                /* verResolution */
  44 +               TV_STD_PAL,         /* standard */
  45 +               1131,               /* horTotal */
  46 +               742,                /* verTotal */
  47 +               813,                /* horStart */
  48 +               840,                /* horSyncStart */
  49 +               633,                /* verSyncStart */
  50 +               708369,             /* defRestart */
  51 +               211,                /* crtcPLL_N */
  52 +               9,                  /* crtcPLL_M */
  53 +               8,                  /* crtcPLL_postDiv */
  54 +               759,                /* pixToTV */
  55 +       },
  56  };
  57
  58  #define N_AVAILABLE_MODES ARRAY_SIZE(available_tv_modes)
  59 @@ -242,7 +261,7 @@ static const struct radeon_tv_mode_const
  60                 if (pll->reference_freq == 2700)
  61                         const_ptr = &available_tv_modes[1];
  62                 else
  63 -                       const_ptr = &available_tv_modes[1]; /* FIX ME */
  64 +                       const_ptr = &available_tv_modes[3];
  65         }
  66         return const_ptr;
  67  }
  68 @@ -685,9 +704,9 @@ void radeon_legacy_tv_mode_set(struct dr
  69                         n = PAL_TV_PLL_N_27;
  70                         p = PAL_TV_PLL_P_27;
  71                 } else {
  72 -                       m = PAL_TV_PLL_M_27;
  73 -                       n = PAL_TV_PLL_N_27;
  74 -                       p = PAL_TV_PLL_P_27;
  75 +                       m = PAL_TV_PLL_M_14;
  76 +                       n = PAL_TV_PLL_N_14;
  77 +                       p = PAL_TV_PLL_P_14;
  78                 }
  79         }
  80