releases/2.6.32.17/drm-i915-define-mi_arb_state-bits.patch

   1 From 45503ded966c98e604c9667c0b458d40666b9ef3 Mon Sep 17 00:00:00 2001
   2 From: Keith Packard <keithp@keithp.com>
   3 Date: Mon, 19 Jul 2010 21:12:35 -0700
   4 Subject: drm/i915: Define MI_ARB_STATE bits
   5
   6 From: Keith Packard <keithp@keithp.com>
   7
   8 commit 45503ded966c98e604c9667c0b458d40666b9ef3 upstream.
   9
  10 The i915 memory arbiter has a register full of configuration
  11 bits which are currently not defined in the driver header file.
  12
  13 Signed-off-by: Keith Packard <keithp@keithp.com>
  14 Signed-off-by: Dave Airlie <airlied@redhat.com>
  15 Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
  16
  17 ---
  18  drivers/gpu/drm/i915/i915_reg.h |   64 ++++++++++++++++++++++++++++++++++++++++
  19  1 file changed, 64 insertions(+)
  20
  21 --- a/drivers/gpu/drm/i915/i915_reg.h
  22 +++ b/drivers/gpu/drm/i915/i915_reg.h
  23 @@ -307,6 +307,70 @@
  24  #define LM_BURST_LENGTH     0x00000700
  25  #define LM_FIFO_WATERMARK   0x0000001F
  26  #define MI_ARB_STATE   0x020e4 /* 915+ only */
  27 +#define   MI_ARB_MASK_SHIFT      16    /* shift for enable bits */
  28 +
  29 +/* Make render/texture TLB fetches lower priorty than associated data
  30 + *   fetches. This is not turned on by default
  31 + */
  32 +#define   MI_ARB_RENDER_TLB_LOW_PRIORITY       (1 << 15)
  33 +
  34 +/* Isoch request wait on GTT enable (Display A/B/C streams).
  35 + * Make isoch requests stall on the TLB update. May cause
  36 + * display underruns (test mode only)
  37 + */
  38 +#define   MI_ARB_ISOCH_WAIT_GTT                        (1 << 14)
  39 +
  40 +/* Block grant count for isoch requests when block count is
  41 + * set to a finite value.
  42 + */
  43 +#define   MI_ARB_BLOCK_GRANT_MASK              (3 << 12)
  44 +#define   MI_ARB_BLOCK_GRANT_8                 (0 << 12)       /* for 3 display planes */
  45 +#define   MI_ARB_BLOCK_GRANT_4                 (1 << 12)       /* for 2 display planes */
  46 +#define   MI_ARB_BLOCK_GRANT_2                 (2 << 12)       /* for 1 display plane */
  47 +#define   MI_ARB_BLOCK_GRANT_0                 (3 << 12)       /* don't use */
  48 +
  49 +/* Enable render writes to complete in C2/C3/C4 power states.
  50 + * If this isn't enabled, render writes are prevented in low
  51 + * power states. That seems bad to me.
  52 + */
  53 +#define   MI_ARB_C3_LP_WRITE_ENABLE            (1 << 11)
  54 +
  55 +/* This acknowledges an async flip immediately instead
  56 + * of waiting for 2TLB fetches.
  57 + */
  58 +#define   MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE      (1 << 10)
  59 +
  60 +/* Enables non-sequential data reads through arbiter
  61 + */
  62 +#define   MI_ARB_DUAL_DATA_PHASE_DISABLE               (1 << 9)
  63 +
  64 +/* Disable FSB snooping of cacheable write cycles from binner/render
  65 + * command stream
  66 + */
  67 +#define   MI_ARB_CACHE_SNOOP_DISABLE           (1 << 8)
  68 +
  69 +/* Arbiter time slice for non-isoch streams */
  70 +#define   MI_ARB_TIME_SLICE_MASK               (7 << 5)
  71 +#define   MI_ARB_TIME_SLICE_1                  (0 << 5)
  72 +#define   MI_ARB_TIME_SLICE_2                  (1 << 5)
  73 +#define   MI_ARB_TIME_SLICE_4                  (2 << 5)
  74 +#define   MI_ARB_TIME_SLICE_6                  (3 << 5)
  75 +#define   MI_ARB_TIME_SLICE_8                  (4 << 5)
  76 +#define   MI_ARB_TIME_SLICE_10                 (5 << 5)
  77 +#define   MI_ARB_TIME_SLICE_14                 (6 << 5)
  78 +#define   MI_ARB_TIME_SLICE_16                 (7 << 5)
  79 +
  80 +/* Low priority grace period page size */
  81 +#define   MI_ARB_LOW_PRIORITY_GRACE_4KB                (0 << 4)        /* default */
  82 +#define   MI_ARB_LOW_PRIORITY_GRACE_8KB                (1 << 4)
  83 +
  84 +/* Disable display A/B trickle feed */
  85 +#define   MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE  (1 << 2)
  86 +
  87 +/* Set display plane priority */
  88 +#define   MI_ARB_DISPLAY_PRIORITY_A_B          (0 << 0)        /* display A > display B */
  89 +#define   MI_ARB_DISPLAY_PRIORITY_B_A          (1 << 0)        /* display B > display A */
  90 +
  91  #define CACHE_MODE_0   0x02120 /* 915+ only */
  92  #define   CM0_MASK_SHIFT          16
  93  #define   CM0_IZ_OPT_DISABLE      (1<<6)