releases/2.6.35.8/agp-intel-fix-cache-control-for-sandybridge.patch

   1 From f8f235e5bbf4e61f3e0886a44afb1dc4cfe8f337 Mon Sep 17 00:00:00 2001
   2 From: Zhenyu Wang <zhenyuw@linux.intel.com>
   3 Date: Fri, 27 Aug 2010 11:08:57 +0800
   4 Subject: agp/intel: Fix cache control for Sandybridge
   5
   6 From: Zhenyu Wang <zhenyuw@linux.intel.com>
   7
   8 commit f8f235e5bbf4e61f3e0886a44afb1dc4cfe8f337 upstream.
   9
  10 Sandybridge GTT has new cache control bits in PTE, which controls
  11 graphics page cache in LLC or LLC/MLC, so we need to extend the mask
  12 function to respect the new bits.
  13
  14 And set cache control to always LLC only by default on Gen6.
  15
  16 Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
  17 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
  18 Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
  19
  20
  21 ---
  22  drivers/char/agp/intel-agp.c    |    1
  23  drivers/char/agp/intel-agp.h    |    6 ++++
  24  drivers/char/agp/intel-gtt.c    |   50 ++++++++++++++++++++++++++++++++--------
  25  drivers/gpu/drm/i915/i915_gem.c |    1
  26  include/linux/intel-gtt.h       |   20 ++++++++++++++++
  27  5 files changed, 68 insertions(+), 10 deletions(-)
  28
  29 --- a/drivers/char/agp/intel-agp.c
  30 +++ b/drivers/char/agp/intel-agp.c
  31 @@ -12,6 +12,7 @@
  32  #include <asm/smp.h>
  33  #include "agp.h"
  34  #include "intel-agp.h"
  35 +#include <linux/intel-gtt.h>
  36
  37  #include "intel-gtt.c"
  38
  39 --- a/drivers/char/agp/intel-agp.h
  40 +++ b/drivers/char/agp/intel-agp.h
  41 @@ -60,6 +60,12 @@
  42  #define I810_PTE_LOCAL         0x00000002
  43  #define I810_PTE_VALID         0x00000001
  44  #define I830_PTE_SYSTEM_CACHED  0x00000006
  45 +/* GT PTE cache control fields */
  46 +#define GEN6_PTE_UNCACHED      0x00000002
  47 +#define GEN6_PTE_LLC           0x00000004
  48 +#define GEN6_PTE_LLC_MLC       0x00000006
  49 +#define GEN6_PTE_GFDT          0x00000008
  50 +
  51  #define I810_SMRAM_MISCC       0x70
  52  #define I810_GFX_MEM_WIN_SIZE  0x00010000
  53  #define I810_GFX_MEM_WIN_32M   0x00010000
  54 --- a/drivers/char/agp/intel-gtt.c
  55 +++ b/drivers/char/agp/intel-gtt.c
  56 @@ -49,6 +49,26 @@ static struct gatt_mask intel_i810_masks
  57          .type = INTEL_AGP_CACHED_MEMORY}
  58  };
  59
  60 +#define INTEL_AGP_UNCACHED_MEMORY              0
  61 +#define INTEL_AGP_CACHED_MEMORY_LLC            1
  62 +#define INTEL_AGP_CACHED_MEMORY_LLC_GFDT       2
  63 +#define INTEL_AGP_CACHED_MEMORY_LLC_MLC        3
  64 +#define INTEL_AGP_CACHED_MEMORY_LLC_MLC_GFDT   4
  65 +
  66 +static struct gatt_mask intel_gen6_masks[] =
  67 +{
  68 +       {.mask = I810_PTE_VALID | GEN6_PTE_UNCACHED,
  69 +        .type = INTEL_AGP_UNCACHED_MEMORY },
  70 +       {.mask = I810_PTE_VALID | GEN6_PTE_LLC,
  71 +         .type = INTEL_AGP_CACHED_MEMORY_LLC },
  72 +       {.mask = I810_PTE_VALID | GEN6_PTE_LLC | GEN6_PTE_GFDT,
  73 +         .type = INTEL_AGP_CACHED_MEMORY_LLC_GFDT },
  74 +       {.mask = I810_PTE_VALID | GEN6_PTE_LLC_MLC,
  75 +         .type = INTEL_AGP_CACHED_MEMORY_LLC_MLC },
  76 +       {.mask = I810_PTE_VALID | GEN6_PTE_LLC_MLC | GEN6_PTE_GFDT,
  77 +         .type = INTEL_AGP_CACHED_MEMORY_LLC_MLC_GFDT },
  78 +};
  79 +
  80  static struct _intel_private {
  81         struct pci_dev *pcidev; /* device one */
  82         u8 __iomem *registers;
  83 @@ -175,13 +195,6 @@ static void intel_agp_insert_sg_entries(
  84                                         off_t pg_start, int mask_type)
  85  {
  86         int i, j;
  87 -       u32 cache_bits = 0;
  88 -
  89 -       if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB ||
  90 -           agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB)
  91 -       {
  92 -               cache_bits = I830_PTE_SYSTEM_CACHED;
  93 -       }
  94
  95         for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
  96                 writel(agp_bridge->driver->mask_memory(agp_bridge,
  97 @@ -314,6 +327,23 @@ static int intel_i830_type_to_mask_type(
  98                 return 0;
  99  }
 100
 101 +static int intel_gen6_type_to_mask_type(struct agp_bridge_data *bridge,
 102 +                                       int type)
 103 +{
 104 +       unsigned int type_mask = type & ~AGP_USER_CACHED_MEMORY_GFDT;
 105 +       unsigned int gfdt = type & AGP_USER_CACHED_MEMORY_GFDT;
 106 +
 107 +       if (type_mask == AGP_USER_UNCACHED_MEMORY)
 108 +               return INTEL_AGP_UNCACHED_MEMORY;
 109 +       else if (type_mask == AGP_USER_CACHED_MEMORY_LLC_MLC)
 110 +               return gfdt ? INTEL_AGP_CACHED_MEMORY_LLC_MLC_GFDT :
 111 +                             INTEL_AGP_CACHED_MEMORY_LLC_MLC;
 112 +       else /* set 'normal'/'cached' to LLC by default */
 113 +               return gfdt ? INTEL_AGP_CACHED_MEMORY_LLC_GFDT :
 114 +                             INTEL_AGP_CACHED_MEMORY_LLC;
 115 +}
 116 +
 117 +
 118  static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start,
 119                                 int type)
 120  {
 121 @@ -1155,7 +1185,7 @@ static int intel_i915_insert_entries(str
 122
 123         mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
 124
 125 -       if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&
 126 +       if (!IS_SNB && mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&
 127             mask_type != INTEL_AGP_CACHED_MEMORY)
 128                 goto out_err;
 129
 130 @@ -1546,7 +1576,7 @@ static const struct agp_bridge_driver in
 131         .fetch_size             = intel_i9xx_fetch_size,
 132         .cleanup                = intel_i915_cleanup,
 133         .mask_memory            = intel_gen6_mask_memory,
 134 -       .masks                  = intel_i810_masks,
 135 +       .masks                  = intel_gen6_masks,
 136         .agp_enable             = intel_i810_agp_enable,
 137         .cache_flush            = global_cache_flush,
 138         .create_gatt_table      = intel_i965_create_gatt_table,
 139 @@ -1559,7 +1589,7 @@ static const struct agp_bridge_driver in
 140         .agp_alloc_pages        = agp_generic_alloc_pages,
 141         .agp_destroy_page       = agp_generic_destroy_page,
 142         .agp_destroy_pages      = agp_generic_destroy_pages,
 143 -       .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
 144 +       .agp_type_to_mask_type  = intel_gen6_type_to_mask_type,
 145         .chipset_flush          = intel_i915_chipset_flush,
 146  #ifdef USE_PCI_DMA_API
 147         .agp_map_page           = intel_agp_map_page,
 148 --- a/drivers/gpu/drm/i915/i915_gem.c
 149 +++ b/drivers/gpu/drm/i915/i915_gem.c
 150 @@ -34,6 +34,7 @@
 151  #include <linux/slab.h>
 152  #include <linux/swap.h>
 153  #include <linux/pci.h>
 154 +#include <linux/intel-gtt.h>
 155
 156  static void i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj);
 157  static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj);
 158 --- /dev/null
 159 +++ b/include/linux/intel-gtt.h
 160 @@ -0,0 +1,20 @@
 161 +/*
 162 + * Common Intel AGPGART and GTT definitions.
 163 + */
 164 +#ifndef _INTEL_GTT_H
 165 +#define _INTEL_GTT_H
 166 +
 167 +#include <linux/agp_backend.h>
 168 +
 169 +/* This is for Intel only GTT controls.
 170 + *
 171 + * Sandybridge: AGP_USER_CACHED_MEMORY default to LLC only
 172 + */
 173 +
 174 +#define AGP_USER_CACHED_MEMORY_LLC_MLC (AGP_USER_TYPES + 2)
 175 +#define AGP_USER_UNCACHED_MEMORY (AGP_USER_TYPES + 4)
 176 +
 177 +/* flag for GFDT type */
 178 +#define AGP_USER_CACHED_MEMORY_GFDT (1 << 3)
 179 +
 180 +#endif