releases/3.0.1/asoc-davinci-fix-codec-start-and-stop-functions.patch

   1 From 3012f43eaf7592d8121426918e43e3b5db013aff Mon Sep 17 00:00:00 2001
   2 From: "Rajashekhara, Sudhakar" <sudhakar.raj@ti.com>
   3 Date: Wed, 20 Jul 2011 17:36:04 +0530
   4 Subject: ASoC: davinci: fix codec start and stop functions
   5
   6 From: "Rajashekhara, Sudhakar" <sudhakar.raj@ti.com>
   7
   8 commit 3012f43eaf7592d8121426918e43e3b5db013aff upstream.
   9
  10 According to DM365 voice codec data sheet at [1], before starting
  11 recording or playback, ADC/DAC modules should follow a reset and
  12 enable cycle. Writing a 1 to the ADC/DAC bit in the register resets
  13 the module and clearing the bit to 0 will enable the module. But the
  14 driver seems to be doing the reverse of it.
  15
  16 [1] http://focus.ti.com/lit/ug/sprufi9b/sprufi9b.pdf
  17
  18 Signed-off-by: Rajashekhara, Sudhakar <sudhakar.raj@ti.com>
  19 Acked-by: Liam Girdwood <lrg@ti.com>
  20 Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
  21 Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
  22
  23 ---
  24  sound/soc/davinci/davinci-vcif.c |    8 ++++----
  25  1 file changed, 4 insertions(+), 4 deletions(-)
  26
  27 --- a/sound/soc/davinci/davinci-vcif.c
  28 +++ b/sound/soc/davinci/davinci-vcif.c
  29 @@ -62,9 +62,9 @@ static void davinci_vcif_start(struct sn
  30         w = readl(davinci_vc->base + DAVINCI_VC_CTRL);
  31
  32         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  33 -               MOD_REG_BIT(w, DAVINCI_VC_CTRL_RSTDAC, 1);
  34 +               MOD_REG_BIT(w, DAVINCI_VC_CTRL_RSTDAC, 0);
  35         else
  36 -               MOD_REG_BIT(w, DAVINCI_VC_CTRL_RSTADC, 1);
  37 +               MOD_REG_BIT(w, DAVINCI_VC_CTRL_RSTADC, 0);
  38
  39         writel(w, davinci_vc->base + DAVINCI_VC_CTRL);
  40  }
  41 @@ -80,9 +80,9 @@ static void davinci_vcif_stop(struct snd
  42         /* Reset transmitter/receiver and sample rate/frame sync generators */
  43         w = readl(davinci_vc->base + DAVINCI_VC_CTRL);
  44         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  45 -               MOD_REG_BIT(w, DAVINCI_VC_CTRL_RSTDAC, 0);
  46 +               MOD_REG_BIT(w, DAVINCI_VC_CTRL_RSTDAC, 1);
  47         else
  48 -               MOD_REG_BIT(w, DAVINCI_VC_CTRL_RSTADC, 0);
  49 +               MOD_REG_BIT(w, DAVINCI_VC_CTRL_RSTADC, 1);
  50
  51         writel(w, davinci_vc->base + DAVINCI_VC_CTRL);
  52  }