releases/3.10.30/drm-radeon-set-the-full-cache-bit-for-fences-on-r7xx.patch

   1 From d45b964a22cad962d3ede1eba8d24f5cee7b2a92 Mon Sep 17 00:00:00 2001
   2 From: Alex Deucher <alexander.deucher@amd.com>
   3 Date: Thu, 16 Jan 2014 18:11:47 -0500
   4 Subject: drm/radeon: set the full cache bit for fences on r7xx+
   5
   6 From: Alex Deucher <alexander.deucher@amd.com>
   7
   8 commit d45b964a22cad962d3ede1eba8d24f5cee7b2a92 upstream.
   9
  10 Needed to properly flush the read caches for fences.
  11
  12 Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
  13 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
  14
  15 ---
  16  drivers/gpu/drm/radeon/r600.c  |   13 +++++++------
  17  drivers/gpu/drm/radeon/r600d.h |    1 +
  18  2 files changed, 8 insertions(+), 6 deletions(-)
  19
  20 --- a/drivers/gpu/drm/radeon/r600.c
  21 +++ b/drivers/gpu/drm/radeon/r600.c
  22 @@ -2957,14 +2957,17 @@ void r600_fence_ring_emit(struct radeon_
  23                           struct radeon_fence *fence)
  24  {
  25         struct radeon_ring *ring = &rdev->ring[fence->ring];
  26 +       u32 cp_coher_cntl = PACKET3_TC_ACTION_ENA | PACKET3_VC_ACTION_ENA |
  27 +               PACKET3_SH_ACTION_ENA;
  28 +
  29 +       if (rdev->family >= CHIP_RV770)
  30 +               cp_coher_cntl |= PACKET3_FULL_CACHE_ENA;
  31
  32         if (rdev->wb.use_event) {
  33                 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
  34                 /* flush read cache over gart */
  35                 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
  36 -               radeon_ring_write(ring, PACKET3_TC_ACTION_ENA |
  37 -                                       PACKET3_VC_ACTION_ENA |
  38 -                                       PACKET3_SH_ACTION_ENA);
  39 +               radeon_ring_write(ring, cp_coher_cntl);
  40                 radeon_ring_write(ring, 0xFFFFFFFF);
  41                 radeon_ring_write(ring, 0);
  42                 radeon_ring_write(ring, 10); /* poll interval */
  43 @@ -2978,9 +2981,7 @@ void r600_fence_ring_emit(struct radeon_
  44         } else {
  45                 /* flush read cache over gart */
  46                 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
  47 -               radeon_ring_write(ring, PACKET3_TC_ACTION_ENA |
  48 -                                       PACKET3_VC_ACTION_ENA |
  49 -                                       PACKET3_SH_ACTION_ENA);
  50 +               radeon_ring_write(ring, cp_coher_cntl);
  51                 radeon_ring_write(ring, 0xFFFFFFFF);
  52                 radeon_ring_write(ring, 0);
  53                 radeon_ring_write(ring, 10); /* poll interval */
  54 --- a/drivers/gpu/drm/radeon/r600d.h
  55 +++ b/drivers/gpu/drm/radeon/r600d.h
  56 @@ -1283,6 +1283,7 @@
  57  #              define PACKET3_CP_DMA_CMD_DAIC      (1 << 29)
  58  #define        PACKET3_SURFACE_SYNC                            0x43
  59  #              define PACKET3_CB0_DEST_BASE_ENA    (1 << 6)
  60 +#              define PACKET3_FULL_CACHE_ENA       (1 << 20) /* r7xx+ only */
  61  #              define PACKET3_TC_ACTION_ENA        (1 << 23)
  62  #              define PACKET3_VC_ACTION_ENA        (1 << 24)
  63  #              define PACKET3_CB_ACTION_ENA        (1 << 25)