releases/3.14.36/clk-sunxi-support-factor-clocks-with-n-factor-starting-not-from-0.patch

   1 From 9a5e6c7eb5ccbb5f0d3a1dffce135f0a727f40e1 Mon Sep 17 00:00:00 2001
   2 From: Chen-Yu Tsai <wens@csie.org>
   3 Date: Thu, 26 Jun 2014 23:55:41 +0800
   4 Subject: clk: sunxi: Support factor clocks with N factor starting not from 0
   5
   6 From: Chen-Yu Tsai <wens@csie.org>
   7
   8 commit 9a5e6c7eb5ccbb5f0d3a1dffce135f0a727f40e1 upstream.
   9
  10 The PLLs on newer Allwinner SoC's, such as the A31 and A23, have a
  11 N multiplier factor that starts from 1, not 0.
  12
  13 This patch adds an option to the factor clk driver's config data
  14 structures to specify the base value of N.
  15
  16 Signed-off-by: Chen-Yu Tsai <wens@csie.org>
  17 Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
  18 Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
  19 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
  20
  21 ---
  22  drivers/clk/sunxi/clk-factors.c |    2 +-
  23  drivers/clk/sunxi/clk-factors.h |    1 +
  24  2 files changed, 2 insertions(+), 1 deletion(-)
  25
  26 --- a/drivers/clk/sunxi/clk-factors.c
  27 +++ b/drivers/clk/sunxi/clk-factors.c
  28 @@ -62,7 +62,7 @@ static unsigned long clk_factors_recalc_
  29                 p = FACTOR_GET(config->pshift, config->pwidth, reg);
  30
  31         /* Calculate the rate */
  32 -       rate = (parent_rate * n * (k + 1) >> p) / (m + 1);
  33 +       rate = (parent_rate * (n + config->n_start) * (k + 1) >> p) / (m + 1);
  34
  35         return rate;
  36  }
  37 --- a/drivers/clk/sunxi/clk-factors.h
  38 +++ b/drivers/clk/sunxi/clk-factors.h
  39 @@ -15,6 +15,7 @@ struct clk_factors_config {
  40         u8 mwidth;
  41         u8 pshift;
  42         u8 pwidth;
  43 +       u8 n_start;
  44  };
  45
  46  struct clk_factors {