releases/3.14.36/drm-radeon-only-enable-kv-kb-dpm-interrupts-once-v3.patch

   1 From 410af8d7285a0b96314845c75c39fd612b755688 Mon Sep 17 00:00:00 2001
   2 From: Alex Deucher <alexander.deucher@amd.com>
   3 Date: Fri, 6 Feb 2015 12:53:27 -0500
   4 Subject: drm/radeon: only enable kv/kb dpm interrupts once v3
   5 MIME-Version: 1.0
   6 Content-Type: text/plain; charset=UTF-8
   7 Content-Transfer-Encoding: 8bit
   8
   9 From: Alex Deucher <alexander.deucher@amd.com>
  10
  11 commit 410af8d7285a0b96314845c75c39fd612b755688 upstream.
  12
  13 Enable at init and disable on fini. Workaround for hardware problems.
  14
  15 v2 (chk): extend commit message
  16 v3: add new function
  17
  18 Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
  19 Signed-off-by: Christian König <christian.koenig@amd.com> (v2)
  20 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
  21
  22 ---
  23  drivers/gpu/drm/radeon/cik.c    |   21 ---------------------
  24  drivers/gpu/drm/radeon/kv_dpm.c |   17 +++++++++++++++--
  25  2 files changed, 15 insertions(+), 23 deletions(-)
  26
  27 --- a/drivers/gpu/drm/radeon/cik.c
  28 +++ b/drivers/gpu/drm/radeon/cik.c
  29 @@ -6809,7 +6809,6 @@ int cik_irq_set(struct radeon_device *rd
  30         u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6;
  31         u32 grbm_int_cntl = 0;
  32         u32 dma_cntl, dma_cntl1;
  33 -       u32 thermal_int;
  34
  35         if (!rdev->irq.installed) {
  36                 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
  37 @@ -6846,13 +6845,6 @@ int cik_irq_set(struct radeon_device *rd
  38         cp_m2p2 = RREG32(CP_ME2_PIPE2_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;
  39         cp_m2p3 = RREG32(CP_ME2_PIPE3_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;
  40
  41 -       if (rdev->flags & RADEON_IS_IGP)
  42 -               thermal_int = RREG32_SMC(CG_THERMAL_INT_CTRL) &
  43 -                       ~(THERM_INTH_MASK | THERM_INTL_MASK);
  44 -       else
  45 -               thermal_int = RREG32_SMC(CG_THERMAL_INT) &
  46 -                       ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
  47 -
  48         /* enable CP interrupts on all rings */
  49         if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
  50                 DRM_DEBUG("cik_irq_set: sw int gfx\n");
  51 @@ -7010,14 +7002,6 @@ int cik_irq_set(struct radeon_device *rd
  52                 hpd6 |= DC_HPDx_INT_EN;
  53         }
  54
  55 -       if (rdev->irq.dpm_thermal) {
  56 -               DRM_DEBUG("dpm thermal\n");
  57 -               if (rdev->flags & RADEON_IS_IGP)
  58 -                       thermal_int |= THERM_INTH_MASK | THERM_INTL_MASK;
  59 -               else
  60 -                       thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW;
  61 -       }
  62 -
  63         WREG32(CP_INT_CNTL_RING0, cp_int_cntl);
  64
  65         WREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET, dma_cntl);
  66 @@ -7071,11 +7055,6 @@ int cik_irq_set(struct radeon_device *rd
  67         WREG32(DC_HPD5_INT_CONTROL, hpd5);
  68         WREG32(DC_HPD6_INT_CONTROL, hpd6);
  69
  70 -       if (rdev->flags & RADEON_IS_IGP)
  71 -               WREG32_SMC(CG_THERMAL_INT_CTRL, thermal_int);
  72 -       else
  73 -               WREG32_SMC(CG_THERMAL_INT, thermal_int);
  74 -
  75         return 0;
  76  }
  77
  78 --- a/drivers/gpu/drm/radeon/kv_dpm.c
  79 +++ b/drivers/gpu/drm/radeon/kv_dpm.c
  80 @@ -1121,6 +1121,19 @@ void kv_dpm_enable_bapm(struct radeon_de
  81         }
  82  }
  83
  84 +static void kv_enable_thermal_int(struct radeon_device *rdev, bool enable)
  85 +{
  86 +       u32 thermal_int;
  87 +
  88 +       thermal_int = RREG32_SMC(CG_THERMAL_INT_CTRL);
  89 +       if (enable)
  90 +               thermal_int |= THERM_INTH_MASK | THERM_INTL_MASK;
  91 +       else
  92 +               thermal_int &= ~(THERM_INTH_MASK | THERM_INTL_MASK);
  93 +       WREG32_SMC(CG_THERMAL_INT_CTRL, thermal_int);
  94 +
  95 +}
  96 +
  97  int kv_dpm_enable(struct radeon_device *rdev)
  98  {
  99         struct kv_power_info *pi = kv_get_pi(rdev);
 100 @@ -1232,8 +1245,7 @@ int kv_dpm_late_enable(struct radeon_dev
 101                         DRM_ERROR("kv_set_thermal_temperature_range failed\n");
 102                         return ret;
 103                 }
 104 -               rdev->irq.dpm_thermal = true;
 105 -               radeon_irq_set(rdev);
 106 +               kv_enable_thermal_int(rdev, true);
 107         }
 108
 109         /* powerdown unused blocks for now */
 110 @@ -1261,6 +1273,7 @@ void kv_dpm_disable(struct radeon_device
 111         kv_stop_dpm(rdev);
 112         kv_enable_ulv(rdev, false);
 113         kv_reset_am(rdev);
 114 +       kv_enable_thermal_int(rdev, false);
 115
 116         kv_update_current_ps(rdev, rdev->pm.dpm.boot_ps);
 117  }