releases/4.14.24/tg3-add-workaround-to-restrict-5762-mrrs-to-2048.patch

   1 From foo@baz Wed Feb 28 16:23:28 CET 2018
   2 From: Siva Reddy Kallam <siva.kallam@broadcom.com>
   3 Date: Fri, 22 Dec 2017 16:05:28 +0530
   4 Subject: tg3: Add workaround to restrict 5762 MRRS to 2048
   5
   6 From: Siva Reddy Kallam <siva.kallam@broadcom.com>
   7
   8
   9 [ Upstream commit 4419bb1cedcda0272e1dc410345c5a1d1da0e367 ]
  10
  11 One of AMD based server with 5762 hangs with jumbo frame traffic.
  12 This AMD platform has southbridge limitation which is restricting MRRS
  13 to 4000. As a work around, driver to restricts the MRRS to 2048 for
  14 this particular 5762 NX1 card.
  15
  16 Signed-off-by: Siva Reddy Kallam <siva.kallam@broadcom.com>
  17 Signed-off-by: Michael Chan <michael.chan@broadcom.com>
  18 Signed-off-by: David S. Miller <davem@davemloft.net>
  19 Signed-off-by: Sasha Levin <alexander.levin@verizon.com>
  20 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
  21 ---
  22  drivers/net/ethernet/broadcom/tg3.c |   10 ++++++++++
  23  drivers/net/ethernet/broadcom/tg3.h |    4 ++++
  24  2 files changed, 14 insertions(+)
  25
  26 --- a/drivers/net/ethernet/broadcom/tg3.c
  27 +++ b/drivers/net/ethernet/broadcom/tg3.c
  28 @@ -10052,6 +10052,16 @@ static int tg3_reset_hw(struct tg3 *tp,
  29
  30         tw32(GRC_MODE, tp->grc_mode | val);
  31
  32 +       /* On one of the AMD platform, MRRS is restricted to 4000 because of
  33 +        * south bridge limitation. As a workaround, Driver is setting MRRS
  34 +        * to 2048 instead of default 4096.
  35 +        */
  36 +       if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
  37 +           tp->pdev->subsystem_device == TG3PCI_SUBDEVICE_ID_DELL_5762) {
  38 +               val = tr32(TG3PCI_DEV_STATUS_CTRL) & ~MAX_READ_REQ_MASK;
  39 +               tw32(TG3PCI_DEV_STATUS_CTRL, val | MAX_READ_REQ_SIZE_2048);
  40 +       }
  41 +
  42         /* Setup the timer prescalar register.  Clock is always 66Mhz. */
  43         val = tr32(GRC_MISC_CFG);
  44         val &= ~0xff;
  45 --- a/drivers/net/ethernet/broadcom/tg3.h
  46 +++ b/drivers/net/ethernet/broadcom/tg3.h
  47 @@ -96,6 +96,7 @@
  48  #define TG3PCI_SUBDEVICE_ID_DELL_JAGUAR                0x0106
  49  #define TG3PCI_SUBDEVICE_ID_DELL_MERLOT                0x0109
  50  #define TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT   0x010a
  51 +#define TG3PCI_SUBDEVICE_ID_DELL_5762          0x07f0
  52  #define TG3PCI_SUBVENDOR_ID_COMPAQ             PCI_VENDOR_ID_COMPAQ
  53  #define TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE     0x007c
  54  #define TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2   0x009a
  55 @@ -281,6 +282,9 @@
  56  #define TG3PCI_STD_RING_PROD_IDX       0x00000098 /* 64-bit */
  57  #define TG3PCI_RCV_RET_RING_CON_IDX    0x000000a0 /* 64-bit */
  58  /* 0xa8 --> 0xb8 unused */
  59 +#define TG3PCI_DEV_STATUS_CTRL         0x000000b4
  60 +#define  MAX_READ_REQ_SIZE_2048                 0x00004000
  61 +#define  MAX_READ_REQ_MASK              0x00007000
  62  #define TG3PCI_DUAL_MAC_CTRL           0x000000b8
  63  #define  DUAL_MAC_CTRL_CH_MASK          0x00000003
  64  #define  DUAL_MAC_CTRL_ID               0x00000004