releases/4.14.53/mfd-intel-lpss-fix-intel-cannon-lake-lpss-i2c-input-clock.patch

   1 From 4e93a658576ab115977225c9d0992b97ff19ba8c Mon Sep 17 00:00:00 2001
   2 From: Jarkko Nikula <jarkko.nikula@linux.intel.com>
   3 Date: Fri, 18 May 2018 11:38:27 +0300
   4 Subject: mfd: intel-lpss: Fix Intel Cannon Lake LPSS I2C input clock
   5
   6 From: Jarkko Nikula <jarkko.nikula@linux.intel.com>
   7
   8 commit 4e93a658576ab115977225c9d0992b97ff19ba8c upstream.
   9
  10 Intel Cannon Lake PCH has much higher 216 MHz input clock to LPSS I2C
  11 than Sunrisepoint which uses 120 MHz. Preliminary information was that
  12 both share the same clock rate but actual silicon implements elevated
  13 rate for better support for 3.4 MHz high-speed I2C.
  14
  15 This incorrect input clock rate results too high I2C bus clock in case
  16 ACPI doesn't provide tuned I2C timing parameters since I2C host
  17 controller driver calculates them from input clock rate.
  18
  19 Fix this by using the correct rate. We still share the same 230 ns SDA
  20 hold time value than Sunrisepoint.
  21
  22 Cc: stable@vger.kernel.org
  23 Fixes: b418bbff36dd ("mfd: intel-lpss: Add Intel Cannonlake PCI IDs")
  24 Reported-by: Jian-Hong Pan <jian-hong@endlessm.com>
  25 Reported-by: Chris Chiu <chiu@endlessm.com>
  26 Reported-by: Daniel Drake <drake@endlessm.com>
  27 Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
  28 Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
  29 Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
  30 Tested-by: Jian-Hong Pan <jian-hong@endlessm.com>
  31 Signed-off-by: Lee Jones <lee.jones@linaro.org>
  32 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
  33
  34 ---
  35  drivers/mfd/intel-lpss-pci.c |   25 +++++++++++++++----------
  36  1 file changed, 15 insertions(+), 10 deletions(-)
  37
  38 --- a/drivers/mfd/intel-lpss-pci.c
  39 +++ b/drivers/mfd/intel-lpss-pci.c
  40 @@ -124,6 +124,11 @@ static const struct intel_lpss_platform_
  41         .properties = apl_i2c_properties,
  42  };
  43
  44 +static const struct intel_lpss_platform_info cnl_i2c_info = {
  45 +       .clk_rate = 216000000,
  46 +       .properties = spt_i2c_properties,
  47 +};
  48 +
  49  static const struct pci_device_id intel_lpss_pci_ids[] = {
  50         /* BXT A-Step */
  51         { PCI_VDEVICE(INTEL, 0x0aac), (kernel_ulong_t)&bxt_i2c_info },
  52 @@ -207,13 +212,13 @@ static const struct pci_device_id intel_
  53         { PCI_VDEVICE(INTEL, 0x9daa), (kernel_ulong_t)&spt_info },
  54         { PCI_VDEVICE(INTEL, 0x9dab), (kernel_ulong_t)&spt_info },
  55         { PCI_VDEVICE(INTEL, 0x9dfb), (kernel_ulong_t)&spt_info },
  56 -       { PCI_VDEVICE(INTEL, 0x9dc5), (kernel_ulong_t)&spt_i2c_info },
  57 -       { PCI_VDEVICE(INTEL, 0x9dc6), (kernel_ulong_t)&spt_i2c_info },
  58 +       { PCI_VDEVICE(INTEL, 0x9dc5), (kernel_ulong_t)&cnl_i2c_info },
  59 +       { PCI_VDEVICE(INTEL, 0x9dc6), (kernel_ulong_t)&cnl_i2c_info },
  60         { PCI_VDEVICE(INTEL, 0x9dc7), (kernel_ulong_t)&spt_uart_info },
  61 -       { PCI_VDEVICE(INTEL, 0x9de8), (kernel_ulong_t)&spt_i2c_info },
  62 -       { PCI_VDEVICE(INTEL, 0x9de9), (kernel_ulong_t)&spt_i2c_info },
  63 -       { PCI_VDEVICE(INTEL, 0x9dea), (kernel_ulong_t)&spt_i2c_info },
  64 -       { PCI_VDEVICE(INTEL, 0x9deb), (kernel_ulong_t)&spt_i2c_info },
  65 +       { PCI_VDEVICE(INTEL, 0x9de8), (kernel_ulong_t)&cnl_i2c_info },
  66 +       { PCI_VDEVICE(INTEL, 0x9de9), (kernel_ulong_t)&cnl_i2c_info },
  67 +       { PCI_VDEVICE(INTEL, 0x9dea), (kernel_ulong_t)&cnl_i2c_info },
  68 +       { PCI_VDEVICE(INTEL, 0x9deb), (kernel_ulong_t)&cnl_i2c_info },
  69         /* SPT-H */
  70         { PCI_VDEVICE(INTEL, 0xa127), (kernel_ulong_t)&spt_uart_info },
  71         { PCI_VDEVICE(INTEL, 0xa128), (kernel_ulong_t)&spt_uart_info },
  72 @@ -240,10 +245,10 @@ static const struct pci_device_id intel_
  73         { PCI_VDEVICE(INTEL, 0xa32b), (kernel_ulong_t)&spt_info },
  74         { PCI_VDEVICE(INTEL, 0xa37b), (kernel_ulong_t)&spt_info },
  75         { PCI_VDEVICE(INTEL, 0xa347), (kernel_ulong_t)&spt_uart_info },
  76 -       { PCI_VDEVICE(INTEL, 0xa368), (kernel_ulong_t)&spt_i2c_info },
  77 -       { PCI_VDEVICE(INTEL, 0xa369), (kernel_ulong_t)&spt_i2c_info },
  78 -       { PCI_VDEVICE(INTEL, 0xa36a), (kernel_ulong_t)&spt_i2c_info },
  79 -       { PCI_VDEVICE(INTEL, 0xa36b), (kernel_ulong_t)&spt_i2c_info },
  80 +       { PCI_VDEVICE(INTEL, 0xa368), (kernel_ulong_t)&cnl_i2c_info },
  81 +       { PCI_VDEVICE(INTEL, 0xa369), (kernel_ulong_t)&cnl_i2c_info },
  82 +       { PCI_VDEVICE(INTEL, 0xa36a), (kernel_ulong_t)&cnl_i2c_info },
  83 +       { PCI_VDEVICE(INTEL, 0xa36b), (kernel_ulong_t)&cnl_i2c_info },
  84         { }
  85  };
  86  MODULE_DEVICE_TABLE(pci, intel_lpss_pci_ids);