releases/4.14.53/mips-bcm47xx-enable-74k-core-externalsync-for-pcie-erratum.patch

   1 From 2a027b47dba6b77ab8c8e47b589ae9bbc5ac6175 Mon Sep 17 00:00:00 2001
   2 From: Tokunori Ikegami <ikegami@allied-telesis.co.jp>
   3 Date: Sun, 3 Jun 2018 23:02:01 +0900
   4 Subject: MIPS: BCM47XX: Enable 74K Core ExternalSync for PCIe erratum
   5 MIME-Version: 1.0
   6 Content-Type: text/plain; charset=UTF-8
   7 Content-Transfer-Encoding: 8bit
   8
   9 From: Tokunori Ikegami <ikegami@allied-telesis.co.jp>
  10
  11 commit 2a027b47dba6b77ab8c8e47b589ae9bbc5ac6175 upstream.
  12
  13 The erratum and workaround are described by BCM5300X-ES300-RDS.pdf as
  14 below.
  15
  16   R10: PCIe Transactions Periodically Fail
  17
  18     Description: The BCM5300X PCIe does not maintain transaction ordering.
  19                  This may cause PCIe transaction failure.
  20     Fix Comment: Add a dummy PCIe configuration read after a PCIe
  21                  configuration write to ensure PCIe configuration access
  22                  ordering. Set ES bit of CP0 configu7 register to enable
  23                  sync function so that the sync instruction is functional.
  24     Resolution:  hndpci.c: extpci_write_config()
  25                  hndmips.c: si_mips_init()
  26                  mipsinc.h CONF7_ES
  27
  28 This is fixed by the CFE MIPS bcmsi chipset driver also for BCM47XX.
  29 Also the dummy PCIe configuration read is already implemented in the
  30 Linux BCMA driver.
  31
  32 Enable ExternalSync in Config7 when CONFIG_BCMA_DRIVER_PCI_HOSTMODE=y
  33 too so that the sync instruction is externalised.
  34
  35 Signed-off-by: Tokunori Ikegami <ikegami@allied-telesis.co.jp>
  36 Reviewed-by: Paul Burton <paul.burton@mips.com>
  37 Acked-by: Hauke Mehrtens <hauke@hauke-m.de>
  38 Cc: Chris Packham <chris.packham@alliedtelesis.co.nz>
  39 Cc: Rafał Miłecki <zajec5@gmail.com>
  40 Cc: linux-mips@linux-mips.org
  41 Cc: stable@vger.kernel.org
  42 Patchwork: https://patchwork.linux-mips.org/patch/19461/
  43 Signed-off-by: James Hogan <jhogan@kernel.org>
  44 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
  45
  46 ---
  47  arch/mips/bcm47xx/setup.c        |    6 ++++++
  48  arch/mips/include/asm/mipsregs.h |    3 +++
  49  2 files changed, 9 insertions(+)
  50
  51 --- a/arch/mips/bcm47xx/setup.c
  52 +++ b/arch/mips/bcm47xx/setup.c
  53 @@ -212,6 +212,12 @@ static int __init bcm47xx_cpu_fixes(void
  54                  */
  55                 if (bcm47xx_bus.bcma.bus.chipinfo.id == BCMA_CHIP_ID_BCM4706)
  56                         cpu_wait = NULL;
  57 +
  58 +               /*
  59 +                * BCM47XX Erratum "R10: PCIe Transactions Periodically Fail"
  60 +                * Enable ExternalSync for sync instruction to take effect
  61 +                */
  62 +               set_c0_config7(MIPS_CONF7_ES);
  63                 break;
  64  #endif
  65         }
  66 --- a/arch/mips/include/asm/mipsregs.h
  67 +++ b/arch/mips/include/asm/mipsregs.h
  68 @@ -680,6 +680,8 @@
  69  #define MIPS_CONF7_WII         (_ULCAST_(1) << 31)
  70
  71  #define MIPS_CONF7_RPS         (_ULCAST_(1) << 2)
  72 +/* ExternalSync */
  73 +#define MIPS_CONF7_ES          (_ULCAST_(1) << 8)
  74
  75  #define MIPS_CONF7_IAR         (_ULCAST_(1) << 10)
  76  #define MIPS_CONF7_AR          (_ULCAST_(1) << 16)
  77 @@ -2745,6 +2747,7 @@ __BUILD_SET_C0(status)
  78  __BUILD_SET_C0(cause)
  79  __BUILD_SET_C0(config)
  80  __BUILD_SET_C0(config5)
  81 +__BUILD_SET_C0(config7)
  82  __BUILD_SET_C0(intcontrol)
  83  __BUILD_SET_C0(intctl)
  84  __BUILD_SET_C0(srsmap)