releases/4.14.60/spi-sh-msiof-fix-setting-sirmdr1.syncac-to-match-sitmdr1.syncac.patch

   1 From foo@baz Sat Jul 28 10:25:26 CEST 2018
   2 From: Geert Uytterhoeven <geert+renesas@glider.be>
   3 Date: Wed, 23 May 2018 11:02:04 +0200
   4 Subject: spi: sh-msiof: Fix setting SIRMDR1.SYNCAC to match SITMDR1.SYNCAC
   5
   6 From: Geert Uytterhoeven <geert+renesas@glider.be>
   7
   8 [ Upstream commit 0921e11e1e12802ae0a3c19cb02e33354ca51967 ]
   9
  10 According to section 59.2.4 MSIOF Receive Mode Register 1 (SIRMDR1) in
  11 the R-Car Gen3 datasheet Rev.1.00, the value of the SIRMDR1.SYNCAC bit
  12 must match the value of the SITMDR1.SYNCAC bit.  However,
  13 sh_msiof_spi_setup() changes only the latter.
  14
  15 Fix this by updating the SIRMDR1 register like the SITMDR1 register,
  16 taking into account register bits that exist in SITMDR1 only.
  17
  18 Reported-by: Renesas BSP team via Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
  19 Fixes: 7ff0b53c4051145d ("spi: sh-msiof: Avoid writing to registers from spi_master.setup()")
  20 Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
  21 Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
  22 Signed-off-by: Mark Brown <broonie@kernel.org>
  23 Signed-off-by: Sasha Levin <alexander.levin@microsoft.com>
  24 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
  25 ---
  26  drivers/spi/spi-sh-msiof.c |    6 ++++--
  27  1 file changed, 4 insertions(+), 2 deletions(-)
  28
  29 --- a/drivers/spi/spi-sh-msiof.c
  30 +++ b/drivers/spi/spi-sh-msiof.c
  31 @@ -555,14 +555,16 @@ static int sh_msiof_spi_setup(struct spi
  32
  33         /* Configure native chip select mode/polarity early */
  34         clr = MDR1_SYNCMD_MASK;
  35 -       set = MDR1_TRMD | TMDR1_PCON | MDR1_SYNCMD_SPI;
  36 +       set = MDR1_SYNCMD_SPI;
  37         if (spi->mode & SPI_CS_HIGH)
  38                 clr |= BIT(MDR1_SYNCAC_SHIFT);
  39         else
  40                 set |= BIT(MDR1_SYNCAC_SHIFT);
  41         pm_runtime_get_sync(&p->pdev->dev);
  42         tmp = sh_msiof_read(p, TMDR1) & ~clr;
  43 -       sh_msiof_write(p, TMDR1, tmp | set);
  44 +       sh_msiof_write(p, TMDR1, tmp | set | MDR1_TRMD | TMDR1_PCON);
  45 +       tmp = sh_msiof_read(p, RMDR1) & ~clr;
  46 +       sh_msiof_write(p, RMDR1, tmp | set);
  47         pm_runtime_put(&p->pdev->dev);
  48         p->native_cs_high = spi->mode & SPI_CS_HIGH;
  49         p->native_cs_inited = true;